CN205811849U - The charge pump system that driving force is stable - Google Patents
The charge pump system that driving force is stable Download PDFInfo
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- CN205811849U CN205811849U CN201620756790.0U CN201620756790U CN205811849U CN 205811849 U CN205811849 U CN 205811849U CN 201620756790 U CN201620756790 U CN 201620756790U CN 205811849 U CN205811849 U CN 205811849U
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Abstract
The utility model discloses the charge pump system that a kind of driving force is stable, including clock generation circuit, electric charge pump, voltage adjuster；The control end of clock generation circuit connects logic control circuit, difference Joining Technology observation circuit and supply voltage monitoring circuit on logic control circuit；This utility model is capable of the automatic monitoring to process corner and supply voltage, produces the clock signal that frequency is different, the impact caused electric charge pump driving force because of process corner and supply voltage with reverse compensation according to the difference of process corner and the different of supply voltage.The clock signal frequency produced under the conditions of fast process corner or high power supply voltage is low, the clock signal frequency produced under the conditions of slow process corner or low supply voltage is high, so that it is guaranteed that electric charge pump all has roughly the same driving force under different process angle and different electrical power voltage conditions.
Description
[technical field]
This utility model relates to a kind of charge pump system that can stably provide driving force.
[background technology]
Electric charge pump, for realizing the builtin voltage higher than supply voltage, is widely used in the chip such as memorizer, display driving
In.Charge pump system is mainly made up of clock generation circuit, electric charge pump and voltage adjuster, is usual as shown in FIG. 1A and 1B
Two kinds of frameworks.
In figure ia, clock generation circuit generation oscillator signal clk0, and it is connected to the input end of clock CK of electric charge pump, electricity
Lotus delivery side of pump is connected to output signal Vout.Output signal Vout may be output to filter capacitor C and load.Voltage Cortrol
Bleeder circuit and comparator that device is typically made up of with resistance R2 resistance R1 are constituted, as shown in Figure 2.Voltage adjuster will output
Compare with reference voltage Vref after signal Vout dividing potential drop, generate control signal En_osc, and be connected to clock generation circuit
Enable Pin.
When oscillator signal Clk0 maintains fixing level, output signal Vout is gradually reduced；Otherwise, work as oscillator signal
Clk0 is when low and high level changes, and according to the rising edge of oscillator signal Clk0, output signal Vout can be made to be gradually increasing.
In fig. ib, clock generation circuit generates oscillator signal clk0, and is connected to the second input with door and, with
It is connected to the signal En_osc phase with the first input end of door and and rear generation signal Clk, and the clock being connected to electric charge pump is defeated
Entering and hold CK, electric charge delivery side of pump is connected to output signal Vout.Output signal Vout may be output to filter capacitor C with negative
Carry.Voltage adjuster compares after output signal Vout dividing potential drop with reference voltage Vref, generates control signal En_osc, and
It is connected to and the first input end of door and.
When oscillator signal Clk maintains fixing level, output signal Vout is gradually reduced；Otherwise, work as oscillator signal
Clk is when low and high level changes, and according to the rising edge of oscillator signal Clk, output signal Vout can be made to be gradually increasing.
If the driving force of electric charge pump is less than load power consumption, then output signal Vout will not reach required voltage
Value.If the driving force of electric charge pump is more than load power consumption, then unnecessary electric current will flow in capacitor C, make electric charge pump
Ripple occurs in output signal Vout.Driving force is more more than load power consumption, and the ripple in output signal Vout is the biggest.
The driving force of electric charge pump is affected very big by supply voltage and process corner, under high power supply voltage or fast process corner,
The driving force of electric charge pump can be big；Otherwise, under low supply voltage or slow process corner, the driving force of electric charge pump can be little.
Generally to ensure in worst case, i.e. under the conditions of low supply voltage, slow process corner, the driving force of electric charge pump is with negative
Carrying power consumption equal or bigger, so under the conditions of other is any, electric charge pump can have enough driving forces.But, so draw
The problem entered is: under other non-worst case, electric charge pump has excessive driving force, thus causes charge pump output signal
The ripple that upper appearance is excessive.Especially under high power supply voltage, fast process corner, the driving force of electric charge pump is maximum, accordingly its
Ripple in output signal is the most maximum.
[utility model content]
The purpose of this utility model is to solve available circuit driving force and changes asking greatly with supply voltage and process corner
Topic, it is provided that the charge pump system that a kind of driving force is stable.
To achieve these goals, this utility model is achieved by the following technical solutions:
The charge pump system that a kind of driving force is stable, including clock generation circuit, electric charge pump and voltage adjuster；Electricity
The clock pulse input terminal CK of lotus pump receives the oscillator signal Clk0 from clock generation circuit, electric charge delivery side of pump output letter
Number Vout, output signal Vout exports respectively to filter capacitor C, load and voltage adjuster；Voltage adjuster will output
Compare with reference voltage Vref after signal Vout dividing potential drop, produce control signal En_osc and export, control signal En_osc
Export Enable Pin EN to clock generation circuit；The configuration end TR of clock generation circuitinThe even outfan of logic control circuit
TRout, the input P of logic control circuitinConnect output signal sense_p of process corner observation circuit, logic control circuit defeated
Enter to hold VinConnect output signal sense_v of supply voltage monitoring circuit；Wherein,
Process corner observation circuit: for monitoring the process corner residing for current chip；
Supply voltage monitoring circuit: for monitoring the height of current power voltage；
Logic control circuit: according to process corner observation circuit and the result of supply voltage monitoring circuit, produce different joining
Confidence number, controls the frequency of clock generation circuit output clock signal.
This utility model is further improved by:
Control signal En_osc that described voltage adjuster produces does not exports Enable Pin EN to clock generation circuit, but
Being directly output to the first input end A1 with door and1, clock generation circuit receives configuration signal trim of logic control circuit,
Generate oscillator signal Clk0, oscillator signal Clk0 to export to the second input A2 with door and1, with door and1 output vibration letter
Number Clk to the clock pulse input terminal CK of electric charge pump.
Described supply voltage monitoring circuit includes 1 output circuit and 2 output circuits, and 1 output circuit includes first
Potentiometer, comparator comp_v1 and the first buffer, 2 output circuits include the second potentiometer, comparator comp_v2 and
Two buffers；One termination supply voltage vext of the first potentiometer, other end ground connection, and the first potentiometer output sampled signal
The positive input of vfb1 to comparator comp_v1, outfan output signal v1 of comparator comp_v1；Second potentiometer
One termination supply voltage vext, other end ground connection, and the second potentiometer output sampled signal vfb2 is to comparator comp_v2 just
To input, outfan output signal v2 of comparator comp_v2；Comparator comp_v1's and comparator comp_v2 is the most defeated
Enter end and all meet reference voltage vref；Output signal v1 passes through the first buffer output signal output sense_v1, output signal v2
By the second buffer output signal output sense_v2；Output signal sense_v1 and the output of output signal sense_v2
Result is as follows:
If sampled signal vfb1 is more than reference voltage vref, output signal sense_v1=1；
If sampled signal vfb1 is less than or equal to reference voltage vref, output signal sense_v1=0；
If sampled signal vfb2 is more than reference voltage vref, output signal sense_v2=1；
If sampled signal vfb2 is less than or equal to reference voltage vref, output signal sense_v2=0.
Described first potentiometer includes resistance R0, resistance R1 and the resistance R2 being sequentially connected in series, one end ground connection of resistance R0, electricity
Node output sampled signal vfb1 that one termination the supply voltage vext, resistance R2 and resistance R1 of resistance R2 is connected；Second potentiometer
Including the resistance R3 being sequentially connected in series, resistance R4 and resistance R5, one end ground connection of resistance R3, a termination supply voltage of resistance R5
Node output sampled signal vfb2 that vext, resistance R5 and resistance R4 are connected.
Described supply voltage monitoring circuit also include m-2 structure and 1 output circuit and 2 output circuits identical
3 to m position output circuit, and m is the positive integer more than 2；One end of the potentiometer of each output circuit all connects supply voltage
Vext, other end ground connection, the positive input of each comparator connect sampled signal vfb3 of each output circuit, vfb4 ...,
Vfbm, reverse input end meets reference voltage vref；3rd to m position output circuit outfan respectively output signal sense_v3,
Sense_v4 ..., sense_vm, output signal sense_v3, sense_v4 ..., sense_vm output result with defeated
The output result going out signal sense_v1 and sense_v2 is similar.
Described output signal v1 is also through the grid end of phase inverter inv1 output to nmos pipe n1, the drain electrode of nmos pipe n1 and source
The both sides of pole connecting resistance R0；Output signal v2 is also through the grid end of phase inverter inv4 output to nmos pipe n2, the leakage of nmos pipe n2
Pole and the both sides of source electrode connecting resistance R3.
Described supply voltage monitoring circuit also include m-2 structure and 1 output circuit and 2 output circuits identical
3 to m position output circuit, and m is the positive integer more than 2；One end of the potentiometer of each output circuit all connects supply voltage
Vext, other end ground connection, the positive input of each comparator connect sampled signal vfb3 of each output circuit, vfb4 ...,
Vfbm, reverse input end meets reference voltage vref；3rd to m position output circuit outfan respectively output signal sense_v3,
Sense_v4 ..., sense_vm, output signal sense_v3, sense_v4 ..., sense_vm output result with defeated
The output result going out signal sense_v1 and sense_v2 is similar.
Described process corner observation circuit include ring oscillator, with door and2, enumerator, comparator comp_p1 and ratio
Relatively device comp_p2, the outfan of comparator comp_p1 and comparator comp_p2 is respectively process corner observation circuit 1 output
With 2 outputs；Ring oscillator produces oscillator signal clk_gen, oscillator signal clk_gen and control signal ctrl_meas connects
Being connected to and door and2, produce signal clk_count, wherein, the high level time of control signal ctrl_meas is T_base；?
Transmitting it to the input of enumerator after signal clk_count, its periodicity is counted and exports result by enumerator
cycle_count；Cycle_count passes through comparator comp_p1 and comparator comp_p2 with ring oscillator at time T_
Periodicity cycle_base1 and periodicity cycle_base2 in base compare, and obtain the output of process corner observation circuit
The output result of signal sense_p1 and output signal sense_p2, output signal sense_p1 and output signal sense_p2 is such as
Under:
If cycle_count is less than or equal to cycle_base1, output signal sense_p1=0；
If cycle_count is more than cycle_base1, output signal sense_p1=1；
If cycle_count is less than or equal to cycle_base2, output signal sense_p2=0；
If cycle_count is more than cycle_base2, output signal sense_p2=1.
Described process corner observation circuit also includes n-2 comparator, and the outfan of this n-2 comparator is respectively process corner
3rd to the n-th output of observation circuit, n is the positive integer more than 2；The input of each comparator meets cycle_ respectively
Base3, cycle_base4 ..., cycle_basen, another input of each comparator connects the most simultaneously simultaneously
Cycle_count, outfan output signal sense_p3, sense_p4 ..., sense_pn, output signal sense_p3,
Sense_p4 ..., the output result of sense_pn and output signal sense_p1 and the output result of output signal sense_p2
Similar.
Described logic control circuit is produced configuration signal trim and can be realized by following three kinds of modes:
1) the input P of logic control circuitinReceive output signal sense_p of process corner observation circuit, produce configuration
Signal trim；
2) the input V of logic control circuitinReceiving output signal sense_v of supply voltage monitoring circuit, generation is joined
Confidence trim；
3) the input P of logic control circuitinWith input VinReceive the output signal of process corner observation circuit simultaneously
Sense_p and output signal sense_v of supply voltage monitoring circuit, produce configuration signal trim.
Compared with prior art, this utility model has the advantages that
This utility model is capable of the automatic monitoring to process corner and supply voltage, according to difference and the power supply of process corner
The different of voltage produce the clock signal that frequency is different, with reverse compensation because process corner and supply voltage are to electric charge pump driving force
The impact caused.The clock signal frequency produced under the conditions of fast process corner or high power supply voltage is low, at slow process corner or low electricity
The clock signal frequency produced under the voltage conditions of source is high, so that it is guaranteed that electric charge pump is at different process angle and different electrical power voltage conditions
Under all there is roughly the same driving force.
[accompanying drawing explanation]
Figure 1A is a kind of circuit theory diagrams of existing charge pump system；
Figure 1B is the second circuit theory diagrams of existing charge pump system；
Fig. 2 is the ultimate principle figure of voltage adjuster；
Fig. 3 A is a kind of circuit theory diagrams of charge pump system described in the utility model；
Fig. 3 B is the second circuit theory diagrams of charge pump system described in the utility model；
Fig. 4 is the circuit theory diagrams of electric source monitoring circuit described in the utility model；
Fig. 5 is the circuit theory diagrams of process corner observation circuit described in the utility model；
Fig. 6 is that the oscillator signal in process corner observation circuit described in the utility model produced ring oscillator carries out pre-
The schematic diagram processed.
[detailed description of the invention]
Below in conjunction with the accompanying drawings this utility model is described in further detail:
Seeing Fig. 3-Fig. 6, the charge pump system that this utility model driving force is stable, including clock generation circuit, electric charge
Pump and voltage adjuster；The clock pulse input terminal CK of electric charge pump receives the oscillator signal Clk0 from clock generation circuit,
Electric charge delivery side of pump output signal Vout, output signal Vout exports respectively to filter capacitor C, load and Voltage Cortrol
Device；Voltage adjuster compares after output signal Vout dividing potential drop with reference voltage Vref, produces control signal En_osc also
Output, Enable Pin EN of control signal En_osc output to clock generation circuit；The configuration end TR of clock generation circuitinEven logic
The outfan TR of control circuitout, the input P of logic control circuitinConnect output signal sense_p of process corner observation circuit,
The input V of logic control circuitinConnect output signal sense_v of supply voltage monitoring circuit；Wherein,
Clock generation circuit: generate the clock signal required for charge pump.
Electric charge pump: under the effect of input clock signal rising edge, makes output signal Vout be gradually increasing.
Voltage adjuster: compare after output signal Vout dividing potential drop with reference voltage Vref, produces control signal En_
osc。
Process corner observation circuit: monitoring process corner residing for current chip.
Supply voltage monitoring circuit: the height of monitoring current power voltage.
Logic control circuit: according to process corner observation circuit and the result of supply voltage monitoring circuit, produce different joining
Confidence number, controls the frequency of clock generation circuit output clock signal.
As shown in Figure 4, supply voltage monitoring circuit includes 1 output circuit and 2 output circuits；1 output circuit bag
Including the first potentiometer, comparator comp_v1 and the first buffer, 2 output circuits include the second potentiometer, comparator comp_
V2 and the second buffer；First potentiometer includes resistance R0, resistance R1 and the resistance R2 being sequentially connected in series, a termination of resistance R0
Ground, node output sampled signal vfb1 that termination a supply voltage vext, resistance R2 and resistance R1 of resistance R2 is connected, sampling letter
Number vfb1 is connected to the positive input of comparator comp_v1；Second potentiometer include the resistance R3, the resistance R4 that are sequentially connected in series and
One end ground connection of resistance R5, resistance R3, a termination supply voltage vext of resistance R5, the node that resistance R5 is connected with resistance R4 is defeated
Going out sampled signal vfb2, sampled signal vfb2 is connected to the positive input of comparator comp_v2；Comparator comp_v1 and ratio
The relatively reverse input end of device comp_v2 all connects outfan output signal v1 of reference voltage vref, comparator comp_v1, compares
Outfan output signal v2 of device comp_v2；
Supply voltage vext is sampled by supply voltage monitoring circuit by the first potentiometer and the second potentiometer, will adopt
Sample signal vfb1 and vfb2 compares with reference voltage vref；When sampled signal vfb1 is more than reference voltage vref, compare
Output signal v1 of device comp_v1 is high level；When sampled signal vfb1 is less than or equal to reference voltage vref, comparator
Output signal v1 of comp_v1 is low level；In like manner, when sampled signal vfb2 is more than reference voltage vref, comparator comp_
Output signal v2 of v2 is high level；When sampled signal vfb2 is less than or equal to reference voltage vref, comparator comp_v2's
Output signal v2 is low level；Signal v1 obtains supply voltage monitoring electricity after the buffer by phase inverter inv2 and inv3 composition
First output signal sense_v1 on road, signal v2 obtains supply voltage after the buffer by phase inverter inv5 and inv6 composition
Second output signal sense_v2 of observation circuit.In supply voltage monitoring circuit, nmos pipe n1 and phase inverter inv1, nmos
Pipe n2 and phase inverter inv4 is used for realizing lag function, to avoid causing supply voltage monitoring electricity because of supply voltage vext shake
Road output instability.Concrete:
If supply voltage vext is relatively low time initial, sampled signal vfb1 is less than reference voltage vref, then comparator
Comp_v1 output signal v1 is low level, and signal v1b is high level, and nmos pipe n1 turns on, and resistance R0 is bypassed to ground, works as electricity
When source voltage vext gradually uprises, only it is increased to more than vth1_rise=(1+R2/R1) vref, comparator comp_v1 when it
Just can overturn；In like manner, if initial time supply voltage vext relatively low, sampled signal vfb2 is less than reference voltage vref, then compare
Device comp_v2 output signal v2 is low level, and signal v2b is high level, and nmos pipe n2 turns on, and resistance R3 is bypassed to ground, when
When supply voltage vext gradually uprises, only it is increased to more than vth2_rise=(1+R5/R4) vref, comparator comp_ when it
V2 just can overturn.
If supply voltage vext is higher time initial, sampled signal vfb1 is more than reference voltage vref, then comparator comp_
V1 output signal v1 is high level, and signal v1b is low level, and nmos pipe n1 disconnects, when supply voltage vext gradually step-down, only
Have and just can overturn when it drops below vth1_fall=(1+R2/ (R1+R0)) vref, comparator comp_v1；In like manner, if
Time initial, supply voltage vext is higher, and sampled signal vfb2 is more than reference voltage vref, then comparator comp_v2 output signal v2
For high level, signal v2b is low level, and nmos pipe n2 disconnects, and when supply voltage vext gradually step-down, is only reduced to when it
Just can overturn less than vth2_fall=(1+R5/ (R4+R3)) vref, comparator comp_v2.
This utility model supply voltage monitoring circuit can also expand to the output of m position, and concrete structure also includes m-2 structure
3rd identical with 1 output circuit and 2 output circuits is to m position output circuit, and m is the positive integer more than 2；Each is defeated
The one end of the potentiometer going out circuit all meets supply voltage vext, other end ground connection, and the positive input of comparator connects each defeated respectively
Going out sampled signal vfb3 of circuit, vfb4 ..., vfbm, reverse input end meets reference voltage vref；3rd to m position output electricity
The outfan on road output signal sense_v3, sense_v4 ..., sense_vm, output signal sense_v3, sense_ respectively
V4 ..., sense_vm output result similar with the output result of output signal sense_v1 and sense_v2.Specifically
, as a example by output signal sense_v3, if initial time supply voltage vext relatively low, output signal sense_v3 is low electricity
Flat, when supply voltage vext gradually uprises, only when it is increased to more than vth3_rise, output signal sense_v3 is
Can overturn as high level；If power supply vext is higher time initial, output signal sense_v3 is high level, as supply voltage vext
Gradually during step-down, only when it drops below vth3_fall, output signal sense_v3 just can overturn as low level.
As it is shown in figure 5, process corner observation circuit by ring oscillator and door and2, enumerator, comparator comp_p1 with
And comparator comp_p2 composition.Ring oscillator produces oscillator signal clk_gen, and its frequency height is completely by process corner level
Determining, when chip is in fast process corner, the frequency of oscillator signal clk_gen is high；Otherwise, when being in slow process corner, vibration
The frequency of signal clk_gen is low.Control signal ctrl_meas is a pulse signal, is used for carrying out oscillator signal clk_gen
Pretreatment, its high level lasting time is T_base.Oscillator signal clk_gen and control signal ctrl_meas are carried out and operation
Rear generation signal clk_count, is its oscillogram as shown in Figure 6.Pretreated oscillator signal clk_count is connected to counting
The input of device, counts its periodicity, and result is cycle_count.In time T_base, if ring oscillator
Periodicity less than or equal to periodicity cycle_base1, then defining process corner now is slow process corner；At time T_base
In, if the periodicity of ring oscillator is more than periodicity cycle_base1 and less than or equal to periodicity cycle_base2,
Then defining process corner now is typical process angle；In time T_base, if the periodicity of ring oscillator is more than the cycle
Number cycle_base2, then defining process corner now is fast process corner.Cycle_count is by comparator comp_p1 and compares
Device comp_p2 and periodicity cycle_base1 and periodicity cycle_base2 compares, and obtains process corner observation circuit
Output signal sense_p1 and output signal sense_p2；
As fruit chip is in slow process corner, then:
Cycle_count is less than or equal to cycle_base1, output signal sense_p1=0；
Cycle_count is less than cycle_base2, output signal sense_p2=0.
As fruit chip is in typical process angle, then:
Cycle_count is more than cycle_base1, output signal sense_p1=1.
Cycle_count is less than or equal to cycle_base2, and output signal sense_p2=0 such as fruit chip is in fast technique
Angle, then:
Cycle_count is more than cycle_base1, output signal sense_p1=1；
Cycle_count is more than or equal to cycle_base2, output signal sense_p1=1.
This utility model process corner observation circuit can also expand to the output of n position, and physical circuit includes n-2 comparator,
The outfan of this n-2 comparator is respectively the 3rd to the n-th output of process corner observation circuit, and n is the positive integer more than 2；Often
The input of one comparator meets cycle_base3, cycle_base4 ..., cycle_basen respectively, simultaneously each
Another input of comparator meets cycle_count, outfan output signal sense_p3, sense_p4 the most simultaneously ...,
Sense_pn, output signal sense_p3, sense_p4 ..., the output result of sense_pn and output signal sense_p1 and
The output result of output signal sense_p2 is similar.Concrete, as a example by output signal sense_p3, work as cycle_count
During less than or equal to cycle_base3, output signal sense_p3=0；When cycle_count is more than cycle_base3, output
Signal sense_p3=1.
Logic control circuit exports result sense_v and the output of process corner observation circuit to supply voltage monitoring circuit
The process of result sense_p, produces configuration signal trim, controls the frequency of clock generation circuit output clock clk0.Logic
Control circuit is produced configuration signal trim and can be realized by following three kinds of modes:
1) the input P of logic control circuitinReceive output signal sense_p of process corner observation circuit, produce configuration
Signal trim；
2) the input V of logic control circuitinReceiving output signal sense_v of supply voltage monitoring circuit, generation is joined
Confidence trim；
3) the input P of logic control circuitinWith input VinReceive the output signal of process corner observation circuit simultaneously
Sense_p and output signal sense_v of supply voltage monitoring circuit, produce configuration signal trim.
Hereby it is achieved that make clock produce by supply voltage monitoring circuit, process corner observation circuit and logic control circuit
The output clock clk0 of raw circuit has different frequencies of oscillation under the conditions of different supply voltages, different process corner.Table 1
Shown in be a truth table of supply voltage monitoring circuit, table 2 is a truth table of process corner observation circuit, and table 3A is logic
Control circuit only receives the truth table during output signal of process corner observation circuit, and table 3B is that logic control circuit only receives power supply
The truth table during output signal of electric voltage observation circuit, table 3C is that logic control circuit receives process corner observation circuit and power supply electricity
Press the truth table during output signal of observation circuit.
The truth table of table 1 electric source monitoring circuit:
| Supply voltage | sense_v1 | sense_v2 |
| Low | 0 | 0 |
| Typical case | 0 | 1 |
| High | 1 | 1 |
The truth table of table 2 process corner observation circuit:
| Process corner | sense_p1 | sense_p2 |
| Slowly | 0 | 0 |
| Typical case | 0 | 1 |
| Hurry up | 1 | 1 |
Table 3A logic control circuit only receives the truth table during output signal of process corner observation circuit:
Table 3B logic control circuit only receives the truth table during output signal of supply voltage monitoring circuit:
True when table 3C logic control circuit receives the output signal of process corner observation circuit and supply voltage monitoring circuit
Value table:
The output clock Clk0 of this utility model clock generation circuit can be directly connected to the input end of clock of electric charge pump
CK, electric charge pump makes its output signal Vout be gradually increasing, as shown in Figure 3A under the effect of clock signal Clk0 rising edge.
Or, the output clock Clk0 of clock generation circuit and the output signal En_osc phase of voltage adjuster with after obtain
Signal Clk, as the input clock of electric charge pump, electric charge pump rises thereon and makes output signal Vout be gradually increasing under the effect on edge,
As shown in Figure 3 B.
Voltage adjuster receives output signal Vout of electric charge pump, produces feedback signal Vfb by resitstance voltage divider, by it
Compare with reference voltage Vref, produce control signal En_osc.When feedback signal Vfb is more than reference voltage Vref, En_
Osc is low；Otherwise, when feedback signal Vfb is less than reference voltage Vref, En_osc is high.Control signal En_osc as time
Clock produces the signal that enables of circuit and controls the work of clock generation circuit, as shown in Figure 3A.Or, clock generation circuit work always
Making, the output clock Clk0 of control signal En_osc and clock generation circuit makees and operation, and can control clock Clk0 normally pass
It is delivered to the input end of clock of electric charge pump, as shown in Figure 3 B.
Above content only illustrates technological thought of the present utility model, it is impossible to limit protection model of the present utility model with this
Enclose, every according to the technological thought that the utility model proposes, any change done on the basis of technical scheme, each fall within this reality
Within protection domain with novel claims.
Claims (10)
1. the charge pump system that driving force is stable, it is characterised in that include clock generation circuit, electric charge pump and Voltage Cortrol
Device；The clock pulse input terminal CK of electric charge pump receives the oscillator signal Clk0 from clock generation circuit, electric charge delivery side of pump
Output signal Vout, output signal Vout exports respectively to filter capacitor C, load and voltage adjuster；Voltage adjuster
Compare after output signal Vout dividing potential drop with reference voltage Vref, produce control signal En_osc and export, control signal
En_osc exports Enable Pin EN to clock generation circuit；The configuration end TR of clock generation circuitinEven logic control circuit is defeated
Go out to hold TRout, the input P of logic control circuitinConnect output signal sense_p of process corner observation circuit, logic control circuit
Input VinConnect output signal sense_v of supply voltage monitoring circuit；Wherein,
Process corner observation circuit: for monitoring the process corner residing for current chip；
Supply voltage monitoring circuit: for monitoring the height of current power voltage；
Logic control circuit: according to process corner observation circuit and the result of supply voltage monitoring circuit, produce different configuration letters
Number, control the frequency of clock generation circuit output clock signal.
The charge pump system that driving force the most according to claim 1 is stable, it is characterised in that described voltage adjuster produces
Raw control signal En_osc does not export Enable Pin EN to clock generation circuit, but is directly output to and the first of door and1
Input A1, clock generation circuit receives configuration signal trim of logic control circuit, generates oscillator signal Clk0, oscillator signal
Clk0 output is to the second input A2 with door and1, defeated to the clock pulses of electric charge pump with door and1 outputting oscillation signal Clk
Enter to hold CK.
The charge pump system that driving force the most according to claim 1 and 2 is stable, it is characterised in that described supply voltage
Observation circuit includes that 1 output circuit and 2 output circuits, 1 output circuit include the first potentiometer, comparator comp_v1
And first buffer, 2 output circuits include the second potentiometer, comparator comp_v2 and the second buffer；First potentiometer
One termination supply voltage vext, other end ground connection, and the first potentiometer output sampled signal vfb1 is to comparator comp_v1 just
To input, outfan output signal v1 of comparator comp_v1；One termination supply voltage vext of the second potentiometer, another
End ground connection, and the second potentiometer output sampled signal vfb2 is to the positive input of comparator comp_v2, comparator comp_v2
Outfan output signal v2；The reverse input end of comparator comp_v1 and comparator comp_v2 all meets reference voltage vref；
Output signal v1 passes through the first buffer output signal output sense_v1, and output signal v2 is by the second buffer output output
Signal sense_v2；The output result of output signal sense_v1 and output signal sense_v2 is as follows:
If sampled signal vfb1 is more than reference voltage vref, output signal sense_v1=1；
If sampled signal vfb1 is less than or equal to reference voltage vref, output signal sense_v1=0；
If sampled signal vfb2 is more than reference voltage vref, output signal sense_v2=1；
If sampled signal vfb2 is less than or equal to reference voltage vref, output signal sense_v2=0.
The charge pump system that driving force the most according to claim 3 is stable, it is characterised in that described first potentiometer bag
Include resistance R0, resistance R1 and the resistance R2 being sequentially connected in series, one end ground connection of resistance R0, a termination supply voltage of resistance R2
Node output sampled signal vfb1 that vext, resistance R2 and resistance R1 are connected；Resistance R3 that second potentiometer includes being sequentially connected in series,
One end ground connection of resistance R4 and resistance R5, resistance R3, termination a supply voltage vext, resistance R5 of resistance R5 is connected with resistance R4
Node output sampled signal vfb2.
The charge pump system that driving force the most according to claim 4 is stable, it is characterised in that described supply voltage is monitored
Circuit also include m-2 structure and 1 output circuit and 2 output circuits identical the 3rd to m position output circuit, m is for being more than
The positive integer of 2；One end of the potentiometer of each output circuit all meets supply voltage vext, other end ground connection, each comparator
Positive input meets sampled signal vfb3 of each output circuit, vfb4 ..., vfbm, and reverse input end meets reference voltage vref；
3rd to outfan respectively output signal sense_v3, sense_v4 ..., the sense_vm of m position output circuit, output letter
Number sense_v3, sense_v4 ..., output result and output signal sense_v1 and the output of sense_v2 of sense_vm
Result is similar.
The charge pump system that driving force the most according to claim 4 is stable, it is characterised in that described output signal v1 is also
Through the grid end of phase inverter inv1 output to nmos pipe n1, the drain electrode of nmos pipe n1 and the both sides of source electrode connecting resistance R0；Output letter
Number v2 is also through the grid end of phase inverter inv4 output to nmos pipe n2, the drain electrode of nmos pipe n2 and the both sides of source electrode connecting resistance R3.
The charge pump system that driving force the most according to claim 6 is stable, it is characterised in that described supply voltage is monitored
Circuit also include m-2 structure and 1 output circuit and 2 output circuits identical the 3rd to m position output circuit, m is for being more than
The positive integer of 2；One end of the potentiometer of each output circuit all meets supply voltage vext, other end ground connection, each comparator
Positive input meets sampled signal vfb3 of each output circuit, vfb4 ..., vfbm, and reverse input end meets reference voltage vref；
3rd to outfan respectively output signal sense_v3, sense_v4 ..., the sense_vm of m position output circuit, output letter
Number sense_v3, sense_v4 ..., output result and output signal sense_v1 and the output of sense_v2 of sense_vm
Result is similar.
The charge pump system that driving force the most according to claim 1 and 2 is stable, it is characterised in that described process corner is supervised
Slowdown monitoring circuit includes ring oscillator and door and2, enumerator, comparator comp_p1 and comparator comp_p2, comparator
The outfan of comp_p1 and comparator comp_p2 is respectively process corner observation circuit 1 output and 2 outputs；Ring oscillation
Device produces oscillator signal clk_gen, and oscillator signal clk_gen and control signal ctrl_meas are connected to and door and2, produces letter
Number clk_count, wherein, the high level time of control signal ctrl_meas is T_base；Will after obtaining signal clk_count
It transmits the input to enumerator, and its periodicity is counted and exports result cycle_count by enumerator；cycle_
Count is by comparator comp_p1 and comparator comp_p2 and ring oscillator periodicity cycle_ in time T_base
Base1 and periodicity cycle_base2 compares, and obtains output signal sense_p1 and the output letter of process corner observation circuit
Number sense_p2, the output result of output signal sense_p1 and output signal sense_p2 is as follows:
If cycle_count is less than or equal to cycle_base1, output signal sense_p1=0；
If cycle_count is more than cycle_base1, output signal sense_p1=1；
If cycle_count is less than or equal to cycle_base2, output signal sense_p2=0；
If cycle_count is more than cycle_base2, output signal sense_p2=1.
The charge pump system that driving force the most according to claim 8 is stable, it is characterised in that described process corner monitoring electricity
Road also includes n-2 comparator, and the outfan of this n-2 comparator be respectively process corner observation circuit the 3rd to the n-th is defeated
Going out, n is the positive integer more than 2；The input of each comparator connect respectively cycle_base3, cycle_base4 ...,
Cycle_basen, another input of each comparator connects cycle_count, outfan output signal the most simultaneously simultaneously
Sense_p3, sense_p4 ..., sense_pn, output signal sense_p3, sense_p4 ..., the output of sense_pn knot
Fruit is similar with the output result of output signal sense_p1 and output signal sense_p2.
The charge pump system that driving force the most according to claim 1 and 2 is stable, it is characterised in that described logic control
Circuit is produced configuration signal trim and can be realized by following three kinds of modes:
1) the input P of logic control circuitinReceive output signal sense_p of process corner observation circuit, produce configuration signal
trim；
2) the input V of logic control circuitinReceive output signal sense_v of supply voltage monitoring circuit, produce configuration letter
Number trim；
3) the input P of logic control circuitinWith input VinReceive output signal sense_p of process corner observation circuit simultaneously
With output signal sense_v of supply voltage monitoring circuit, produce configuration signal trim.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620756790.0U CN205811849U (en) | 2016-07-18 | 2016-07-18 | The charge pump system that driving force is stable |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620756790.0U CN205811849U (en) | 2016-07-18 | 2016-07-18 | The charge pump system that driving force is stable |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160462A (en) * | 2016-07-18 | 2016-11-23 | 西安紫光国芯半导体有限公司 | The charge pump system that a kind of driving force is stable |
| CN108879596A (en) * | 2017-05-09 | 2018-11-23 | 上海复旦微电子集团股份有限公司 | A kind of leakage protection circuit with power supply monitoring function |
| CN110956985A (en) * | 2018-09-21 | 2020-04-03 | 合肥格易集成电路有限公司 | Memory control circuit and method and nonvolatile memory |
-
2016
- 2016-07-18 CN CN201620756790.0U patent/CN205811849U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160462A (en) * | 2016-07-18 | 2016-11-23 | 西安紫光国芯半导体有限公司 | The charge pump system that a kind of driving force is stable |
| CN108879596A (en) * | 2017-05-09 | 2018-11-23 | 上海复旦微电子集团股份有限公司 | A kind of leakage protection circuit with power supply monitoring function |
| CN108879596B (en) * | 2017-05-09 | 2019-11-05 | 上海复旦微电子集团股份有限公司 | A kind of leakage protection circuit with power supply monitoring function |
| CN110956985A (en) * | 2018-09-21 | 2020-04-03 | 合肥格易集成电路有限公司 | Memory control circuit and method and nonvolatile memory |
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