CN109104216A - A kind of M-BUS repeater - Google Patents
A kind of M-BUS repeater Download PDFInfo
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- CN109104216A CN109104216A CN201811284388.7A CN201811284388A CN109104216A CN 109104216 A CN109104216 A CN 109104216A CN 201811284388 A CN201811284388 A CN 201811284388A CN 109104216 A CN109104216 A CN 109104216A
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- nand gate
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- 238000012545 processing Methods 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims description 49
- 230000005540 biological transmission Effects 0.000 abstract description 16
- 238000012546 transfer Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004891 communication Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/36—Repeater circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention discloses a kind of M-BUS repeater, the input terminal of first signal processing circuit is connected with the higher level equipment, and the output end of the second signal processing circuit is connected with the subordinate equipment；The input terminal of the second signal processing circuit is connected with the subordinate equipment, and the output end of the second signal processing circuit is connected with the higher level equipment.First signal processing circuit transmits signal by Schmidt's logic gates, logic circuit does not reduce the rate of data transmission, under the cooperation of second signal processing circuit, higher level equipment shields the transmission signal of subordinate equipment, guarantee that repeater only carries out one-way data transfer, other interference signals are shielded simultaneously, and signal has same effect when transmitting from subordinate equipment superior equipment；The circuit structure of repeater is simple, and transmission rate is very fast.
Description
Technical field
The present invention relates to communication field more particularly to a kind of M-BUS repeaters.
Background technique
At present in M-BUS transmission technique field, based on the characteristic of M-BUS bus transfer, forwarding device is to utilize monolithic
Machine receives the data that higher level equipment transmitting terminal is sent, and after differentiating data content, then forwards the data of subordinate equipment.
As forwarding device, for shielded signal interference, needs frequently switch host computer side and the transmission from pusher side and connect
Receiving end mouth, does not interfere with when ensureing data communication, which generally utilizes single-chip microcontroller and software to cooperate and realize.But monolithic
There are several respects in the use of machine and software: one, host (higher level equipment) and slave (subordinate equipment) must be known in advance
Communications protocol, understand two equipment and when " be sent " and " receiving ", sent and received convenient for differentiating when to convert
State needs to carry out protocol identification and conversion if both sides agreement is different, additionally increases work, influences very much transponder
Versatility, and software forward can not be then used for the occasion of agreement secrecy, it is close to prevent stopping leak；
Two, data communication limited speed system forwards data using single-chip microcontroller, and there are two types of modes, one is byte-by-byte turns
Hair, single-chip microcontroller must discriminate whether that, there are loss of data, the failure of CRC check mistake etc, forwarding is easy, but differentiate that data are complete
Whole property is more difficult；The second is entire data packet forwarding, is first temporarily stored in single-chip microcontroller, forwards again after to be identified, this
Then speed is greatly affected sample, if there is multi-level forwarding device in centre, speed declines at double, seriously affects the practicability of transponder；
Three, Information Security needs the occasion encrypted in communication data there are risk, sometimes using data send when
Sequence sends interval time as secret key parameter, due to intermediate software identification and forwards link, will lead to the generation of these parameters
Variation, causes can not to decrypt or encrypted deactivation.
Summary of the invention
The technical problems to be solved by the present invention are: providing, a kind of hardware configuration is simple, in the faster M-BUS of communication speed
After device.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows: a kind of M-BUS repeater, the relaying
Device is connected between higher level equipment and subordinate equipment, including the first signal processing circuit and second signal processing circuit；
First signal processing circuit includes the first NAND gate, the first phase inverter, the second phase inverter, first resistor, the
One Schmidt's NAND gate and first capacitor, the end TXD of the higher level equipment by first phase inverter with described first with it is non-
The input terminal of door is connected, and the end RXD of the higher level equipment passes sequentially through first resistor, first Schmidt's NAND gate and described second
Phase inverter is connected with another input terminal of first NAND gate, output end and the subordinate equipment of first NAND gate
The end RX is connected, and another input terminal of the first Schmidt NAND gate is grounded by the first capacitor, the first diode
The cathode of the first diode in parallel and described with the first resistor is connected with the end TXD of the higher level equipment；
The second signal processing circuit includes the second NAND gate, third phase inverter, the 4th phase inverter, second resistance, the
The end TX of two Schmidt's NAND gates and the second capacitor, the subordinate equipment passes through the third phase inverter and second NAND gate
Input terminal be connected, the end RX of the subordinate equipment passes sequentially through second resistance, second applies close NAND gate and the 4th reverse phase
Device is connected with another input terminal of second NAND gate, the output end of second NAND gate and the RXD of the higher level equipment
End is connected, another input terminal of the second Schmidt NAND gate by the second capacity earth, second diode with it is described
The cathode of second resistance parallel connection and second diode is connected with the end RX of the subordinate equipment.
Further, the end the TXD output high level intermittent phase of the higher level equipment is the charging time of the first capacitor
The 1/10 of constant；The 1/10 of the charging constant of second capacitor described in the end the TX output high level intermittent phase of the subordinate equipment.
Further, the charge constant of the first capacitor capacitor is 4.16 milliseconds, the resistance value of the first resistor
It is 50 kilo-ohms, the resistance value of the first capacitor is 0.1 microfarad；The charge constant of second capacitance is 4.16 millis
Second, the resistance value of the second resistance is 50 kilo-ohms, and the resistance value of second capacitor is 0.1 microfarad.
Further, the first Schmidt NAND gate and the second Schmidt NAND gate be CD4093 Schmidt with
NOT gate.
Further, first NAND gate is Schmidt's NAND gate.
Further, second NAND gate is Schmidt's NAND gate.
The beneficial effects of the present invention are: the first signal processing circuit passes signal by Schmidt's logic gates
Defeated, logic circuit does not reduce the rate of data transmission, and under the cooperation of second signal processing circuit, higher level equipment is to subordinate equipment
Transmission signal shielded, guarantee that repeater only carries out one-way data transfer, while shielding other interference signals, signal from
There is same effect when subordinate equipment superior equipment is transmitted；The circuit structure of repeater is simple, and transmission rate is very fast.
Detailed description of the invention
Fig. 1 is the circuit diagram of the M-BUS repeater of the embodiment of the present invention one.
Label declaration:
U1, the first NAND gate；U2, the first phase inverter；U3, the second phase inverter；U4, first Schmidt's NAND gate；U5, second
NAND gate；U6, third phase inverter；U7, the 4th phase inverter；U8, second Schmidt's NAND gate；R1, first resistor；R2, the second electricity
Resistance；C1, first capacitor；C2, the second capacitor；
D1, first diode；D2, the second diode.
Specific embodiment
To explain the technical content, the achieved purpose and the effect of the present invention in detail, below in conjunction with embodiment and cooperate attached
Figure is explained.
The most critical design of the present invention is: the first signal processing circuit carries out signal by Schmidt's logic gates
Transmission, under the cooperation of second signal processing circuit, higher level equipment shields the transmission signal of subordinate equipment, guarantees relaying
Device only carries out one-way data transfer, and it is identical that subordinate equipment superior equipment carries out signal transmission working principle.
Fig. 1, a kind of M-BUS repeater are please referred to, the repeater is connected between higher level equipment and subordinate equipment, including
First signal processing circuit and second signal processing circuit；
First signal processing circuit includes the first NAND gate U1, the first phase inverter U2, the second phase inverter U3, the first electricity
Hinder R1, first Schmidt's NAND gate U4 and first capacitor C1, the end TXD of the higher level equipment by the first phase inverter U2 with
The input terminal of the first NAND gate U1 is connected, and the end RXD of the higher level equipment passes sequentially through first resistor R1, the first Schmidt
NAND gate U4 and the second phase inverter U3 is connected with another input terminal of the first NAND gate U1, the first NAND gate U1
Output end be connected with the end RX of the subordinate equipment, another input terminal of the first Schmidt NAND gate U4 passes through described the
One capacitor C1 ground connection, the cathode of first diode D1 first diode D1 in parallel and described with the first resistor R1 and institute
The end TXD for stating higher level equipment is connected；
The second signal processing circuit includes the second NAND gate U5, third phase inverter U6, the 4th phase inverter U7, the second electricity
Hinder R2, second Schmidt's NAND gate U8 and the second capacitor C2, the end TX of the subordinate equipment by the third phase inverter U6 and
The input terminal of the second NAND gate U5 is connected, the end RX of the subordinate equipment pass sequentially through second resistance R2, second apply it is close with
NOT gate and the 4th phase inverter U7 are connected with another input terminal of the second NAND gate U5, and the second NAND gate U5's is defeated
Outlet is connected with the end RXD of the higher level equipment, and another input terminal of the second Schmidt NAND gate U8 passes through the second capacitor
C2 ground connection, the cathode of the second diode D2 second diode D2 in parallel and described with the second resistance R2 and the junior
The end RX of equipment is connected.
The working principle of the invention is summarized as follows: before work starts, the end TXD and the end RXD of higher level equipment are high level,
The end TX and the end RX of subordinate equipment are also high level, the output end of first Schmidt's NAND gate and second Schmidt's NAND gate
Output end exports low level, and higher level equipment and subordinate equipment can be with normal transmission data；
After work starts, data are sent by the end TXD of higher level equipment first, the end TX of subordinate equipment is sent not yet at this time
Data, so the end RXD of higher level equipment is still high level, the output end of first Schmidt's NAND gate is low level, by the
The output end of two phase inverters exports high level, is input in the first NAND gate, is at this time unlocked state, the end TXD of higher level equipment
Data can by the first phase inverter and first Schmidt's NAND gate it is reversed twice after, be input to the end RX of subordinate equipment, normally
Communication.
While the TXD end data of higher level equipment is sent to the end RX of subordinate equipment, by second resistance, the second capacitor and
Second diode constitutes one and slows down charging circuit fastly, the falling edge that the low pulse of first of the end RX of subordinate equipment arrives,
Voltage on second capacitor immediately passes through the end RX that the second diode is released to subordinate equipment, reaches zero level；At the same time
Overturning immediately occurred in the level of two Schmidt's NAND gates, and the output end of second Schmidt's NAND gate becomes high level, and immediately the 4th
The output end of phase inverter becomes low level, is output to the second NAND gate, no matter the TX foot of subordinate equipment exports high level or low
Level, what the end RXD of higher level equipment received is all high level, to shield the sending function at the end TX of subordinate equipment.
As can be seen from the above description, the beneficial effects of the present invention are: the first signal processing circuit passes through Schmidt's logic gate
Circuit transmits signal, and logic circuit does not reduce the rate of data transmission, under the cooperation of second signal processing circuit, on
Grade equipment shields the transmission signal of subordinate equipment, guarantees that repeater only carries out one-way data transfer, while shielding it
His interference signal, signal have same effect when transmitting from subordinate equipment superior equipment；The first signal processing electricity of repeater
Road and second signal processing circuit structure are simple, and transmission rate is very fast.
Further, when the end the TXD output high level intermittent phase of the higher level equipment is the charging of the first capacitor C1
Between constant 1/10；The 1/ of the charging constant of second capacitor C2 described in the end the TX output high level intermittent phase of the subordinate equipment
10。
Seen from the above description, the output high level intermittent phase is the 1/10 of capacitor charging time constant, forms fixed signal,
Delay and error are reduced, reliable exclusive circuit is constituted.
Further, the charge constant of the first capacitor C1 capacitor is 4.16 milliseconds, the first resistor R1's
Resistance value is 50 kilo-ohms, and the resistance value of the first capacitor C1 is 0.1 microfarad；The charge constant of the second capacitor C2 capacitor is
4.16 milliseconds, the resistance value of the second resistance R2 is 50 kilo-ohms, and the resistance value of the second capacitor C2 is 0.1 microfarad.
Further, the first Schmidt NAND gate U4 and the second Schmidt NAND gate U8 be CD4093 apply it is close
Special NAND gate.
Further, the first NAND gate U1 is Schmidt's NAND gate.
Further, the second NAND gate U5 is Schmidt's NAND gate.
Seen from the above description, the first NAND gate and the second NAND gate using Schmidt's NAND gate can be integrated into it is same apply it is close
In special NAND gate, the wasting of resources in the consumption and processing on hardware selection is reduced.
Embodiment one
Please refer to Fig. 1, the embodiment of the present invention one are as follows: a kind of M-BUS repeater, the repeater are connected to higher level equipment
Between subordinate equipment, including the first signal processing circuit and second signal processing circuit；
First signal processing circuit includes the first NAND gate U1, the first phase inverter U2, the second phase inverter U3, the first electricity
Hinder R1, first Schmidt's NAND gate U4 and first capacitor C1, the end TXD of the higher level equipment by the first phase inverter U2 with
The input terminal of the first NAND gate U1 is connected, and the end RXD of the higher level equipment passes sequentially through first resistor R1, the first Schmidt
NAND gate U4 and the second phase inverter U3 is connected with another input terminal of the first NAND gate U1, the first NAND gate U1
Output end be connected with the end RX of the subordinate equipment, another input terminal of the first Schmidt NAND gate U4 passes through described the
One capacitor C1 ground connection, the cathode of first diode D1 first diode D1 in parallel and described with the first resistor R1 and institute
The end TXD for stating higher level equipment is connected；
The second signal processing circuit includes the second NAND gate U5, third phase inverter U6, the 4th phase inverter U7, the second electricity
Hinder R2, second Schmidt's NAND gate U8 and the second capacitor C2, the end TX of the subordinate equipment by the third phase inverter U6 and
The input terminal of the second NAND gate U5 is connected, the end RX of the subordinate equipment pass sequentially through second resistance R2, second apply it is close with
NOT gate and the 4th phase inverter U7 are connected with another input terminal of the second NAND gate U5, and the second NAND gate U5's is defeated
Outlet is connected with the end RXD of the higher level equipment, and another input terminal of the second Schmidt NAND gate U8 passes through the second capacitor
C2 ground connection, the cathode of the second diode D2 second diode D2 in parallel and described with the second resistance R2 and the junior
The end RX of equipment is connected.
The 1/ of the charge constant that the end the TXD output high level intermittent phase of the higher level equipment is the first capacitor C1
10；The 1/10 of the charging constant of second capacitor C2 described in the end the TX output high level intermittent phase of the subordinate equipment, in this implementation
In example, the high level intermittent phase is that the data of capacitor charging time constant are definite value, avoids numerical value too small, block signal can not
It forms one section of fixed level or numerical value is excessive, cause block signal the phenomenon that larger delay or generation large error occur, lead
It causes signal shielding not exclusively or loses useful signal.
Detailed, the charge constant of the first capacitor C1 capacitor is 4.16 milliseconds, according to τ=RC, when wherein τ is
Between constant, in the present embodiment, time constant is 4.16 milliseconds, and optionally, the resistance value of the first resistor R1 is 50 kilo-ohms, institute
The resistance value for stating first capacitor C1 is 0.1 microfarad；The charge constant of the second capacitor C2 capacitor is 4.16 milliseconds, according to τ
=RC, wherein τ is time constant, and in the present embodiment, time constant is 4.16 milliseconds, optionally, the second resistance R2's
Resistance value is 50 kilo-ohms, and the resistance value of the second capacitor C2 is 0.1 microfarad.
Specifically, the first Schmidt NAND gate U4 and the second Schmidt NAND gate U8 are CD4093 Schmidt
NAND gate.
Optionally, the first NAND gate U1 is Schmidt's NAND gate, and the second NAND gate U5 is Schmidt's NAND gate,
When the first NAND gate U1 and the second NAND gate U5 select Schmidt's NAND gate, then in M-BUS repeater, used logic gate
NAND gate in circuit is all made of Schmidt's NAND gate, more specifically, the first NAND gate U1, the second NAND gate U5, first apply it is close
Special NAND gate U4 and second Schmidt's NAND gate U8 are all made of CD4093 Schmidt's NAND gate, have in the selection of device unified
Property, reduce the cost waste in type selecting.
In conclusion a kind of M-BUS repeater provided by the invention, the first signal processing circuit passes through Schmidt's logic gate
Circuit transmits signal, and logic circuit does not reduce the rate of data transmission, under the cooperation of second signal processing circuit, on
Grade equipment shields the transmission signal of subordinate equipment, guarantees that repeater only carries out one-way data transfer, while shielding it
His interference signal, signal have same effect when transmitting from subordinate equipment superior equipment；The circuit structure of repeater is simple, passes
Defeated rate is very fast；The output high level intermittent phase is the 1/10 of capacitor charging time constant, forms fixed signal, reduces delay and misses
Difference constitutes reliable exclusive circuit.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalents made by bright specification and accompanying drawing content are applied directly or indirectly in relevant technical field, similarly include
In scope of patent protection of the invention.
Claims (6)
1. a kind of M-BUS repeater, the repeater are connected between higher level equipment and subordinate equipment, it is characterised in that: including
First signal processing circuit and second signal processing circuit；
First signal processing circuit is applied including the first NAND gate, the first phase inverter, the second phase inverter, first resistor, first
The end TXD of close spy's NAND gate and first capacitor, the higher level equipment passes through first phase inverter and first NAND gate
Input terminal is connected, and the end RXD of the higher level equipment passes sequentially through first resistor, first Schmidt's NAND gate and second reverse phase
Device is connected with another input terminal of first NAND gate, the output end of first NAND gate and the end RX of the subordinate equipment
It is connected, another input terminal of the first Schmidt NAND gate is grounded by the first capacitor, the first diode and institute
The cathode for stating first resistor parallel connection and the first diode is connected with the end TXD of the higher level equipment；
The second signal processing circuit is applied including the second NAND gate, third phase inverter, the 4th phase inverter, second resistance, second
Close spy's NAND gate and the second capacitor, the end TX of the subordinate equipment are defeated by the third phase inverter and second NAND gate
Enter end to be connected, the end RX of the subordinate equipment pass sequentially through second resistance, second apply close NAND gate and the 4th phase inverter with
Another input terminal of second NAND gate is connected, the end the RXD phase of the output end and the higher level equipment of second NAND gate
Even, another input terminal of the second Schmidt NAND gate passes through the second capacity earth, second diode and described second
The cathode of resistor coupled in parallel and second diode is connected with the end RX of the subordinate equipment.
2. M-BUS repeater according to claim 1, it is characterised in that: the end TXD of the higher level equipment exports high level
Intermittent phase is the 1/10 of the charge constant of the first capacitor；The end TX of the subordinate equipment exports high level intermittent phase institute
State the 1/10 of the charging constant of the second capacitor.
3. M-BUS repeater according to claim 2, it is characterised in that: the charging time of the first capacitor capacitor is normal
Number is 4.16 milliseconds, and the resistance value of the first resistor is 50 kilo-ohms, and the resistance value of the first capacitor is 0.1 microfarad；Described second
The charge constant of capacitance is 4.16 milliseconds, and the resistance value of the second resistance is 50 kilo-ohms, the resistance of second capacitor
Value is 0.1 microfarad.
4. M-BUS repeater according to claim 1, it is characterised in that: the first Schmidt NAND gate and described the
Two Schmidt's NAND gates are CD4093 Schmidt's NAND gate.
5. M-BUS repeater according to claim 1, it is characterised in that: first NAND gate is Schmidt's NAND gate.
6. M-BUS repeater according to claim 1, it is characterised in that: second NAND gate is Schmidt's NAND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811284388.7A CN109104216B (en) | 2018-10-31 | 2018-10-31 | M-BUS repeater |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811284388.7A CN109104216B (en) | 2018-10-31 | 2018-10-31 | M-BUS repeater |
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| Publication Number | Publication Date |
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| CN109104216A true CN109104216A (en) | 2018-12-28 |
| CN109104216B CN109104216B (en) | 2024-05-10 |
Family
ID=64869880
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811284388.7A Active CN109104216B (en) | 2018-10-31 | 2018-10-31 | M-BUS repeater |
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2018
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| JP2000209073A (en) * | 1999-01-13 | 2000-07-28 | Asahi Kasei Microsystems Kk | Schmitt trigger circuit |
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| CN107979359A (en) * | 2018-01-11 | 2018-05-01 | 苏州锴威特半导体有限公司 | A kind of clock synchronization circuit for maintaining fixed pulse |
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| CN109104216B (en) | 2024-05-10 |
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