CN103368366A - Inverter over-current protection circuit - Google Patents
Inverter over-current protection circuit Download PDFInfo
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- CN103368366A CN103368366A CN2012100874980A CN201210087498A CN103368366A CN 103368366 A CN103368366 A CN 103368366A CN 2012100874980 A CN2012100874980 A CN 2012100874980A CN 201210087498 A CN201210087498 A CN 201210087498A CN 103368366 A CN103368366 A CN 103368366A
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Abstract
The invention discloses an inverter over-current protection circuit which comprises a first logic control circuit, a second control circuit and a third control logic circuit. The first logic control circuit is connected with a first input pin used for receiving a first level protection signal. The second logic control circuit is connected with a second input pin used for receiving a second level protection signal. The first level or the second level protection signal is subjected to signal conversion by the first logic control circuit, the second control circuit or the third control logic circuit, and an enable signal used for controlling the PWM waveform output of the inverter is outputted from an output end of the third logic control circuit. According to the inverter over-current protection circuit, through setting two pins to receive control signals of two levels to carry out two-level protection, a reliable circuit with strong interference resistance is provided, the inverter can be reliably and stably operated for a long time in an extremely harsh electromagnetic interference environment, a disadvantage that the inverter shows an error action to over-current protection is solved, and great convenience is brought to a user.
Description
Technical field
The present invention relates to the control circuit field, relate more specifically to a kind of frequency converter current foldback circuit.
Background technology
In the industrial automation product designs such as frequency converter, UPS and inverter or other commercial Application, often need the industrial automation product stable at work, forbid that the over current fault that daps appears in product in running.Existing method all is that the peak value of current sensor output waveform and reference level are compared, and the actual value of exporting when current sensor has surpassed reference level, blocks immediately the output of PWM, and equipment shows the overcurrent protection fault simultaneously.Existing protective circuit for frequency converter as shown in Figure 1; based on this circuit; when current sensor detects fault current; the OC1 pin will be received low level signal; this low level signal is delivered to input the 2nd pin with door U9A (74HC08); the OC signal by with produce behind the door a low level signal and deliver to and the output of the 3rd pin of door U9A; this low level signal is with triode Q1 conducting; after the Q1 conducting; U3A (74VHC14) the 1st pin is set to high level; 1 pin by 2 not gate U3A and U3D after signal or high level, so high level through the R150 current limliting after, light the LED1 light-emitting diode.Therefore when the output current of frequency converter was excessive, the LED1 light-emitting diode was in the operating state of Chang Liang.The 2nd pin of U3A this moment (74HCT14) is set to low level, through with door U9B after, its the 6th pin is output as low level, behind not gate U3F, the 12nd pin of U3F is set to high level, and this high level signal is with triode Q2 conducting, after the Q2 conducting, the 1st pin of NAND gate U11 is set to low level, is set to high level through its 4th pin behind the NAND gate U11, namely the DRV-EN signal exported of DRV-EN pin is high level.The DRV-EN signal is the control signal that enables of PWM waveform, and when the DRV-EN signal was low level, the PWM waveform was exported by 74HCT244, when the DRV-EN signal is high level, and PWM waveform no thoroughfare 74HCT244 output.
Yet but there is following defective in foregoing circuit: if industrial equipment scene interference ratio is severe, and after the amplitude of interference signal has surpassed reference level, comparator work, causing the OC signal disturbed is low level, hardware blocks the output of PWM waveform immediately.Thereby affected the normal operating conditions of frequency converter, also had a strong impact on stability and the reliability of product, even caused in various degree loss to the user.
In order to address the aforementioned drawbacks, to be necessary to provide a kind of and to have the frequency converter current foldback circuit of high anti-jamming capacity to improve the monolithic stability reliability of converter circuit.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can skip flow problem to solve the frequent misoperation of on-the-spot frequency converter by frequency converter current foldback circuit that under adverse circumstances, work, that antijamming capability is strong, thereby improve the reliability of circuit.
To achieve these goals, the technical solution used in the present invention is: a kind of frequency converter current foldback circuit is provided, it comprises the first logic control circuit, the second logic control circuit and the 3rd logic control circuit, wherein, described the first logic control circuit comprises the first NAND gate, the second NAND gate, the first diode and the second diode, two inputs of described the first NAND gate link to each other and are connected to one for the first input pin that receives first order guard signal, the output of described the first NAND gate is connected to two inputs of described the second NAND gate by described the first diode, the output of described the second NAND gate links to each other with an output pin by the second diode; Described the second logic control circuit comprises the 3rd NAND gate, the 4th NAND gate, the 3rd diode and the 4th diode, two inputs of described the 3rd NAND gate link to each other and are connected to one for the second input pin that receives second level guard signal, the output of described the 3rd NAND gate links to each other with an input of described the 4th NAND gate, another input termination supply power voltage of described the 4th NAND gate, the output of described the 4th NAND gate links to each other with described output pin by described the 3rd diode, and described the 4th diode is connected between the output of the input of described the 3rd NAND gate and described the 4th NAND gate; Described the 3rd logic control circuit comprises the 5th NAND gate, and an input of described the 5th NAND gate is connected to described output pin, another input termination supply power voltage of described the 5th NAND gate, and the output of described the 5th NAND gate is the enable pin of PWM waveform.
Its further technical scheme is: described the first logic control circuit also comprises resistance and electric capacity, described resistance is connected between the input of the output of described the first NAND gate and the second NAND gate, and described electric capacity one end links to each other and other end ground connection with the input of described the second NAND gate.
Its further technical scheme is: described first order guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one first predetermined current value; described first order guard signal is low level; described inverter current is during less than described the first predetermined current value, and described first order guard signal is high level.
Its further technical scheme is: described second level guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one second predetermined current value; described second level guard signal is low level; described inverter current is during less than described the second predetermined current value, and described second level guard signal is high level.
Its further technical scheme is: described the first predetermined current value is less than described the second predetermined current value.
Its further technical scheme is: described the first predetermined current value is 1.8 times of rated current.
Its further technical scheme is: described the second predetermined current value is 2.2 times of rated current.
Compared with prior art; frequency converter current foldback circuit provided by the invention adopts hardware to realize the wave limiting function; impulse waveform is one by one detected; as finding the over-current phenomenon avoidance that surpasses the setting current value was arranged within a pulse period; hardware is realized the circuit start protection of wave limiting; so that frequency converter is when reaching software and cross flow point, can be with the operation of hardware constraints current value, reduced the probability that overcurrent protection appears in frequency converter.Receive two other control signals of level and carry out twin-stage protection by two input pins are set; thereby provide a kind of superpower jamproof reliable circuit; so that frequency converter can carry out long, reliable and stable operation in extremely abominable electromagnetic interference environment; greatly degree reduces the situation that various industrial automation equipments frequently break down at the scene; solve frequency converter and misoperation occurred to the shortcoming of overcurrent protection, brought great ease of use to the user.
By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining embodiments of the invention.
Description of drawings
Fig. 1 is the circuit diagram of existing frequency converter current foldback circuit.
Fig. 2 is the circuit diagram of frequency converter current foldback circuit one embodiment of the present invention.
Each description of reference numerals is as follows among the figure:
Frequency converter current foldback circuit 10
The first logic control circuit 11
The second logic control circuit 12
The 3rd logic control circuit 13
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme among the embodiment is clearly and completely described, similar assembly label represents similar assembly in the accompanying drawing.Obviously, below only be the present invention's part embodiment with the embodiment that describes, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
With reference to Fig. 2, Fig. 2 has showed an embodiment of frequency converter current foldback circuit of the present invention.In the present embodiment, described frequency converter current foldback circuit 10 comprises the first logic control circuit 11, the second logic control circuit 12 and the 3rd logic control circuit 13.The input of described the first logic control circuit 11 and the second logic control circuit 12 receives respectively first order guard signal and second level guard signal; and the output of described the first logic control circuit 11 and the second logic control circuit 12 all links to each other with the input of described the 3rd logic control circuit 13, and the output output of described the 3rd logic control circuit 13 is used for the enable signal of control PWM waveform output.
In the present embodiment; described the first logic control circuit 11 comprises the first NAND gate U1, the second NAND gate U2, the first diode D1 and the second diode D2; two inputs of described the first NAND gate U1 link to each other and are connected to one for the first input pin OC1 that receives first order guard signal; the output of described the first NAND gate U1 is connected to two inputs of described the second NAND gate U2 by described the first diode D1, the output of described the second NAND gate U2 links to each other with output pin TZ1 by the second diode D2.Preferably, described the first logic control circuit 11 also comprises resistance R 4 and capacitor C 2, described resistance R 4 is connected between the input of the output of described the first NAND gate U1 and the second NAND gate U2, and described capacitor C 2 one ends link to each other and other end ground connection with the input of described the second NAND gate U2.
In the present embodiment; described the second logic control circuit 12 comprises the 3rd NAND gate U3; the 4th NAND gate U4; the 3rd diode D3 and the 4th diode D4; two inputs of described the 3rd NAND gate U3 link to each other and are connected to one for the second input pin OC2 that receives second level guard signal; the output of described the 3rd NAND gate U3 links to each other with the input of described the 4th NAND gate U4; another input termination supply power voltage of described the 4th NAND gate U4; the output of described the 4th NAND gate U4 links to each other with described output pin TZ1 by described the 3rd diode D3, and described the 4th diode D4 is connected between the output of the input of described the 3rd NAND gate U3 and described the 4th NAND gate U4.
In the present embodiment, described the 3rd logic control circuit 13 comprises the 5th NAND gate U5, the input of described the 5th NAND gate U5 is connected to described output pin TZ1, another of described the 5th NAND gate U5 inputted termination supply power voltage and is pulled to high level always, and the output of described the 5th NAND gate U5 is the enable pin DRV-EN of PWM waveform.
In the present embodiment; described first order guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one first predetermined current value; described first order guard signal is low level; described inverter current is during less than described the first predetermined current value, and described first order guard signal is high level.Similarly; described second level guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one second predetermined current value; described second level guard signal is low level; described inverter current is during less than described the second predetermined current value, and described second level guard signal is high level.In the present embodiment, set described the first predetermined current value less than described the second predetermined current value, wherein, described the first predetermined current value is 1.8 times of rated current, and described the second predetermined current value is 2.2 times of rated current.Understandably, described first, second predetermined current value is not limited to above-mentioned situation, and it can be set to other current value as required.
Describe the operation principle of frequency conversion current foldback circuit of the present invention in detail referring to accompanying drawing.
When inverter current during more than or equal to the first predetermined current value (rated current 1.8 times); the first input pin OC1 is effective; the first order guard signal that it receives is low level signal; this low level signal is through the 12nd of the first NAND gate U1 (74HC132) the; export high level by 11 pin (output) of this NAND gate U1 after 13 pin (two inputs) input; high level is at this moment through the first diode D1 (IN5819); through the 1st of the second NAND gate U2 (74HC132); the input of 2 pin also gives capacitor C 2 chargings simultaneously; afterwards in 3 pin output low levels, this low level is through controlling pin TZ1 output low level behind the second diode D2 (IN5819) through the second NAND gate U2.DRIVE drive that pin is connected to VCC and always by on move high level to, the low level of control pin TZ1 output is delivered to the input (the 1st pin) of the 5th NAND gate U5 (74VHC1G00), through its output (the 4th pin) output high level signal DRV-EN after this NAND gate U5, the DRV-EN signal is used for controlling the pin that enables of the 74HC244 that can produce 6 road PWM waveforms.This DRV-EN signal is low level when frequency converter works, and this DRV-EN signal becomes high level immediately when over-current phenomenon avoidance occurring, thereby blocks the output of frequency converter.
When the output current of frequency converter is varied down to when being lower than 1.8 times rated current, the input signal of the first input pin OC1 is set to high level, this high level signal is through the 12nd of the first NAND gate U1 the, rear 11 pin (output) output low level by this NAND gate U1 of 13 pin (two inputs) input, this moment, C2 and R4 formed a discharge loop, time constant is 200Us, low level is at this moment through the 1st of the second NAND gate U2, the input of 2 pin, then at its 3rd pin output high level, this high level is ended by the second diode D2, thereby the output signal of control pin TZ1 is set to high level.Described output signal is delivered to the 1st pin of the 5th NAND gate U5, is low level through the DRV-EN signal in its 4th pin output after the NAND gate, and this moment, frequency converter was in again normal operating conditions.As mentioned above, the operating state of this circuit has reached the effect of fabulous wave limiting.
When the output current of frequency converter during more than or equal to the second predetermined current value (rated current 2.2 times); the second input pin OC2 is effective; the second level guard signal that it receives is low level signal; this low level signal is through the 4th, the 5 pin input of U3 (74HC132); through after this NAND gate U3 at its 6th pin output high level and this high level is input to the 4th NAND gate U4 (74HC132) from the 9th pin (input), and this moment the 4th NAND gate U4 the 10th pin (another input) drawn on the 3.3V and be high level.Therefore, after the 4th NAND gate U4, the 8th pin output low level, this low level is again through controlling pin TZ1 output low level behind the 3rd diode D3 (IN5819), therefore, based on above-mentioned principle, finally the DRV-EN signal in the output of the 5th NAND gate U5 output (the 4th pin) is high level, thereby blocks the output of frequency converter.At this moment, the 4th diode D4 (IN5819) plays interlocked and uses, when the 8th pin output low level of U4, the signal no matter the second input pin OC2 receives is high level or low level, the permanent output low level of the 8th pin of U4, the output of control pin TZ1 is set to low level behind this low level process diode D3, and the DRV-EN signal in its 4th pin output is high level after the process NAND gate U5.
As mentioned above; protective circuit of the present invention is to be higher than 1.8 times or equal 1.8 times of rated current and at 2.2 times below the rated current when the interference signal amplitude; this interference signal is processed by the first input pin OC1; when the interference signal amplitude equals or is higher than more than 2.2 times of rated current, interference signal is processed by the second input pin OC2.And the time constant of the blockade PWM that interference signal causes is the result of R4, C2 product.Reason is when interference signal (amplitude is lower than 2.2 times of rated current) when coming, the enable signal DRV-EN that exports after the processing of low level through the first logic control circuit 11 and the 3rd logic control circuit 13 that OC1 receives is high level, thereby block the output of frequency converter, and under the effect of RC circuit, 6 road PWM waveform blocking times are the result of R4 and C2 product.After interference signal was gone over, OC1 was set to high level again, and the DRV-EN signal becomes low level, frequency converter normal operation this moment.Therefore interference signal time of turn-offing afterwards the PWM waveform is the product of R4 and C2.So this circuit can the establishment amplitude be lower than the interference signal of 2.2 times of rated current.
Therefore; frequency converter current foldback circuit provided by the invention is a kind of superpower jamproof reliable circuit; it can carry out long, reliable and stable operation in extremely abominable electromagnetic interference environment; greatly degree reduces the situation that various industrial automation equipments frequently break down at the scene; solve frequency converter and misoperation occurred to the shortcoming of overcurrent protection, brought great ease of use to the user.
Need to prove, other electronic components of not describing act as technology well-known to those skilled in the art in the frequency converter current foldback circuit of the present invention in this circuit, are not described in detail in this.
Above invention has been described in conjunction with preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain various modification, equivalent combinations of carrying out according to essence of the present invention.
Claims (7)
1. a frequency converter current foldback circuit is used for frequency converter is realized the wave limiting protection, it is characterized in that described frequency converter current foldback circuit comprises:
The first logic control circuit, described the first logic control circuit comprises the first NAND gate, the second NAND gate, the first diode and the second diode, two inputs of described the first NAND gate link to each other and are connected to one for the first input pin that receives first order guard signal, the output of described the first NAND gate is connected to two inputs of described the second NAND gate by described the first diode, the output of described the second NAND gate links to each other with an output pin by the second diode;
The second logic control circuit, described the second logic control circuit comprises the 3rd NAND gate, the 4th NAND gate, the 3rd diode and the 4th diode, two inputs of described the 3rd NAND gate link to each other and are connected to one for the second input pin that receives second level guard signal, the output of described the 3rd NAND gate links to each other with an input of described the 4th NAND gate, another input termination supply power voltage of described the 4th NAND gate, the output of described the 4th NAND gate links to each other with described output pin by described the 3rd diode, and described the 4th diode is connected between the output of the input of described the 3rd NAND gate and described the 4th NAND gate;
The 3rd logic control circuit, described the 3rd logic control circuit comprises the 5th NAND gate, one input of described the 5th NAND gate is connected to described output pin, another input termination supply power voltage of described the 5th NAND gate, the output of described the 5th NAND gate is the enable pin of frequency converter PWM waveform.
2. frequency converter current foldback circuit as claimed in claim 1; it is characterized in that: described the first logic control circuit also comprises resistance and electric capacity; described resistance is connected between the input of the output of described the first NAND gate and the second NAND gate, and described electric capacity one end links to each other and other end ground connection with the input of described the second NAND gate.
3. frequency converter current foldback circuit as claimed in claim 1; it is characterized in that: described first order guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one first predetermined current value; described first order guard signal is low level; described inverter current is during less than described the first predetermined current value, and described first order guard signal is high level.
4. frequency converter current foldback circuit as claimed in claim 3; it is characterized in that: described second level guard signal is the level signal that is controlled by inverter current; described inverter current is during more than or equal to one second predetermined current value; described second level guard signal is low level; described inverter current is during less than described the second predetermined current value, and described second level guard signal is high level.
5. frequency converter current foldback circuit as claimed in claim 4, it is characterized in that: described the first predetermined current value is less than described the second predetermined current value.
6. frequency converter current foldback circuit as claimed in claim 5, it is characterized in that: described the first predetermined current value is 1.8 times of rated current.
7. frequency converter current foldback circuit as claimed in claim 5, it is characterized in that: described the second predetermined current value is 2.2 times of rated current.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210087498.0A CN103368366B (en) | 2012-03-29 | 2012-03-29 | Inverter over-current protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210087498.0A CN103368366B (en) | 2012-03-29 | 2012-03-29 | Inverter over-current protection circuit |
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| CN103368366A true CN103368366A (en) | 2013-10-23 |
| CN103368366B CN103368366B (en) | 2016-10-19 |
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| CN108155783A (en) * | 2016-12-02 | 2018-06-12 | 长沙市日业电气有限公司 | A kind of circuit for improving overcurrent protection antijamming capability |
| CN109104216A (en) * | 2018-10-31 | 2018-12-28 | 深圳市创仁科技有限公司 | A kind of M-BUS repeater |
| CN110247615A (en) * | 2018-03-09 | 2019-09-17 | 深圳市蓝海华腾技术股份有限公司 | Wave limiting control system, method and electric machine controller based on dsp chip |
| CN110346637A (en) * | 2019-08-23 | 2019-10-18 | 邢台子中电子科技有限公司 | A kind of method and device of sinusoid information Digital Extraction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108155783A (en) * | 2016-12-02 | 2018-06-12 | 长沙市日业电气有限公司 | A kind of circuit for improving overcurrent protection antijamming capability |
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| CN110247615B (en) * | 2018-03-09 | 2024-04-12 | 深圳市蓝海华腾技术股份有限公司 | Wave-by-wave current limiting control system and method based on DSP chip and motor controller |
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| CN110346637A (en) * | 2019-08-23 | 2019-10-18 | 邢台子中电子科技有限公司 | A kind of method and device of sinusoid information Digital Extraction |
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| CN103368366B (en) | 2016-10-19 |
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Inventor after: Chen Pengcheng Inventor after: Wang Wujun Inventor after: Liu Hongyi Inventor after: Zhu Zhihua Inventor before: Chen Pengcheng Inventor before: Chen Zhiling Inventor before: Ma Zhefeng |
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