CN103368366B - Inverter over-current protection circuit - Google Patents
Inverter over-current protection circuit Download PDFInfo
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- CN103368366B CN103368366B CN201210087498.0A CN201210087498A CN103368366B CN 103368366 B CN103368366 B CN 103368366B CN 201210087498 A CN201210087498 A CN 201210087498A CN 103368366 B CN103368366 B CN 103368366B
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Abstract
The invention discloses a kind of inverter over-current protection circuit, it includes first, second and the 3rd logic control circuit, described first logic control circuit connects the first input pin having for receiving first order protection signal, described second logic control circuit connects the second input pin having for receiving second level protection signal, the enable signal that the described first order or second level protection signal export for the PWM waveform controlling converter from the output of the outfan of the 3rd logic control circuit after the first or second logic control circuit and the 3rd logic control circuit carry out signal conversion.Inverter over-current protection circuit of the present invention carries out twin-stage protection by arranging two input pins and receiving the control signal of two ranks; thus a kind of superpower jamproof reliable circuit is provided; make converter can carry out long, reliable and stable operation in the electromagnetic interference environment of extreme; solve converter and the misoperation shortcoming to overcurrent protection occurs, bring great convenience to user.
Description
Technical field
The present invention relates to control circuit field, relate more specifically to a kind of inverter over-current protection circuit.
Background technology
In the industrial automation product designs such as converter, UPS and inverter or other commercial Application, warp
Often need industrial automation product the most stable, forbid that product occurs dapping in running
Stream fault.Existing method is all that peak value and the datum of current sensor output waveform are compared, and works as electricity
The actual value of flow sensor output has exceeded datum, blocks the output of PWM immediately, and equipment shows simultaneously
Overcurrent protection fault.The existing protection circuit for converter is as it is shown in figure 1, based on this circuit, work as electric current
When sensor detects fault current, OC1 pin will be received low level signal, this low level signal is delivered to
With input the 2nd foot of door U9A (74HC08), OC signal by with produce a low level signal behind the door and give
To the 3rd foot output with door U9A, audion Q1 is turned on by this low level signal, after Q1 conducting, by U3A
(74VHC14) the 1st foot is set to high level, and 1 foot passes through signal or high level after 2 not gate U3A and U3D,
Therefore high level is after R150 current limliting, lights LED1 light emitting diode.Therefore when the output electric current of converter
Time excessive, LED1 light emitting diode is in the duty of Chang Liang.Now the 2nd of U3A (74HCT14)
Foot is set to low level, through with door U9B after, its 6th foot is output as low level, after not gate U3F,
12nd foot of U3F is set to high level, and audion Q2 is turned on by this high level signal, after Q2 conducting, and will be with
1st foot of not gate U11 is set to low level, and after NAND gate U11, its 4th foot is set to high level, i.e. DRV-EN
The DRV-EN signal that pin is exported is high level.DRV-EN signal is that the enable of PWM waveform controls letter
Number, when DRV-EN signal is low level, PWM waveform is exported by 74HCT244, when DRV-EN believes
When number being high level, PWM waveform no thoroughfare 74HCT244 output.
But, but there is following defect in foregoing circuit: if the on-the-spot interference ratio of industrial equipment is more severe, when dry
Disturbing after the amplitude of signal exceeded datum, comparator works, and causes OC signal disturbed for low level,
Hardware blocks PWM waveform output immediately.Thus have impact on the normal operating conditions of converter, also have a strong impact on
The loss in various degree of the stability of product and reliability, even cause the user.
In order to solve drawbacks described above, it is necessary to provide a kind of converter overcurrent protection with high anti-jamming capacity
Circuit is to improve the monolithic stability reliability of converter circuit.
Summary of the invention
It is an object of the invention to provide a kind of change that can the most normally work, that capacity of resisting disturbance is strong
Frequently device current foldback circuit skips flow problem to solve the on-the-spot frequent misoperation of converter, thus improves circuit
Reliability.
To achieve these goals, the technical solution used in the present invention is: provide a kind of converter overcurrent protection
Circuit, it includes the first logic control circuit, the second logic control circuit and the 3rd logic control circuit, its
In, described first logic control circuit includes the first NAND gate, the second NAND gate, the first diode and second
Diode, two inputs of described first NAND gate are connected and are connected to one for receiving first order protection signal
The first input pin, the outfan of described first NAND gate is connected with the anode of described first diode, institute
Two inputs of the negative electrode and described second NAND gate of stating the first diode are connected, described second NAND gate defeated
Going out end to be connected with the negative electrode of described second diode, the anode of described second diode is connected to an output pin；
Wherein, described first logic control circuit also include resistance and electric capacity, described resistance be connected to described first with
Between outfan and the input of the second NAND gate of not gate, described electric capacity one end and described second NAND gate
Input is connected and other end ground connection；Described second logic control circuit includes the 3rd NAND gate, the 4th with non-
Door, the 3rd diode and the 4th diode, two inputs of described 3rd NAND gate are connected and are connected to a use
In the second input pin of reception second level protection signal, the outfan and the described 4th of described 3rd NAND gate
One input of NAND gate is connected, another input termination supply voltage of described 4th NAND gate, and the described 4th
The outfan of NAND gate is connected with the negative electrode of described 3rd diode, and the anode of described 3rd diode is connected to
Described output pin, the anode of described 4th diode is connected with the input of described 3rd NAND gate, described
The negative electrode of the 4th diode is connected with the outfan of described 4th NAND gate；Described 3rd logic control circuit bag
Including the 5th NAND gate, an input of described 5th NAND gate is connected to described output pin, the described 5th with
Another input termination supply voltage of not gate, the enable that outfan is PWM waveform of described 5th NAND gate is drawn
Foot.
Its further technical scheme is: described first order protection signal is the level letter being controlled by inverter current
Number, when described inverter current is more than or equal to first pre-set current value, described first order protection signal is
Low level, when described inverter current is less than described first pre-set current value, described first order protection signal is
High level.
Its further technical scheme is: described second level protection signal is the level letter being controlled by inverter current
Number, when described inverter current is more than or equal to second pre-set current value, described second level protection signal is
Low level, when described inverter current is less than described second pre-set current value, described second level protection signal is
High level.
Its further technical scheme is: described first pre-set current value is less than described second pre-set current value.
Its further technical scheme is: described first pre-set current value is 1.8 times of rated current.
Its further technical scheme is: described second pre-set current value is 2.2 times of rated current.
Compared with prior art, the inverter over-current protection circuit that the present invention provides uses hardware to realize by ripple and limits
Stream function, detects impulse waveform one by one, as found to have more than setting electric current within a pulse period
The over-current phenomenon avoidance of value, hardware realizes the circuit start protection of wave limiting so that converter is reaching software mistake
During flow point, can run with hardware limitation current value, decrease converter and the probability of overcurrent protection occurs.Pass through
Arrange two input pins to receive the control signal of two ranks and carry out twin-stage protection, thus provide a kind of super
The reliable circuit of strong anti-interference so that converter can be carried out in the electromagnetic interference environment of extreme for a long time
, reliable and stable operation, high degree reduces various industrial automation equipments and frequently occurs fault at the scene
Situation, solve converter and the misoperation shortcoming to overcurrent protection occur, bring greatly use to user
Convenience.
By description below and combine accompanying drawing, the present invention will become more fully apparent, and these accompanying drawings are used for explaining
Embodiments of the invention.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing inverter over-current protection circuit.
Fig. 2 is the circuit diagram of inverter over-current protection circuit one embodiment of the present invention.
In figure, each description of reference numerals is as follows:
Inverter over-current protection circuit 10
First logic control circuit 12
Second logic control circuit 11
3rd logic control circuit 13
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in embodiment is carried out clear, complete
Describing, reference numerals similar in accompanying drawing represents similar assembly wholely.Obviously, enforcement explained below
Example is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention,
The every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise,
Broadly fall into the scope of protection of the invention.
An embodiment of inverter over-current protection circuit of the present invention is illustrated with reference to Fig. 2, Fig. 2.At the present embodiment
In, described inverter over-current protection circuit 10 includes first logic control circuit the 12, second logic control circuit
11 and the 3rd logic control circuit 13.Described first logic control circuit 12 and the second logic control circuit 11
Input receive respectively the first order protection signal and the second level protection signal, and described first logic control electricity
The outfan of road 12 and the second logic control circuit 11 all with the input of described 3rd logic control circuit 13
Being connected, the outfan output of described 3rd logic control circuit 13 is for controlling the enable of PWM waveform output
Signal.
In the present embodiment, described first logic control circuit 12 includes the first NAND gate U1, second with non-
Door U2, the first diode D1 and the second diode D2, two inputs of described first NAND gate U1 are connected
And it is connected to one for receiving the first input pin OC1 of first order protection signal, described first NAND gate U1
Outfan be connected with the anode of described first diode D1, the negative electrode of described first diode D1 is with described
Two inputs of the second NAND gate U2 are connected, the outfan of described second NAND gate U2 and described two or two pole
The negative electrode of pipe D2 is connected, and the anode of described second diode D2 is connected to output pin TZ1.Preferably,
It is described that described first logic control circuit 12 also includes that resistance R4 and electric capacity C2, described resistance R4 are connected to
Between outfan and the input of the second NAND gate U2 of the first NAND gate U1, described electric capacity C2 one end with
The input of described second NAND gate U2 is connected and other end ground connection.
In the present embodiment, described second logic control circuit 11 includes the 3rd NAND gate U3, the 4th with non-
Door U4, the 3rd diode D13 and the 4th diode D14, two input phases of described 3rd NAND gate U3
Connect and be connected to one for receiving the second input pin OC2 of second level protection signal, described 3rd NAND gate
The outfan of U3 is connected with an input of described 4th NAND gate U4, another of described 4th NAND gate U4
Input termination supply voltage, the outfan of described 4th NAND gate U4 and the moon of described 3rd diode D13
The most connected, the anode of described 3rd diode 13 is connected to described output pin TZ1, described 4th diode
The anode of D14 is connected with the input of described 3rd NAND gate U3, the negative electrode of described 4th diode D14 with
The outfan of described 4th NAND gate U4 is connected.
In the present embodiment, described 3rd logic control circuit 13 includes the 5th NAND gate U5, the described 5th
One input of NAND gate U5 is connected to described output pin TZ1, and another of described 5th NAND gate U5 is defeated
Entering and terminate supply voltage and be pulled to high level always, the outfan of described 5th NAND gate U5 is PWM
The enable pin DRV-EN of waveform.
In the present embodiment, described first order protection signal is the level signal being controlled by inverter current, institute
When stating inverter current more than or equal to first pre-set current value, described first order protection signal is low level,
When described inverter current is less than described first pre-set current value, described first order protection signal is high level.
Similarly, described second level protection signal is the level signal being controlled by inverter current, described converter electricity
When stream is more than or equal to second pre-set current value, described second level protection signal is low level, described frequency conversion
When device electric current is less than described second pre-set current value, described second level protection signal is high level.In this enforcement
In example, set described first pre-set current value less than described second pre-set current value, wherein, described first pre-
If current value is rated current 1.8 times, described second pre-set current value is 2.2 times of rated current.Can manage
Xie Di, described first, second pre-set current value is not limited to above-mentioned situation, and it can be arranged as required to as it
Its current value.
Describe the operation principle of frequency conversion current foldback circuit of the present invention referring to the drawings in detail.
When inverter current is more than or equal to the first pre-set current value (1.8 times of rated current), first is defeated
Entering pin OC1 effective, the first order protection signal that it receives is low level signal, this low level signal warp
Cross the 12nd of the first NAND gate U1 (74HC132) the, after 13 feet (two inputs) input by this NAND gate
U1 11 feet (outfan) output high level, high level now through the first diode D1 (IN5819),
Through the 1st, 2 foot inputs of the second NAND gate U2 (74HC132) and simultaneously to electric capacity C2 charging, pass through
In 3 foot output low levels after second NAND gate U2, this low level is through the second diode D2 (IN5819)
After control pin TZ1 output low level.DRIVE drives pin to be connected to VCC and be essentially pulled up to always
High level, the low level controlling pin TZ1 output delivers to the defeated of the 5th NAND gate U5 (74VHC1G00)
Enter end (the 1st foot), its outfan (the 4th foot) output high level signal after this NAND gate U5
DRV-EN, DRV-EN signal is used for controlling to produce the enable foot of the 74HC244 of 6 road PWM waveform.
When converter normally works, this DRV-EN signal is low level, this DRV-EN when there is over-current phenomenon avoidance
Signal immediately becomes high level, thus blocks the output of converter.
When the output electric current of converter is varied down to the rated current less than 1.8 times, the first input pin OC1
Input signal be set to high level, this high level signal is through the 12nd, 13 feet (two of the first NAND gate U1
Input) input after by 11 feet (outfan) output low level of this NAND gate U1, now C2 and R4
Forming a discharge loop, time constant is 200Us, low level now through the second NAND gate U2 the 1st,
2 foot inputs, then export high level at its 3rd foot, and this high level is ended by the second diode D2, from
And the output signal controlling pin TZ1 is set to high level.Described output signal delivers to the 5th NAND gate U5
The 1st foot, after NAND gate its 4th foot output DRV-EN signal be low level, this time-varying
Frequently device is in again normal operating conditions.As it has been described above, the duty of this circuit has reached fabulous wave limiting
Effect.
When the output electric current of converter is more than or equal to the second pre-set current value (2.2 times of rated current),
Second input pin OC2 is effective, and the second level protection signal that it receives is low level signal, this low level
Signal is through the 4th, the 5 foot inputs of U3 (74HC132), at its 6th foot after this NAND gate U3
This high level is also input to the 4th NAND gate U4 (74HC132) from the 9th foot (input) by output high level,
And now the 10th foot (another input) of the 4th NAND gate U4 is high level by 3.3V pull-up.Therefore,
After the 4th NAND gate U4, the 8th foot output low level, this low level is again through the 3rd diode D13
(IN5819) pin TZ1 output low level is being controlled, therefore, based on above-mentioned principle, finally the 5th after
The DRV-EN signal that NAND gate U5 outfan (the 4th foot) exports is high level, thus blocks converter
Output.Now, the 4th diode D14 (IN5819) plays interlocked use, when the 8th foot output of U4 is low
During level, no matter the second input pin OC2 received signal is high level or low level, the 8th of U4
Foot perseverance output low level, this low level controls the output of pin TZ1 after diode D13 and is set to low level,
And the DRV-EN signal exported at its 4th foot after NAND gate U5 is high level.
As it has been described above, the protection circuit of the present invention is when interference signal amplitude is higher than 1.8 times or equal to 1.8 times of volumes
Determine electric current and below 2.2 times of rated current, this interference signal by the first input pin OC1 process,
When interference signal amplitude is drawn by the second input at or above more than 2.2 times of rated current, interference signal
Foot OC2 process.And disturbing the time constant of the block PWM that signal caused is R4, C2 product
Result.Reason is that it is low that OC1 receives when disturbing signal (amplitude is less than 2.2 times of rated current) to come
The enable letter that level exports after the process of the first logic control circuit 12 and the 3rd logic control circuit 13
Number DRV-EN is high level, thus blocks the output of converter, and under the effect of RC circuit, 6 tunnels
PWM waveform blocking time is the result of R4 and C2 product.After interference signal is in the past, OC1 weighs again
Newly being set to high level, DRV-EN signal becomes low level, and now converter normally works.Therefore signal is disturbed
The time turning off PWM waveform after Laiing is the product of R4 and C2.So this circuit can effectively suppress width
Value is less than the interference signal of 2.2 times of rated current.
Therefore, the inverter over-current protection circuit that the present invention provides is a kind of superpower jamproof reliable circuit,
It can carry out long, reliable and stable operation, high degree in the electromagnetic interference environment of extreme
Reduce various industrial automation equipment and frequently occur the situation of fault at the scene, solve converter and malfunction occurs
Make the shortcoming to overcurrent protection, bring great ease of use to user.
It should be noted that other electronic components not described are at this in inverter over-current protection circuit of the present invention
Circuit act as technology well-known to those skilled in the art, is not described in detail in this.
Above in association with preferred embodiment, invention has been described, but the invention is not limited in disclosed above
Embodiment, and amendment, the equivalent combinations that the various essence according to the present invention is carried out should be contained.
Claims (6)
1. an inverter over-current protection circuit, for converter realizes wave limiting protection, its feature exists
Include in described inverter over-current protection circuit:
First logic control circuit, described first logic control circuit include the first NAND gate, the second NAND gate,
First diode and the second diode, two inputs of described first NAND gate are connected and are connected to one for connecing
Receive the first input pin of first order protection signal, the outfan of described first NAND gate and described one or two pole
The anode of pipe is connected, and the negative electrode of described first diode is connected with two inputs of described second NAND gate, institute
The negative electrode of the outfan and described second diode of stating the second NAND gate is connected, the anode of described second diode
It is connected to an output pin；Wherein, described first logic control circuit also includes resistance and electric capacity, described electricity
Resistance is connected between outfan and the input of the second NAND gate of described first NAND gate, described electric capacity one end
It is connected and other end ground connection with the input of described second NAND gate；
Second logic control circuit, described second logic control circuit include the 3rd NAND gate, the 4th NAND gate,
3rd diode and the 4th diode, two inputs of described 3rd NAND gate are connected and are connected to one for connecing
Receive the second level protection signal the second input pin, the outfan of described 3rd NAND gate with the described 4th with non-
One input of door is connected, and another input termination supply voltage of described 4th NAND gate, the described 4th with non-
The outfan of door is connected with the negative electrode of described 3rd diode, and the anode of described 3rd diode is connected to described
Output pin, the anode of described 4th diode is connected with the input of described 3rd NAND gate, and the described 4th
The negative electrode of diode is connected with the outfan of described 4th NAND gate；
3rd logic control circuit, described 3rd logic control circuit includes the 5th NAND gate, the described 5th with
One input of not gate is connected to described output pin, another input termination power supply electricity of described 5th NAND gate
Pressure, the enable pin that outfan is converter PWM waveform of described 5th NAND gate.
2. inverter over-current protection circuit as claimed in claim 1, it is characterised in that: the described first order is protected
Protecting signal is the level signal being controlled by inverter current, and described inverter current is pre-more than or equal to one first
If during current value, described first order protection signal is low level, and described inverter current is first pre-less than described
If during current value, described first order protection signal is high level.
3. inverter over-current protection circuit as claimed in claim 2, it is characterised in that: the described second level is protected
Protecting signal is the level signal being controlled by inverter current, and described inverter current is pre-more than or equal to one second
If during current value, described second level protection signal is low level, and described inverter current is second pre-less than described
If during current value, described second level protection signal is high level.
4. inverter over-current protection circuit as claimed in claim 3, it is characterised in that: described first presets
Current value is less than described second pre-set current value.
5. inverter over-current protection circuit as claimed in claim 4, it is characterised in that: described first presets
Current value is 1.8 times of rated current.
6. inverter over-current protection circuit as claimed in claim 4, it is characterised in that: described second presets
Current value is 2.2 times of rated current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210087498.0A CN103368366B (en) | 2012-03-29 | 2012-03-29 | Inverter over-current protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210087498.0A CN103368366B (en) | 2012-03-29 | 2012-03-29 | Inverter over-current protection circuit |
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| Publication Number | Publication Date |
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| CN103368366A CN103368366A (en) | 2013-10-23 |
| CN103368366B true CN103368366B (en) | 2016-10-19 |
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| CN201210087498.0A Active CN103368366B (en) | 2012-03-29 | 2012-03-29 | Inverter over-current protection circuit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155783B (en) * | 2016-12-02 | 2020-09-22 | 长沙市日业电气有限公司 | Circuit for improving overcurrent protection anti-interference capability |
| CN110247615B (en) * | 2018-03-09 | 2024-04-12 | 深圳市蓝海华腾技术股份有限公司 | Wave-by-wave current limiting control system and method based on DSP chip and motor controller |
| CN109104216B (en) * | 2018-10-31 | 2024-05-10 | 深圳市创仁科技有限公司 | M-BUS repeater |
| CN110346637A (en) * | 2019-08-23 | 2019-10-18 | 邢台子中电子科技有限公司 | A kind of method and device of sinusoid information Digital Extraction |
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| CN1452176A (en) * | 2002-04-12 | 2003-10-29 | 三星电子株式会社 | Semiconductor memory delay circuit |
| CN101355319A (en) * | 2008-09-17 | 2009-01-28 | 南京航空航天大学 | Method for improving operation reliability of current-control type inverter output short circuit |
| CN101567668A (en) * | 2008-04-24 | 2009-10-28 | 骅讯电子企业股份有限公司 | Voltage detection type overcurrent protection device applied to D-class amplifier |
| CN101861034A (en) * | 2010-04-16 | 2010-10-13 | 北京工业大学 | Protective circuit for electronic ballast with RC timing unit |
| CN202111463U (en) * | 2011-06-24 | 2012-01-11 | 深圳市正川电气技术有限公司 | Protection circuit for frequency converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007222000A (en) * | 2007-06-04 | 2007-08-30 | Ricoh Co Ltd | Switching regulator having overcurrent protection function and electronic apparatus using the regulator |
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|---|---|---|---|---|
| CN1452176A (en) * | 2002-04-12 | 2003-10-29 | 三星电子株式会社 | Semiconductor memory delay circuit |
| CN101567668A (en) * | 2008-04-24 | 2009-10-28 | 骅讯电子企业股份有限公司 | Voltage detection type overcurrent protection device applied to D-class amplifier |
| CN101355319A (en) * | 2008-09-17 | 2009-01-28 | 南京航空航天大学 | Method for improving operation reliability of current-control type inverter output short circuit |
| CN101861034A (en) * | 2010-04-16 | 2010-10-13 | 北京工业大学 | Protective circuit for electronic ballast with RC timing unit |
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| CN103368366A (en) | 2013-10-23 |
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Inventor after: Chen Pengcheng Inventor after: Wang Wujun Inventor after: Liu Hongyi Inventor after: Zhu Zhihua Inventor before: Chen Pengcheng Inventor before: Chen Zhiling Inventor before: Ma Zhefeng |
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Free format text: CORRECT: INVENTOR; FROM: CHEN PENGCHENG CHEN ZHILING MA ZHEFENG TO: CHEN PENGCHENG WANG WUJUN LIU HONGYI ZHU ZHIHUA |
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