CN110995244B - Automatic direction detection circuit of bidirectional transmission interface - Google Patents
Automatic direction detection circuit of bidirectional transmission interface Download PDFInfo
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- CN110995244B CN110995244B CN201911280960.7A CN201911280960A CN110995244B CN 110995244 B CN110995244 B CN 110995244B CN 201911280960 A CN201911280960 A CN 201911280960A CN 110995244 B CN110995244 B CN 110995244B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/01759—Coupling arrangements; Interface arrangements with a bidirectional operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an automatic direction detection circuit of a bidirectional transmission interface, which comprises a D trigger, a primary NAND gate and a final NAND gate, wherein the D trigger, the primary NAND gate and the final NAND gate are configured corresponding to signal input and output on any side; the pre-driving signal is connected to the D end of the D trigger, the input signal is connected to the Clk end of the D trigger, the Q end of the D trigger outputs the enabling signal of the corresponding side through the primary NAND gate and the final NAND gate in sequence, the detection circuit is provided with periodic Reset units which are respectively connected to the Reset ends of the D trigger based on the input signals at two sides, and the output ends of the primary NAND gates at two sides are respectively connected to one input end of the primary NAND gate at the other side in a wire jumping mode. By applying the detection circuit design of the invention, whether the output of the local side is opened or not can be periodically detected through the rising edge or the falling edge of the input side signal, and the enable signal can be reset; the hardware loss of automatic direction identification is greatly reduced, and the flexibility of automatic direction identification is improved.
Description
Technical Field
The invention relates to a detection scheme of output enabling in a data transmission interface, in particular to an automatic direction detection circuit of a bidirectional transmission interface.
Background
Half-duplex transmission refers to a transmission scheme in which reception and transmission share a single transmission channel, but only data can be transmitted or received at the same time. On the other hand, full duplex transmission refers to a data transmission mode that occurs in both directions simultaneously. For example: an intercom is a half-duplex device that allows only one party to talk at a time. In contrast, a telephone is a full duplex device, and two parties to a conversation can have a conversation simultaneously.
In the chip design of such devices, a bidirectional interface Circuit is usually used for half-duplex data transmission, and time division multiplexing is performed through an input interface and an output interface, so that the number of input and output ports of the chip and the complexity of Printed Circuit Board (PCB) wiring can be effectively reduced.
However, in the bidirectional transmission interface, the hardware loss of the existing automatic direction identification is large, and the problem of data transmission delay exists.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an automatic direction detection circuit for a bidirectional transmission interface, so as to improve the efficiency and flexibility of automatic identification of the direction of such an interface.
In order to achieve the above object, the present invention adopts a technical solution that an automatic direction detection circuit of a bidirectional transmission interface includes:
the first D flip-flop, a first primary NAND gate and a first final NAND gate, wherein an A-side pre-driving signal is connected to a D end of the first D flip-flop, an A-side input signal is connected to a Clk end of the first D flip-flop, a Q end of the first D flip-flop is connected to one input end of the first primary NAND gate, an output end of the first primary NAND gate and a total enable signal are connected to the first final NAND gate, and the first final NAND gate outputs an enable signal output by the A side;
the second D flip-flop, a second primary NAND gate and a second final NAND gate, wherein a B-side pre-driving signal is connected to a D end of the second D flip-flop, a B-side input signal is connected to a Clk end of the second D flip-flop, a Q end of the second D flip-flop is connected to one input end of the second primary NAND gate, an output end of the second primary NAND gate and a total enable signal are connected to the second final NAND gate, and the second final NAND gate outputs an enable signal output by the B side;
the input signals of the side A and the side B are accessed into the unit, and the output of the unit is respectively accessed into Reset ends of the first D trigger and the second D trigger;
and the output end of the first primary NAND gate is connected with the other input end of the second primary NAND gate in a jumper way, and the output end of the second primary NAND gate is connected with the other input end of the first primary NAND gate in a jumper way.
Furthermore, an and gate, a third nand gate, a buffer, two MOS transistors and a capacitor C are arranged in the periodic reset unit, an a-side input signal and a B-side input signal are respectively connected to two input ends of the and gate and the third nand gate, an output end of the and gate is connected to a gate of the first MOS transistor, a drain of the first MOS transistor is connected to the current source I, an output end of the third nand gate is connected to a gate of the second MOS transistor, a source of the second MOS transistor is connected to the ground in common with one end of the capacitor C, a drain of the second MOS transistor is connected to an input end of the buffer in common with the other end of the capacitor C and a source of the first MOS transistor, and an output end of the buffer is a unit output of the reset signal.
The detection circuit design of the invention has prominent substantive features and remarkable progress: the circuit can periodically detect whether the output of the local side is opened or not through the rising edge or the falling edge of the input side signal, and can reset the enable signal; the hardware loss of automatic direction recognition is greatly reduced, and the flexibility of automatic direction recognition is improved.
Drawings
FIG. 1 is a schematic diagram of the circuit connection for automatic direction detection of the bi-directional transmission interface of the present invention.
Fig. 2 is a detailed circuit connection schematic diagram of the periodic reset unit of fig. 1.
Detailed Description
The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.
Aiming at the defects of the prior art, the designer of the invention carries out comprehensive analysis on the aspect of circuit structure, combines self experience and creative labor, seeks optimization breakthrough in the automatic direction identification of the bidirectional transmission interface, and innovatively provides an automatic direction detection circuit so as to improve the flexibility and transmission efficiency of the automatic direction identification of the interface.
The connection diagram of the automatic direction detection circuit of the bidirectional transmission interface shown in fig. 1 is shown. It can be seen from the figure that it includes: a first D flip-flop 11, a first primary nand gate 12 and a first final nand gate 13, wherein an a-side pre-driving signal is connected to a D terminal of the first D flip-flop 11, an a-side input signal is connected to a Clk terminal of the first D flip-flop 11, a Q terminal of the first D flip-flop 11 is connected to one input terminal of the first primary nand gate 12, an output terminal of the first primary nand gate 12 and a total Enable signal Enable are connected to the first final nand gate 13, and the first final nand gate 13 outputs an Enable signal output by the a side; a second D flip-flop 21, a second primary nand gate 22 and a second final nand gate 23, wherein the B-side pre-driving signal is connected to the D terminal of the second D flip-flop 21, the B-side input signal is connected to the Clk terminal of the second D flip-flop 21, the Q terminal of the second D flip-flop 21 is connected to one input terminal of the second primary nand gate 22, the output terminal of the second primary nand gate 22 and the total enable signal are connected to the second final nand gate 23, and the second final nand gate 23 outputs the enable signal output by the B side; the input signals of the A side and the B side of the periodic Reset unit 3 are connected into the unit, and the output of the unit is respectively connected to the Reset ends of the first D flip-flop 11 and the second D flip-flop 12; and the output end of the first-stage nand gate 12 is jumpered into the other input end of the second-stage nand gate 22, and the output end of the second-stage nand gate 22 is jumpered into the other input end of the first-stage nand gate 12.
It should be additionally described to the diagram based on the above circuit configuration, where the a-side Input signal is indicated as a _ Input and the B-side Input signal is indicated as B _ Input. And the output enable signal AEnable of the side A and the output enable signal BEnable of the side B are both logic 0 valid, and enable the output of the bidirectional transmission interface. Further, a _ Output _ PreDriver indicates a predrive signal Output from the a side, B _ Output _ PreDriver indicates a predrive signal Output from the B side, and the predrive signal is logic 1 when the a/B sides do not Output each other.
As a further refinement of one of the above innovative features, the periodic reset unit 3 is provided with an and gate 31, a third nand gate 32, a buffer 35 (also referred to as a buffer amplifier), two MOS transistors, and a capacitor C. The concrete connection is as follows: the a-side Input signal a _ Input and the B-side Input signal B _ Input are respectively connected to two Input ends of an and gate and a third nand gate, that is, the and gate 31 outputs a logical and of two Input signals, and the third nand gate 32 outputs a logical nand of two Input signals. The output end of the and gate 31 is connected to the gate of the first MOS transistor 33, the drain of the first MOS transistor 33 is connected to the current source I, the output end of the third nand gate 32 is connected to the gate of the second MOS transistor 34, the source of the second MOS transistor 34 is connected to one end of the capacitor C in common, the drain of the second MOS transistor 34 is connected to the other end of the capacitor C and the source of the first MOS transistor 33 in common, and the output end of the buffer 35 is the unit output of the reset signal.
Based on the above circuit connection structure, the function of the automatic direction detection can be realized as follows:
the bidirectional transmission interface circuit periodically detects whether the output of the local side is opened or not through the rising edge or the falling edge of the input side signal. Specifically, the interface circuit has two input and output functional modules at the same time. When the output function is in default non-enable state, namely in a three-state, the side pre-drive signal is 1; and the side input signal generates a rising edge or a falling edge, namely the side signal is considered to enable the input function, the side output function is closed, and the automatic direction recognition is completed.
The resource consumption is reduced during half-duplex transmission, the periodic real-time detection can be realized, and the flexibility of automatic direction identification is improved; the automatic direction identification circuit simplifies a handshake header protocol of a Host slave end when data start transmission is carried out under the traditional half-duplex data transmission, thereby reducing the resource consumption.
By adopting the periodic reset signal (A & B is high), the data transmission direction can be detected in real time in each frame, the data transmission direction has no memory function, and the problem of overlarge transmission delay of the first frame of the transmitted data is avoided.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and modifications and equivalents within the scope of the claims may be made by those skilled in the art and are included in the scope of the present invention.
Claims (2)
1. An automatic direction detection circuit for a bidirectional transmission interface, comprising:
the first D flip-flop, a first primary NAND gate and a first final NAND gate, wherein an A-side pre-driving signal is connected to a D end of the first D flip-flop, an A-side input signal is connected to a Clk end of the first D flip-flop, a Q end of the first D flip-flop is connected to one input end of the first primary NAND gate, an output end of the first primary NAND gate and a total enable signal are connected to the first final NAND gate, and the first final NAND gate outputs an enable signal output by the A side;
the second D flip-flop, a second primary NAND gate and a second final NAND gate, wherein a B-side pre-driving signal is connected to a D end of the second D flip-flop, a B-side input signal is connected to a Clk end of the second D flip-flop, a Q end of the second D flip-flop is connected to one input end of the second primary NAND gate, an output end of the second primary NAND gate and a total enable signal are connected to the second final NAND gate, and the second final NAND gate outputs an enable signal output by the B side;
the periodic Reset unit receives input signals of an A side and a B side, wherein the input signals of the A side and the B side comprise periodic Reset signals, and the periodic Reset unit periodically controls Reset ends of the first D flip-flop and the second D flip-flop to Reset the first D flip-flop and the second D flip-flop based on the periodic Reset signals;
and the output end of the first primary NAND gate is connected with the other input end of the second primary NAND gate in a jumper way, and the output end of the second primary NAND gate is connected with the other input end of the first primary NAND gate in a jumper way.
2. The automatic direction detection circuit of a bi-directional transmission interface of claim 1, wherein: the periodic reset unit is internally provided with an AND gate, a third NAND gate, a buffer, two MOS tubes and a capacitor C, wherein an A-side input signal and a B-side input signal are respectively connected with two input ends of the AND gate and the third NAND gate, the output end of the AND gate is connected with a grid of the first MOS tube, a drain electrode of the first MOS tube is connected with a current source I, the output end of the third NAND gate is connected with a grid of the second MOS tube, a source electrode of the second MOS tube is connected with one end of the capacitor C in a common mode and is grounded, a drain electrode of the second MOS tube is connected with the other end of the capacitor C and a source electrode of the first MOS tube in a common mode and is connected with the input end of the buffer, and the output end of the buffer is the unit output of the reset signal.
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| CN201911280960.7A CN110995244B (en) | 2019-12-13 | 2019-12-13 | Automatic direction detection circuit of bidirectional transmission interface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911280960.7A CN110995244B (en) | 2019-12-13 | 2019-12-13 | Automatic direction detection circuit of bidirectional transmission interface |
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| CN110995244A CN110995244A (en) | 2020-04-10 |
| CN110995244B true CN110995244B (en) | 2022-08-09 |
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| CN113872829B (en) * | 2021-09-27 | 2023-02-28 | 西安易朴通讯技术有限公司 | Bidirectional data transmission testing device and testing method |
| CN118100639B (en) * | 2024-04-24 | 2024-07-12 | 瓴科微(上海)集成电路有限责任公司 | Bidirectional voltage conversion circuit with direction self-identification function |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594341A (en) * | 2011-01-13 | 2012-07-18 | 三星电子株式会社 | Digital phase frequency detector, digital phase locked loop and method of detecting the same |
| CN107979359A (en) * | 2018-01-11 | 2018-05-01 | 苏州锴威特半导体有限公司 | A kind of clock synchronization circuit for maintaining fixed pulse |
| CN110311671A (en) * | 2019-06-28 | 2019-10-08 | 西安紫光国芯半导体有限公司 | A kind of feedback sense circuit |
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2019
- 2019-12-13 CN CN201911280960.7A patent/CN110995244B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594341A (en) * | 2011-01-13 | 2012-07-18 | 三星电子株式会社 | Digital phase frequency detector, digital phase locked loop and method of detecting the same |
| CN107979359A (en) * | 2018-01-11 | 2018-05-01 | 苏州锴威特半导体有限公司 | A kind of clock synchronization circuit for maintaining fixed pulse |
| CN110311671A (en) * | 2019-06-28 | 2019-10-08 | 西安紫光国芯半导体有限公司 | A kind of feedback sense circuit |
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