JP2009290812A - Dead time control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for reducing switching loss in a synchronous rectifying circuit of a switching stage including a high-side control transistor and a low-side synchronous rectifying transistor which is coupled at a switching node. <P>SOLUTION: A switching stage receives an input voltage and provides a controlled output voltage at an output contact. A circuit includes a first circuit portion and a second circuit portion. The first circuit portion senses the waveshape edges of a first signal at a gate terminal of the low-side synchronous rectifying transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage. The second circuit portion calibrates the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to attain minimal power loss. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a converter circuit, and more particularly to a control circuit that prevents conduction between a high-side FET and a low-side FET in the converter circuit and reduces dead time.

  In DC-DC conversion, a good converter is generally determined based on conversion efficiency. This efficiency is determined according to how much power loss such as switching loss and loss due to the on-resistance of the power device is small in the converter.

  Synchronous rectifier circuits are widely used in order to reduce switching loss in spite of complicated control. In the synchronous rectifier circuit, one of the main causes of power loss is a delay between the control of the high-side / control transistor and the control of the low-side / synchronous rectifier transistor.

FIG. 1 shows a known high speed synchronous rectification step-down (buck) converter circuit 10. The buck converter circuit 10 includes a switching stage, and the switching stage includes a high-side transistor Q ₁ that is a power device for control and a low-side transistor Q ₂ that is a power device for synchronous rectification. The transistor Q ₁ and the low side transistor Q ₂ are connected by a switching node. The switching stage receives the DC input voltage V _IN and provides a well controlled DC output voltage V _O at the output contact. The buck converter circuit 10 includes an input capacitor C ₁ connected in parallel with the switching stage, an output inductor L connected between the switching node and the output contact, and an output contact having a DC output voltage V _O. And an output capacitor C ₂ connected thereto. Load is connected in parallel with the output capacitor C _2.

Since the high-side transistor Q ₁ and the low-side transistor Q ₂ are turned on / off by pulse width modulation (PWM) as usual, when the high-side transistor Q ₁ is on, the low-side transistor Q ₂ is off and the low-side transistor Q ₂ is turned on. _{When 2} is on, the high-side transistor Q ₁ is off. The pulse width modulation is controlled, even if the DC input voltage _VIN that may be supplied by the battery of the portable electronic device varies with age, temperature, power demand, etc. V _O is maintained.

Since there is a possibility of generating a short circuit in the input circuit, care must be taken to eliminate a state in which the high side transistor Q ₁ and the low side transistor Q ₂ are simultaneously turned on. Therefore, as shown in FIG. 2, a constant dead time is always supplied when both the high-side transistor Q ₁ and the low-side transistor Q ₂ are off. It is desirable to reduce this dead time as much as possible. To increase the circuit efficiency, it is preferable that the dead time is closer to zero.

A conventional attempt to control the dead time shown in FIG. 3 includes a fixed delay method. In this way, the optimal delay can be varied by load, line, and power device when the high side transistor Q ₁ and the low side transistor Q ₂ are off. The dead time itself cannot be adjusted to obtain the optimum delay for each given condition.

  As shown in FIG. 4, the adaptive control method is a better control method than the fixed delay method, but does not adjust for changes in load, line, and temperature.

As shown in FIG. 5, the predictive control method monitors the voltage V _SW at the switching node connecting the high side transistor Q ₁ and the low side transistor Q ₂ and continues the delay until the delay reaches a predetermined value. And adjust. In this method, the voltage V _SW must be lower than the ground voltage and is compared with a fixed voltage. The voltage V _SW is a negative voltage sufficient to produce an optimum delay that requires minimal power loss. Due to the delay of the voltage V _SW comparator, this method does not achieve an optimal dead time.

  The object of the present invention is to provide a fixed delay to any type of rectifier / power device by comparing the low side gate drive (LGD) edge and the switching node (VSW) / high side gate drive (HGD) edge. Thus, it is an object of the present invention to provide an improved solution for obtaining an optimal dead time for reducing power loss.

  Furthermore, an object of the present invention is to reduce or eliminate conduction loss, reverse recovery loss, or penetration loss.

  According to the present invention, there is provided a synchronous rectifier circuit or a circuit that reduces switching loss in a switching stage including a high-side control transistor and a low-side synchronous rectifier transistor connected at a switching node. The switching stage receives the input voltage and provides a controlled output voltage at the output contact. The circuit includes a first circuit unit and a second circuit unit. The first circuit unit detects the waveform edge of the first signal and the waveform edge of the first voltage at the gate of the low-side synchronous rectification transistor, and detects between the waveform edge of the first signal and the waveform edge of the first voltage. Determine the delay. The second circuit unit calibrates the first signal and the first voltage, and matches the waveform edge of the first signal and the waveform edge of the first voltage.

  For further optimization, the circuit can be trimmed to achieve a fixed delay effect. This dead time control circuit can be applied to all types of power switching devices used in a half bridge or synchronous rectification step-down type.

  Other features and advantages of the present invention will become apparent from the following description based on the accompanying drawings.

FIG. 1 shows PWM input to the gates of the high-side transistor Q ₁ and the low-side transistor Q ₂ . The signal to the high-side transistor Q ₁ is represented by HGD, and the signal to the low-side transistor Q ₂ is converted by the inverter 12 and represented by LGD, and is shown as an LGD waveform in FIG. The high side transistor Q ₁ and the low side transistor Q ₂ are connected by a switching node.

FIG. 2 is a diagram illustrating the relationship between the rising edge and the falling edge of the LGD signal waveform, the voltage V _SW waveform (VSW) at the switching node, and / or the rising edge and the falling edge of the HGD signal waveform.

Returning to FIG. 1, according to the present invention, the low-side transistor Q ₂ is optimal for a high-speed synchronous step-down (buck) converter, which is made to switch at high speed, for example, within 1 nanosecond. The dead time occurs when the gate signal of the low-side transistor Q ₂ coincides with the voltage V _SW waveform (VSW) and / or the rising / falling edge of the HGD signal waveform.

Synchronization of the voltage V _SW waveform (VSW) edge and / or the HGD signal waveform edge and the LGD signal waveform edge is achieved via an analog or digital phase synchronization circuit (PLL) to eliminate phase errors. be able to. Therefore, as shown in FIG. 6, the PLL circuit 15 is connected to the circuit of FIG. 1, and each edge of the voltage V _SW (VSW) and / or the HGD signal requires one phase detection circuit set. To do.

When the rising edge of the voltage V _SW (VSW) and / or the HGD signal is used, for example, the LGD signal waveform and the voltage V _SW waveform (VSW) and / or the HGD signal waveform in FIGS. If there is no overlap between, the LGD signal and the voltage V _SW (VSW) and / or the HGD signal waveform will be adjusted by the delay circuits 11 and 13 to introduce the overlap. When there is an overlap, the LGD signal and the voltage V _SW (VSW) and / or the HGD signal waveform will be adjusted to eliminate the overlap.

The conduction loss or reverse recovery loss of the synchronous rectifier circuit is processed by monitoring two control signals, namely, the LGD signal and the voltage V _SW (VSW) and / or the synchronous rectifier circuit control signal of the HGD signal. Is done. As shown in FIG. 7, the edges of both the LGD signal and the voltage V _SW (VSW) and / or the HGD signal are first detected by the delay detection unit of the circuit 20 and then corrected by the calibration unit. Is done. First, in order to make a better adjustment in the delay control loop in the delay detection unit, the voltage V _SW (VSW) and / or the HGD signal is detected by the edge detection circuit 22 and an optional delay detection circuit 26. The LGD signal is detected by the edge detection circuit 24 and processed via the optional delay detection circuit 28.

  In the calibration unit, the edge comparison circuits 34 and 36 compare the signals from the delay detection circuits 26 and 28 with each other. Next, the edge comparison circuit 34 sends the presettable up / down counter circuit 38 to the edge comparison circuit 36. Sends a command to the presettable up / down counter circuit 40 to perform addition or subtraction counter processing. The counter circuit 38 receives an input from the rising range selection circuit 42, and the counter circuit 40 receives an input from the falling range selection circuit 44.

The counter circuits 38 and 40 can be preloaded to minimize the edge adjustment operation. The output of the n-bit counter of the counter circuit 38 is sent to the rising edge dt control circuit 46, and the output of the n-bit counter of the counter circuit 40 is It is transferred to the falling edge dt control circuit 48. This n-bit counter value is decoded and selects the corresponding delay. The operation of the circuit 20 continues until the edges of both waveforms of the voltage V _SW (VSW) and / or the HGD signal and the LGD signal are aligned.

  The circuit 20 compares the two signals and generates a signal that reduces or increases the delay depending on the timing situation. The delay is adjusted by the transmitted signal. This operation is performed at both the rising edge and falling edge of the control signal. Furthermore, individual delays are incorporated into this automatic calibration and will correct the detected errors.

The circuit 20 finds the optimum delay that is independent of the output situation, ie, load, line temperature, and / or power device. The delay can be adjusted by any delay while sensing the edges of the waveform. In order for the circuit 20 to operate correctly, the voltage V _SW (VSW) and / or the HGD signal need not fall below the ground level.

  Next, the fast control signal detection of the synchronous rectifier converter will be described.

As shown in FIG. 8, it has capacitors C0a and C1a connected in series, a split capacitor 80a connected between the LGD node and the GND node, and capacitors C0b and C1b connected in series, It is used to detect the edge of fast operation at a potential different from that of the split capacitor 80b connected between the VSW / HGD node and the GND node. On the other hand, the split capacitors 80a and 80b are used for various purposes, but the famous one is the joint use with the synchronous rectifier converter. The signal delay detected in the control loop is often critical for time-dependent control. In the case of a synchronous rectifier converter, the detection of the drive signal and / or the voltage V _{SW at} the switching node is very useful information to optimize the efficiency and performance of the synchronous rectifier converter. The swing of the switching node signal to the sensing contact can be limited using a split resistor or a clamp circuit. By limiting the swing, more power is consumed and the detection process is slowed down.

  The advantage of using split capacitors 80a and 80b is the loss in speed and DC power. Split capacitors 80a and 80b need to be charged during the transition period. However, the divided capacitors 80a and 80b once charged do not consume power. For applications that require a constant DC current, parallel split resistors 82a and 82b can be added to split capacitors 80a and 80b to maintain the DC voltage value. The dividing resistor 82a is connected between the LGD node and the GND node, and has resistors R0a and R1a connected in series. The dividing resistor 82b is connected between the VSW / HGD node and the GND node, and is connected in series. Resistors R0b and R1b are provided.

  Although the present invention has been described based on specific embodiments, the present invention includes other modifications that are apparent to those skilled in the art without departing from the scope of the claims. In other words, the present invention is not limited to the examples in the specification, and is limited only by the scope of the claims.

FIG. 6 is a circuit diagram of a high-speed synchronous rectification step-down (buck) converter having a switching stage.

2 is a time chart showing a PWM signal and an LGD signal when a transistor of the switching stage of FIG. 1 is turned on and off.

FIG. 2 is a circuit diagram having a switching stage and a well-known time chart showing a fixed delay for controlling a dead time.

FIG. 4 is a circuit diagram having a switching stage and a gate driving circuit using a known adaptive control method for controlling dead time.

It is a circuit and block diagram which have a switching stage, a detection circuit, and a gate drive circuit using the well-known predictive control method which controls a dead time.

FIG. 2 is a schematic circuit diagram and a block diagram for detecting and calibrating an edge delay of a voltage V _SW (VSW) and / or a gate voltage (HGD) of a high-side transistor and an LGD signal in the circuit of FIG.

FIG. 2 is a block diagram for detecting and calibrating an edge delay of a voltage V _SW (VSW) and / or a gate voltage (HGD) of a high-side transistor and an LGD signal in the circuit of FIG. 1.

FIG. 8 is a circuit and block diagram of FIG. 7 that uses split capacitors to detect fast-moving edges with different potentials and / or high-voltage signals.

Explanation of symbols

10: step-down (buck) converter circuit 11, 13: delay circuit 12: inverter 15: PLL circuit 20: circuit 22, 24: edge detection circuit 26, 28: delay detection circuit 34, 36: edge comparison circuit 38, 40: Presettable up / down counter circuit 42: rising range selection circuit 44: falling range selection circuit 46: rising edge dt control circuit 48: falling edge dt control circuits 80a, 80b: dividing capacitors 82a, 82b: dividing resistor C ₁ : Input capacitor C ₂ : Output capacitors C 0 a, C _{1 a,} C 0 b, C ₁ b: Capacitor L: Output inductors R 0 a, R _{1 a} , R 0 b, R ₁ b: Resistor Q ₁ : High side transistor Q ₂ : Low side transistor V _IN : DC input voltage V _O : DC Output voltage V _SW : Voltage

Claims (19)

Reduce switching losses in the synchronous rectifier circuit of the switching stage, comprising a high side control transistor and a low side synchronous rectifier transistor connected at the switching node, which receives the input voltage and is controlled at the output contact Output voltage, and
A first circuit unit that detects a waveform edge of the first signal and the first voltage at the gate of the low-side synchronous rectification transistor and determines a delay between the waveform edge of the first signal and the waveform edge of the first voltage When,
A circuit comprising: a second circuit unit that calibrates the first signal and the first voltage and matches the waveform edge of the first signal and the waveform edge of the first voltage.   An input capacitor connected in parallel with the switching stage, an output inductor connected between the switching node and the output contact, an output capacitor connected to the output contact having the output voltage, and connected in parallel with the output capacitor The circuit of claim 1, comprising a load.   The circuit of claim 1, wherein the circuit is self-adjustable to changes in load, line, temperature, and power device.   The circuit of claim 1, wherein the first voltage need not be lower than a ground voltage.   The synchronous rectifier circuit operates at an optimum dead time that occurs when the low-side transistor that performs high-speed switching and the gate signal of the low-side transistor are aligned with the rising and falling edges of the first voltage waveform. The circuit of claim 1.   The first circuit unit aligns waveform edges by minimizing a delay between the first control signal of the high-side transistor and the second control signal of the low-side synchronous rectification transistor, and thereby the dead time. The circuit of claim 1, wherein the circuit is configured to reduce as much as possible to zero.   The circuit of claim 1, wherein each edge requires a set of edge detection circuits to detect rising and falling edges of the first voltage.   When there is no overlap between the waveform edge of the first signal and the waveform edge of the first voltage, the waveform of the first signal or the first voltage is adjusted to introduce an overlap and there is an overlap The circuit of claim 1, wherein the waveform of the first signal or the first voltage is adjusted to eliminate overlap. The first circuit unit detects at least two edge detection circuits that detect waveform edges of the first signal and the first voltage;
The circuit of claim 1, further comprising at least one delay detection circuit that processes the detected waveform edge.   The circuit of claim 9, wherein the at least one delay sensing circuit is used to optimize matching of the first signal and a first voltage. The second circuit unit compares at least one processed waveform edge with at least one edge comparison circuit;
At least one presettable counter circuit having an up / down counter to adjust the waveform edge;
10. The circuit according to claim 9, further comprising a rising and falling edge range selection control circuit for adjusting rising and falling waveform edges.   12. The circuit of claim 11, wherein the up / down counter is adjusted every clock / PWM cycle.   12. The circuit of claim 11, wherein the up / down counter is pre-loadable to minimize edge adjustment.   12. The circuit of claim 11, wherein the up / down counter value is decoded to select a corresponding delay or a corresponding adjustment.   12. The circuit according to claim 11, further comprising rising and falling edge range selection circuits for preloading up / down counter values to set waveform edges.   The circuit of claim 1, wherein the first voltage is selected from a voltage at the switching node and a voltage at a gate of a high side transistor.   The circuit of claim 1, wherein the operation continues until the waveform edge of the first signal is aligned with the waveform edge of the first voltage.   The circuit of claim 1, comprising a split capacitor having two capacitors connected in series between the first contact and the second contact at the sense contact in order to sense a fast operating waveform edge.   19. The circuit of claim 18, comprising a split resistor at a sensing contact having a resistor connected in series between the first and second contacts to maintain a DC voltage value.

Images