CN220087138U - Voltage converter capable of adjusting zero-crossing reference current - Google Patents

Abstract

The utility model provides a voltage converter capable of adjusting zero-crossing reference current, which comprises a first power switch, a second power switch, a current detection circuit, a zero-crossing reference current source and an adjusting circuit. The first power switch is coupled in series with the second power switch to generate an inductor current. The current detection circuit is coupled to the second power switch to detect a current flowing through the second power switch and generate a detection current. The zero-crossing reference current source outputs a zero-crossing reference current. The adjusting circuit is coupled to the current detecting circuit and the zero-crossing reference current source to receive the detecting current and the zero-crossing reference current, and further controls the second power switch according to the detecting current and the zero-crossing reference current and adjusts the zero-crossing reference current. Thus, the voltage converter can automatically adjust zero-crossing reference current to accurately start zero-crossing protection.

Description

Voltage converter capable of adjusting zero-crossing reference current

Technical Field

The present utility model relates to zero crossing adjustment, and more particularly to a voltage converter capable of adjusting zero crossing reference current.

Background

With the advancement of technology, various integrated circuits have been developed. For example, a power switch in the voltage converter may provide inductor current to the output to power the circuitry of the back-end. However, when the inductor current is reversed, the efficiency of the voltage converter will be deteriorated.

Disclosure of Invention

Some embodiments of the utility model relate to a voltage converter with adjustable zero-crossing reference current. The voltage converter comprises a first power switch, a second power switch, a current detection circuit, a zero-crossing reference current source and an adjusting circuit. The first power switch is coupled in series with the second power switch to generate an inductor current. The current detection circuit is coupled to the second power switch to detect a current flowing through the second power switch and generate a detection current. The zero-crossing reference current source outputs a zero-crossing reference current. The adjusting circuit is coupled to the current detecting circuit and the zero-crossing reference current source to receive the detecting current and the zero-crossing reference current, and further controls the second power switch according to the detecting current and the zero-crossing reference current and adjusts the zero-crossing reference current.

In some embodiments, the adjusting circuit includes a comparator, a control circuit, and a gate signal detecting circuit. The comparator is coupled to the current detection circuit and the zero-crossing reference current source to receive the detection current and the zero-crossing reference current and generate a comparison voltage according to the detection current and the zero-crossing reference current. The control circuit is coupled to the comparator to receive the comparison voltage and generate a gate signal according to the comparison voltage, and controls the second power switch to be turned on or off. The gate signal detection circuit is coupled to the control circuit to receive the gate signal and generate a turn-off detection signal according to the gate signal. The control circuit receives the turn-off detection signal and the comparison voltage to adjust the zero-crossing reference current according to the turn-off detection signal and the comparison voltage.

In some embodiments, the first power switch is coupled between the input voltage and the switching node, and the second power switch is coupled between the switching node and ground. The current detection circuit is coupled to the switching node and the gate terminal of the second power switch to generate a detection current according to the voltage at the switching node, the voltage of the gate signal at the gate terminal, and the ground voltage at the ground terminal.

In some embodiments, the comparator includes a positive input, a negative input, and an output. The positive input terminal is coupled to the zero-crossing reference current source to receive the zero-crossing reference current. The negative input terminal is coupled to the current detection circuit to receive the detection current. The output end outputs the comparison voltage to the control circuit.

In some embodiments, the control circuit includes control logic, a pulse width modulation circuit, and a driver. The control logic circuit is coupled to the comparator to receive the comparison voltage and generate a first control signal according to the comparison voltage. The pulse width modulation circuit is coupled to the control logic circuit to receive the first control signal and generate a driving signal according to the first control signal. The driver is coupled to the pulse width modulation circuit to receive the driving signal and generate a gate signal according to the driving signal.

In some embodiments, the control circuit further includes an up-down counter. The up-down counter is coupled to the control logic circuit and the zero-crossing reference current source to receive a second control signal generated according to the comparison voltage and the turn-off detection signal from the control logic circuit and further adjust the zero-crossing reference current according to the second control signal.

In some embodiments, the comparison voltage transitions from a low logic value to a high logic value when the detected current is less than the zero crossing reference current.

In some embodiments, in response to the comparison voltage transitioning from a low logic value to a high logic value, the gate signal transitions from a high logic value to a low logic value to turn off the second power switch.

In some embodiments, the turn-off detection signal transitions from a low logic value to a high logic value in response to the gate signal transitioning from a high logic value to a low logic value.

In some embodiments, the control circuit decreases the zero crossing reference current when the comparison voltage has a low logic value in response to the switch-off detection signal transitioning from a low logic value to a high logic value. In response to the switch-off detection signal transitioning from a low logic value to a high logic value, the control circuit increases the zero-crossing reference current when the comparison voltage has a high logic value.

Drawings

The foregoing and other objects, features, advantages and embodiments of the utility model will be apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a voltage converter with zero crossing reference current adjustment according to some embodiments of the utility model;

FIG. 2 is a timing diagram illustrating a single cycle of the voltage converter of FIG. 1 according to some embodiments of the present utility model;

FIG. 3 is a timing diagram illustrating a plurality of cycles of the voltage converter of FIG. 1 according to some embodiments of the present utility model;

FIG. 4 is a flow chart of an adjustment method according to some embodiments of the utility model;

FIG. 5 is a schematic diagram of a voltage converter with zero crossing reference current adjustment according to some embodiments of the utility model; and

fig. 6 is a schematic diagram of a voltage converter with zero crossing reference current adjustment according to some embodiments of the utility model.

Detailed Description

The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Reference is made to fig. 1. Fig. 1 is a schematic diagram of a voltage converter 100 with zero-crossing reference current adjustment according to some embodiments of the utility model.

For example, in fig. 1, the voltage converter 100 includes a power switch M1, a power switch M2, a current detection circuit 120, a zero-crossing reference current source 130, and a regulation circuit 140.

The power switch M1 is coupled in series with the power switch M2, and is controlled by the control circuit 144 to generate the inductor current IL to generate the output voltage VOUT. In detail, the power switch M1 is coupled between the input voltage VIN and the switching node SN. The power switch M2 is coupled between the switching node SN and the ground GND. The voltage at the first end of the capacitor CL is the output voltage VOUT, and the second end of the capacitor CL is coupled to the ground GND.

The current detection circuit 120 is coupled to the switching node SN (also the drain terminal of the power switch M2) to detect the current flowing through the power switch M2 and generate the detection current ISEN.

For example, in fig. 1, the current detection circuit 120 includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, and an amplifier 122. The drain terminal of the transistor T1 is coupled to the switching node SN (also the drain terminal of the power switch M2). The gate terminal of the transistor T1 is coupled to the gate terminal of the power switch M2. The source terminal of the transistor T1 is coupled to the negative input terminal of the amplifier 122. The positive input of the amplifier 122 is coupled to the ground GND. The output of amplifier 122 is coupled to the gate terminal of transistor T2. The source terminal of the transistor T2 is coupled to the drain terminal of the transistor T1. The drain terminal of the transistor T2 is coupled to the drain terminal of the transistor T3. The gate terminal of the transistor T3 is coupled to the drain terminal of the transistor T3 and the gate terminal of the transistor T4. The source terminal of the transistor T3 is coupled to the source terminal of the transistor T4. The drain terminal of the transistor T4 is coupled to the negative input terminal of the comparator 142.

The amplifier 122 and the transistor T2 can lock the source terminal of the transistor T1 to the ground voltage of the ground GND. That is, the three-terminal voltage of the transistor T1 (the voltage of the switching node SN, the voltage of the gate signal LG, the ground voltage of the ground GND) is the same as the three-terminal voltage of the power switch M2 (the voltage of the switching node SN, the voltage of the gate signal LG, the ground voltage of the ground GND). Accordingly, the ratio between the current flowing through the transistor T1 and the current flowing through the power switch M2 is positively correlated with the ratio between the size of the transistor T1 and the size of the power switch M2. The "dimension" referred to herein may refer to the gate width of a transistor or switch. For example, if the ratio between the gate width of the transistor T1 and the gate width of the power switch M2 is 1:1000, the ratio between the current flowing through the transistor T1 and the current flowing through the power switch M2 is 1:1000.

Then, the detection current ISEN is generated according to the current flowing through the transistor T3 (also the current flowing through the transistor T1) by the current mirror formed by the transistors T3 and T4. For example, the detection current ISEN is equal to the current flowing through the transistor T3 (also the current flowing through the transistor T1).

It is specifically described herein that the implementation of the current detection circuit 120 in fig. 1 is only an example, and the present utility model is not limited to the implementation in fig. 1. Other suitable implementations are also within the scope of the utility model.

The zero-crossing reference current source 130 is coupled to the current detecting circuit 120 and the adjusting circuit 140. Zero-crossing reference current source 130 may output zero-crossing reference current IREF. Various implementations suitable for implementing the zero-crossing reference current source 130 are within the scope of the present utility model.

The adjusting circuit 140 is coupled to the current detecting circuit 120, the zero-crossing reference current source 130 and the power switch M2. The adjusting circuit 140 can receive the detection current ISEN and the zero-crossing reference current IREF, and further control the power switch M2 according to the detection current ISEN and the zero-crossing reference current IREF and adjust the zero-crossing reference current IREF.

For the example of fig. 1, the adjusting circuit 140 includes a comparator 142, a control circuit 144, and a gate signal detecting circuit 146.

The positive input of the comparator 142 is coupled to the zero-crossing reference current source 130 to receive the zero-crossing reference current IREF. The negative input of the comparator 142 is coupled to the current detection circuit 120 for receiving the detection current ISEN. The comparator 142 compares the zero-crossing reference current IREF and the detection current ISEN to output a comparison voltage VCOMP at its output. When the detection current ISEN is less than the zero-crossing reference current IREF, the comparison voltage VCOMP has a high logic value (e.g., logic value 1). When the detection current ISEN is greater than the zero-crossing reference current IREF, the comparison voltage VCOMP has a low logic value (e.g., logic value 0).

The control circuit 144 is coupled to the output of the comparator 142 for receiving the comparison voltage VCOMP. For the example of fig. 1, the control circuit 144 includes a control logic circuit 1442, a pulse width modulation circuit 1444, drivers 1446A,1446B, and an up-down counter 1448. The control logic 1442 provides a drive signal UGDR. The driver 1446A is coupled to the control logic 1442 for receiving the driving signal UGDR and generating the gate signal UG according to the driving signal UGDR. The gate signal UG is transmitted to the gate terminal of the power switch M1 to control the power switch M1 to be turned on or off. The control logic 1442 is further coupled to an output of the comparator 142 for receiving the comparison voltage VCOMP and generating the control signal CS1 according to the comparison voltage VCOMP. The pulse width modulation circuit 1444 is coupled to the control logic circuit 1442 for receiving the control signal CS1 and generating the driving signal LGDR according to the control signal CS1. The driver 1446B is coupled to the pwm circuit 1444 for receiving the driving signal LGDR and generating the gate signal LG according to the driving signal LGDR. The gate signal LG is transmitted to the gate terminal of the power switch M2 to control the on or off of the power switch M2.

The gate signal detecting circuit 146 is coupled to the output end of the driver 1446B (i.e. the gate end of the power switch M2) to receive the gate signal LG and generate the turn-off detecting signal LGOFF according to the gate signal LG. The control logic circuit 1442 is coupled to the gate signal detection circuit 146 to receive the turn-off detection signal LGOFF and generate the control signal CS2 according to the turn-off detection signal LGOFF and the comparison voltage VCOMP.

The up-down counter 1448 is coupled to the control logic 1442 for receiving the control signal CS2 and coupled to the zero-crossing reference current source 130 for generating the control signal CS3 according to the control signal CS2. Up-down counter 1448 transmits control signal CS3 to zero-crossing reference current source 130 to adjust zero-crossing reference current IREF.

In some embodiments, the control logic 1442, the pulse width modulation circuit 1444, the up-down counter 1448, the gate signal detection circuit 146, or other portions other than inductors or capacitors may be implemented using application specific integrated circuits (Application Specific Integrated Circuit, ASIC).

Fig. 2 is a timing diagram illustrating a period D1 of the voltage converter of fig. 1 according to some embodiments of the utility model. FIG. 3 is a timing diagram illustrating periods D1-D3 of the voltage converter of FIG. 1 according to some embodiments of the present utility model.

First, refer to fig. 1 and 2 together. The period D1 includes a time period D11 and a time period D12. In the time interval D11, the power switch M1 is turned on and the power switch M2 is turned off, so that the inductor current IL gradually increases. In the time interval D12, the power switch M1 is turned off and the power switch M2 is turned on, so that the inductor current IL gradually decreases.

For example, in fig. 2, the time interval D12 has a time point T11, a time point T12, and a time point T13 sequentially.

At the time point T11 to the time point T12, when the detected current ISEN is equal to or less than the zero-crossing reference current IREF, the inductor current IL is at the zero-crossing point IZC. In general, the closer the zero crossing IZC1 is to the zero current value, the better. This is because reverse current IL may occur when a zero crossing event occurs representing an inductor current IL. When the inductor current IL flows backward, the efficiency of the voltage converter 100 is deteriorated. Accordingly, the closer the zero crossing IZC1 is to the zero current value, the more accurately zero crossing protection can be enabled (turning off the power switch M2 to avoid reverse flow). Since the detection current ISEN is equal to or less than the zero-crossing reference current IREF, the comparison voltage VCOMP outputted by the comparator 142 is changed from a low logic value to a high logic value. In response to the comparison voltage VCOMP transitioning from a low logic value to a high logic value, the control logic 1442 outputs a control signal CS1. In response to the control signal CS1, the driving signal LGDR output by the pwm circuit 1444 changes from a high logic value to a low logic value. At this time, the inductor current IL and the detection current ISEN continuously decrease.

At time T12, the gate signal LG output by the driver 1446B transitions from a high logic value to a low logic value in response to the driving signal LGDR transitioning from a high logic value to a low logic value based on the circuit delay of the driver 1446B. Accordingly, the power switch M2 is turned off by the gate signal LG. At this time, since the inductor current IL is greater than zero and the power switch M1 of the time period D12 is turned off, the inductor current IL flows from the ground GND to the ground GND (freewheels) via the body diode BD2 and the capacitor CL of the power switch M2. However, since the inductor current IL flows through the body diode BD2 of the power switch M2, the detection current ISEN is increased and greater than the zero-crossing reference current IREF. Accordingly, the comparison voltage VCOMP outputted by the comparator 142 is changed from a high logic value to a low logic value.

At time T13, the gate signal detecting circuit 146 detects that the gate signal LG is completely changed to a low logic value (the power switch M2 is completely turned off). Accordingly, the turn-off detection signal LGOFF outputted from the gate signal detection circuit 146 is changed from a low logic value to a high logic value. When the turn-off detection signal LGOFF is at a high logic value, the control logic 1442 confirms the logic value of the comparison voltage VCOMP. At this time, the comparison voltage VCOMP is low, which indicates that the inductor current IL is flowing through the body diode BD2 of the power switch M2. Accordingly, the control logic 1442 outputs the control signal CS2 to control the up-down counter 1448 to output the control signal CS3 to decrease the zero-crossing reference current IREF, so that the zero crossing of the next cycle decreases (the zero crossing IZC of the cycle D2 is lower than the zero crossing IZC1 of the cycle D1 in fig. 3).

As shown in fig. 3, the period D2 is sequentially time point T21, time point T22, and time point T23. The operations at time T21, time T22, and time T23 are similar to those at time T11, time T12, and time T13, respectively. That is, the control logic 1442 outputs the control signal CS2 to control the up-down counter 1448 to decrease the zero-crossing reference current IREF again, so that the zero crossing of the next cycle is further decreased (the zero crossing IZC of the cycle D3 is lower than the zero crossing IZC2 of the cycle D2 in fig. 3).

Next, the period D3 has a time point T31, a time point T32, and a time point T33 in order. Similar to the time point T12 of the period D1 and the time point T22 of the period D2, the power switch M2 is turned off by the gate signal LG at the time point T32 of the period D3. At this time, since the inductor current IL is equal to zero, the detection current ISEN is smaller than the zero-crossing reference current IREF. Accordingly, the comparison voltage VCOMP outputted by the comparator 142 is maintained at a high logic value.

Similar to the time point T13 of the period D1 and the time point T23 of the period D2, the gate signal detection circuit 146 detects that the gate signal LG is completely changed to the low logic value (the power switch M2 is completely turned off) at the time point T33 of the period D3. Accordingly, the turn-off detection signal LGOFF outputted from the gate signal detection circuit 146 is changed from a low logic value to a high logic value. As described above, when the turn-off detection signal LGOFF is at a high logic value, the control logic 1442 confirms the logic value of the comparison voltage VCOMP. At this time, the comparison voltage VCOMP is at a high logic value, which indicates that the inductor current IL does not flow through the body diode BD2 of the power switch M2. Accordingly, the control logic 1442 outputs the control signal CS2 to control the up-down counter 1448 to output the control signal CS3 to further increase the zero-crossing reference current IREF, so that the zero-crossing point of the next cycle rises.

By the above operation, the subsequent zero crossing points are all close to the zero current value time point so as to accurately start zero crossing protection at the zero current value time point (turn off the power switch M2 to avoid reverse current). Accordingly, the inductor current IL is prevented from flowing backward to maintain or improve the efficiency of the voltage converter 100.

In some related art, the voltage of the switching node is detected and the voltage is correlated with the zero crossing voltage for zero crossing detection or zero crossing adjustment. In addition, these related techniques require two sets of comparators to perform the related zero crossing detection or zero crossing adjustment.

In comparison with the above related art, the present utility model utilizes the current detection circuit 120 to detect the current flowing through the power switch M2 to generate the detection current ISEN for performing the related zero crossing adjustment. Specifically, the current detection circuit 120 generates the detection current ISEN according to the same voltage as the three terminals of the power switch M2. In addition, the present utility model requires only one set of comparators 142 to perform the relevant zero crossing adjustment.

Refer to fig. 4. Fig. 4 is a flow chart of an adjustment method 400 according to some embodiments of the utility model. In some embodiments, the adjustment method 400 can be applied to the voltage converter 100 in fig. 1, the voltage converter 500 in fig. 5, or the voltage converter 600 in fig. 6, but the utility model is not limited thereto. For ease of understanding, the adjustment method 400 will be described below in conjunction with FIG. 1.

The adjustment method 400 includes operation S410, operation S420, operation S430, and operation S440.

In operation S410, the inductor current IL is generated by the power switches M1 and M2.

In operation S420, the current flowing through the power switch M2 is detected by the current detection circuit 120 and a detection current ISEN is generated.

In operation S430, a zero-crossing reference current IREF is output by the zero-crossing reference current source 130.

In operation S440, the adjusting circuit 140 controls the power switch M2 according to the detection current ISEN and the zero-crossing reference current IREF and adjusts the zero-crossing reference current IREF.

Details of the operations S410-S440 are described in the relevant paragraphs of fig. 1, and are not repeated here.

Reference is made to fig. 5. Fig. 5 is a schematic diagram of a voltage converter 500 with zero crossing reference current adjustment according to some embodiments of the utility model.

The main difference between the voltage converter 500 and the voltage converter 100 in fig. 1 is that in the voltage converter 500, the up-down counter 1448 generates the control signal CS4 (e.g., having N bits) according to the control signal CS2 and transmits the control signal CS4 back to the control logic circuit 1442. Control logic 1442 generates control signal CS5 (e.g., having N bits) according to control signal CS4 and sends control signal CS5 to zero-crossing reference current source 130 to adjust zero-crossing reference current IREF. The control signal CS5 is the same as the control signal CS4 at this time. At steady state, the least significant bit of the control signal CS4 toggles between bit 1 and bit 0. After a period of jitter, the control logic 1442 latches the control signal CS5 and latches the least significant bit of the control signal CS5 in bit 1. When the bits other than the least significant bit of the control signal CS4 change, the control logic 1442 unlatches the control signal CS5 and directly transmits the control signal CS4 as the control signal CS5 until the next steady state is entered (the least significant bit of the control signal CS4 continuously toggles between bit 1 and bit 0).

Since the rest of the voltage converter 500 is similar to the voltage converter 100, the description thereof is omitted.

Refer to fig. 6. Fig. 6 is a schematic diagram of a voltage converter 600 with zero crossing reference current adjustment according to some embodiments of the utility model.

The main difference between the voltage converter 600 and the voltage converter 500 in fig. 5 is that the voltage converter 600 further comprises a counter 650. The counter 650 is coupled to the control logic 1442. In some embodiments, the counter 650 may be an N-bit successive approximation register (successive approximation register, SAR) counter. After the system is started, the control signal CS5 is the same as the control signal CS 6. The first time zero current is triggered, the counter 650 is used to find the steady-state control signal CS6 only by N cycles (some related art needs to wait for 2N cycles before entering steady state). Control signal CS4 may then be updated to be the same as control signal CS6, and control signal CS5 latched. At this time, the least significant bit of the control signal CS4 continuously toggles between bit 1 and bit 0, and the remaining bits of the control signal CS4 are identical to the corresponding bits of the control signal CS 5. When the bits other than the least significant bit of the control signal CS4 change, the control logic 1442 unlatches the control signal CS5 and directly transmits the control signal CS4 as the control signal CS5 until the next steady state is entered (the least significant bit of the control signal CS4 continuously toggles between bit 1 and bit 0).

Since the rest of the voltage converter 600 is similar to the voltage converter 500, the description thereof is omitted.

In summary, the voltage converter of the present utility model can automatically adjust the zero-crossing reference current to accurately start zero-crossing protection (turn off the lower bridge power switch to avoid reverse current) and further avoid reverse current of the inductor.

While the utility model has been described with reference to the above embodiments, it should be understood that the utility model is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the utility model, and the scope of the utility model is accordingly defined by the appended claims.

[ symbolic description ]

100,500,600 voltage converter

120 current detection circuit

122 amplifier

130 zero-crossing reference current source

140 adjusting circuit

142 comparator(s)

144 control circuit

1442 control logic circuit

1444 pulse width modulation circuit

1446A,1446B driver

1448 up-down counter

146 gate signal detection circuit

400 adjusting method

650 counter

BD2 body diode

CL capacitance

CS1, CS2, CS3, CS4, CS5, CS6: control signal

D1, D2, D3: period

D11, D12 time interval

GND ground terminal

IL inductor current

IREF zero-crossing reference current

ISEN detecting current

IZC1, IZC, IZC3 zero crossing points

LG, UG: gate Signal

LGDR, UGDR, drive Signal

LGOFF off detection signal

M1, M2 power switch

S410, S420, S430, S440 operation

SN switching node

T1, T2, T3, T4: transistors

T11, T12, T13, T21, T22, T23, T31, T32, T33: time point VCOMP: comparison voltage

VIN input Voltage

VOUT: output voltage.

Claims (10)

1. A voltage converter for regulating zero-crossing reference current, comprising:

the first power switch and the second power switch are coupled in series to generate inductive current;

the current detection circuit is coupled with the second power switch to detect the current flowing through the second power switch and generate a detection current;

zero-crossing reference current source, output zero-crossing reference current; and

the adjusting circuit is coupled to the current detecting circuit and the zero-crossing reference current source to receive the detecting current and the zero-crossing reference current, and further to control the second power switch and adjust the zero-crossing reference current according to the detecting current and the zero-crossing reference current.

2. The voltage converter of claim 1, wherein the regulation circuit comprises:

the comparator is coupled with the current detection circuit and the zero-crossing reference current source to receive the detection current and the zero-crossing reference current and generate comparison voltage according to the detection current and the zero-crossing reference current;

the control circuit is coupled with the comparator to receive the comparison voltage and further generate a gate signal according to the comparison voltage and control the second power switch to be turned on or turned off; and

the gate signal detection circuit is coupled with the control circuit to receive the gate signal and generate a turn-off detection signal according to the gate signal, wherein the control circuit receives the turn-off detection signal and the comparison voltage to adjust the zero-crossing reference current according to the turn-off detection signal and the comparison voltage.

3. The voltage converter of claim 2, wherein the first power switch is coupled between an input voltage and a switching node, and the second power switch is coupled between the switching node and a ground, wherein the current detection circuit is coupled to the switching node and a gate terminal of the second power switch to generate the detection current according to a voltage at the switching node, a voltage of the gate signal at the gate terminal, and a ground voltage at the ground.

4. The voltage converter of claim 2, wherein the comparator comprises:

a positive input coupled to the zero-crossing reference current source for receiving the zero-crossing reference current;

the negative input end is coupled with the current detection circuit to receive the detection current; and

and an output terminal for outputting the comparison voltage to the control circuit.

5. The voltage converter of claim 2, wherein the control circuit comprises:

the control logic circuit is coupled with the comparator to receive the comparison voltage and generate a first control signal according to the comparison voltage;

the pulse width modulation circuit is coupled with the control logic circuit to receive the first control signal and further generate a driving signal according to the first control signal; and

the driver is coupled to the pulse width modulation circuit to receive the driving signal and generate the gate signal according to the driving signal.

6. The voltage converter of claim 5, wherein the control circuit further comprises:

the up-down counter is coupled to the control logic circuit and the zero-crossing reference current source to receive a second control signal generated according to the comparison voltage and the turn-off detection signal from the control logic circuit and further adjust the zero-crossing reference current according to the second control signal.

7. The voltage converter of claim 2, wherein the comparison voltage transitions from a low logic value to a high logic value when the detection current is less than the zero-crossing reference current.

8. The voltage converter of claim 7, wherein the gate signal transitions from the high logic value to the low logic value to turn off the second power switch in response to the comparison voltage transitioning from the low logic value to the high logic value.

9. The voltage converter of claim 8, wherein the turn-off detection signal transitions from the low logic value to the high logic value in response to the gate signal transitioning from the high logic value to the low logic value.

10. The voltage converter of claim 9, wherein the control circuit decreases the zero crossing reference current when the comparison voltage has the low logic value and increases the zero crossing reference current when the comparison voltage has the high logic value in response to the turn-off detection signal transitioning from the low logic value to the high logic value.