CN115833582B - Buck-boost converter, controller and control method thereof - Google Patents
Buck-boost converter, controller and control method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005070 sampling Methods 0.000 claims description 42
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000001939 inductive effect Effects 0.000 claims description 2
- 230000001276 controlling effect Effects 0.000 description 14
- 101100041125 Arabidopsis thaliana RST1 gene Proteins 0.000 description 8
- 101100443250 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG1 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000004044 response Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 4
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- 239000004065 semiconductor Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
The invention discloses a buck-boost converter, a controller thereof and a control method thereof. The controller includes: an oscillator for generating a clock signal having a plurality of pulses; an error amplifier adapted to compare the feedback signal of the output voltage with a reference voltage to generate a first error signal; a first PWM comparator for comparing a triangular wave signal related to the inductor current with a first error signal and generating a first off logic signal when the first error signal crosses the triangular wave signal; and the logic circuit judges whether a first turn-off logic signal is received before each pulse comes, if the first turn-off logic signal is detected, the step-up and step-down converter is controlled to work in a step-down mode in the current clock cycle, otherwise, the step-up and step-down converter is controlled to work in the step-up mode in the current clock cycle, so that only a pair of switching tubes can be switched in one clock cycle, the switching loss is greatly reduced, and the efficiency of the power supply is obviously improved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a buck-boost converter, a controller thereof and a control method thereof.
Background
Modern portable electronic devices are often provided with a power source, such as a battery, which serves as the Direct Current (DC) for the various electronic components within the device. However, typically these components will have different voltage requirements, and so such devices typically employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.
Existing DC/DC converters with wide input voltages include cascaded buck-boost converters, H-bridge buck-boost converters, kuke converters, SEPIC (Single Enable Primary Inductance Converter, single-ended primary inductor converters) and the like. Wherein the H-bridge buck-boost converter (single inductor or non-inverting buck-boost converter) has good performance.
The buck-boost converter operates in three different modes of operation based on the relationship between the input voltage and the output voltage. These modes include a pure buck mode, a pure boost mode, and a buck-boost switching mode. When the input voltage is higher than the output voltage, the converter works in a pure step-down mode, and the input voltage is reduced to a voltage level required by the output of the converter; when the input voltage is lower than the output voltage, the converter works in a pure boost mode to increase the input voltage to a voltage level required by output; when the input voltage approaches the output voltage, the converter operates in buck-boost conversion mode.
The main disadvantage of the prior art is that the control mode must contain a buck-boost switching section, which would otherwise cause instability of the system. In the buck-boost conversion mode, the four power switches in the converter are switched in any period, which causes switching loss (SWITCHING LOSS) and increases energy loss.
Disclosure of Invention
In view of the above, the present invention is directed to a buck-boost converter, a controller thereof and a control method thereof, in which only one pair of power switches operates in each switching cycle, so that switching loss can be greatly reduced and power efficiency can be improved.
According to a first aspect of the present invention, there is provided a controller of a buck-boost converter comprising a buck switching tube pair coupled between an input voltage and a reference ground, a boost switching tube pair coupled between an output voltage and the reference ground, and an inductor, wherein a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forms a first switching node, a common terminal of a second power switch and a second rectifying switch of the boost switching tube pair forms a second switching node, and the inductor is coupled between the first switching node and the second switching node, the controller comprising: an oscillator for generating a clock signal having a plurality of pulses, adjacent ones of the pulses defining a clock period; an error amplifier adapted to compare the feedback signal of the output voltage with a reference voltage to generate a first error signal; a first PWM comparator for comparing a triangular wave signal related to an inductor current with the first error signal and generating a first off logic signal when the first error signal crosses the triangular wave signal; and the logic circuit is used for judging whether the first turn-off logic signal is received before each pulse comes, if the first turn-off logic signal is detected, controlling the buck-boost converter to work in a buck mode in the current clock cycle, otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle.
Optionally, the logic circuit is further adapted to control a switching duty cycle of the buck switching tube pair according to the first turn-off logic signal in the buck mode.
Optionally, the controller further includes: the level conversion circuit is suitable for level-converting the first error signal to obtain a second error signal; and a second PWM comparator adapted to compare the triangular wave signal with the second error signal and generate a second turn-off logic signal when the second error signal crosses the triangular wave signal, wherein the logic circuit is adapted to control a switching duty ratio of the boost switching transistor pair according to the second turn-off logic signal in the boost mode.
Optionally, the logic circuit includes: the first logic module is provided with a first setting end, a first resetting end, a first positive output end and a first negative output end, wherein the first setting end receives the clock signal, the first resetting end receives the first turn-off logic signal, the first positive output end outputs a step-down switch driving signal for controlling the step-down switch tube pair, and the first negative output end outputs a forced emptying signal; the second logic module is provided with a second setting end, a second resetting end, a third input end and a second negative output end, wherein the second setting end receives the clock signal, the second resetting end receives the second turn-off logic signal, the third input end receives the forced emptying signal, and the second negative output end outputs a boost switch driving signal for controlling the boost switch tube pair.
Optionally, the first logic module is configured to generate an effective forced-clearing signal to force clearing of the boost mode of the second logic module if the first shutdown logic signal is detected before each pulse arrives.
Optionally, the controller further includes: and the current sampling circuit is used for obtaining a current sampling signal representing the inductance current, and the current sampling signal is used for being overlapped with a slope compensation signal to generate the triangular wave signal.
Optionally, the current sampling circuit includes: the sampling tube and the sampling resistor are used for sampling the inductance current flowing through the buck switching tube pair; and a current amplifier for obtaining the current sampling signal by generating a sensing voltage across the sampling resistor.
Optionally, the controller further includes: and a current inverting comparator for detecting whether the current flowing through the inductor crosses zero, and turning off the first rectifying switch and the second rectifying switch when the current flowing through the inductor is detected to be zero.
According to a second aspect of the present invention, there is provided a control method of a buck-boost converter including a buck switching tube pair coupled between an input voltage and a reference ground, a boost switching tube pair coupled between an output voltage and the reference ground, and an inductor, wherein a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forms a first switching node, a common terminal of a second power switch and a second rectifying switch of the boost switching tube pair forms a second switching node, and the inductor is coupled between the first switching node and the second switching node, the control method comprising: generating a clock signal having a plurality of pulses, adjacent pulses defining a clock period; comparing the feedback signal of the output voltage with a reference voltage to generate a first error signal; comparing the triangular wave signal related to the inductive current with the first error signal, and generating a first turn-off logic signal when the first error signal and the triangular wave signal intersect; and judging whether the first turn-off logic signal is received before each pulse comes, if the first turn-off logic signal is detected, controlling the buck-boost converter to work in a buck mode in the current clock cycle, otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle.
Optionally, the first turn-off logic signal is further configured to control a switching duty cycle of the buck switching transistor pair in the buck mode.
Optionally, the control method further includes: converting the first error signal level to obtain a second error signal; and comparing the triangular wave signal with the second error signal, and generating a second turn-off logic signal when the second error signal intersects the triangular wave signal, wherein the second turn-off logic signal is suitable for controlling the switching duty ratio of the boost switch tube pair in the boost mode.
Optionally, determining whether the first shutdown logic signal is received before each pulse comes, and if the first shutdown logic signal is detected, controlling the buck-boost converter to operate in the buck mode in the current clock cycle includes: generating a buck switch driving signal and a forced emptying signal for controlling the buck switch tube pair according to the clock signal and the first turn-off logic signal; and generating a boost switch driving signal for controlling the boost switch tube pair according to the clock signal, the second turn-off logic signal and the forced clearing signal, wherein if the first turn-off logic signal is detected before each pulse comes, an effective forced clearing signal is generated, and a boost mode is forced cleared.
Optionally, the control method further includes: a current sampling signal representative of the inductor current is obtained and superimposed with a slope compensation signal to produce the triangular wave signal.
Optionally, the control method further includes: detecting whether a current flowing through the inductor crosses zero; and if the zero crossing of the current flowing through the inductor is detected, the first rectifying switch and the second rectifying switch are turned off.
According to a third aspect of the present invention, there is provided a buck-boost converter comprising: a buck switching tube pair coupled between an input voltage and a reference ground, a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forming a first switching node; a boost switch tube pair coupled between the output voltage and the reference ground, wherein a common end of a second power switch and a second rectifying switch of the boost switch tube pair form a second switch node; an inductor coupled between the first switching node and the second switching node; and the controller.
In the buck-boost converter, the controller and the control method thereof, the controller controls in a buck-preferred manner in each clock cycle, and switches to the boost mode only when the buck mode condition is not satisfied. The controller judges whether a first turn-off logic signal is received before each clock pulse comes, and if the first turn-off logic signal is detected, the controller controls the buck-boost converter to work in a buck mode in the current clock period; otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle. Therefore, only one step-down switch tube pair or step-up switch tube pair needs to be switched in one clock period, the switching loss is greatly reduced, and the efficiency of the power supply is obviously improved. In addition, compared with the traditional voltage mode, the converter in the fixed frequency power supply mode has better load dynamic response, and the transient response speed of the converter can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention;
fig. 2 is an operation waveform diagram of a buck-boost converter according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of logic circuitry in a buck-boost converter according to an embodiment of the invention;
fig. 4 is a waveform diagram illustrating the operation of the logic circuit in the buck-boost converter according to the embodiment of the invention when the input voltage and the output voltage are very close.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two. In addition, the transistors present in pairs according to the invention are matched transistors, the dimensions and/or types being identical, unless otherwise specified.
In the context of the present invention, a transistor blocks current and/or does not substantially conduct current when the transistor is in an "off (off) state" or "off". Conversely, when the transistor is never in an "on (on) state" or "conducting", the transistor is able to conduct current significantly. For example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) Field Effect Transistor (FET), wherein the high voltage is provided between a first terminal (i.e., drain) and a second terminal (i.e., source) of the transistor. In some embodiments, an integrated controller circuit may be used to drive the power switch when regulating the energy provided to the load. In addition, for purposes of this disclosure, "ground" or "ground potential" in this disclosure refers to a reference voltage or potential with respect to which all other voltages or potentials of an electronic circuit or Integrated Circuit (IC) are defined or measured.
Fig. 1 is a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention. The buck-boost converter of the present embodiment includes a controller 300 and an external power circuit. Wherein the power circuit includes one or more switch and filter elements (e.g., inductors, capacitors, etc.) configured to regulate the transfer of electrical energy from the input to the output of the switching converter in response to one or more switch drive signals from the controller 300. In some embodiments, one or more switches in the power circuit are integrated with the controller 210 to form an integrated circuit chip.
As shown in fig. 1, the power circuit includes a buck switching tube pair 100 coupled between an input voltage Vin and a reference ground, a boost switching tube pair coupled between an output voltage Vout and a reference ground, and an inductor L. The buck switching transistor pair 100 includes a power switch a and a rectifying switch B, the power switch a having a first terminal coupled to an input voltage Vin, a second terminal, and a control terminal. The rectifying switch B has a first terminal coupled to the second terminal of the power switch a, a second terminal coupled to the reference ground, and a control terminal. The inductor L has a first end and a second end, the common end of the power switch a and the rectifying switch B forming a first switching node, the first end of the inductor L being coupled to the first switching node. The boost switch transistor pair 200 includes a power switch C having a first terminal, a second terminal, and a control terminal, and a rectifier switch D, the second terminal of which is connected to the reference ground. The rectifying switch D has a first terminal coupled to the first terminal of the power switch C, a second terminal coupled to the output voltage Vout, and a control terminal. The common terminal of the power switch C and the rectifying switch D forms a second switching node, to which a second terminal of the inductor L is coupled. The power switch A, the rectifier switch B and the inductor L form a step-down circuit of the step-up/down converter, and the power switch C, the rectifier switch D and the inductor L form a step-up circuit of the step-up/down converter. The switches a-D may be any controllable semiconductor switching device, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), insulated Gate Bipolar Transistors (IGBTs), etc.
It should be noted that although MOSFETs are used for the switching elements in this embodiment, any other type of suitable switching element may be used without departing from the principles of the present invention. Although the present embodiment is described with reference to a synchronous buck-boost converter, the present invention is not limited thereto, and the present invention is equally applicable to an asynchronous buck-boost converter, and those skilled in the art may use rectifier diodes instead of rectifier switches B and D in the above embodiments.
The controller 300 is used to control the switching elements a-D to be turned on and off to control the inductor L to output energy in discrete pulses. The controller 300 includes a current sampling circuit 301, an oscillator 302, a logic circuit 303, an error amplifier 304, a level conversion circuit 305, a PWM comparator 306, a PWM comparator 307, and a current inverting comparator 308.
The current sampling circuit 301 samples a current flowing through the inductor L to generate a current sampling signal. The above-described sampling may be implemented by sampling resistors, current transformers, current mirrors, or the like, and the current sampling circuit 301 may also estimate the current flowing through the inductor L and acquire a current sampling signal by sampling the current flowing through each switching element (e.g., the power switch a).
As shown in fig. 1, the current sampling circuit 301 of the present embodiment includes a sampling tube S, a sampling resistor Rs, and a current amplifier 311. The sampling resistor Rs has a first terminal and a second terminal, the first terminal of which is coupled to the first terminal of the power switch a. The sampling tube S has a first end coupled to the second end of the sampling resistor Rs, a second end coupled to the second end of the power switch a, and a control end. The current amplifier 311 has a non-inverting input coupled to the first terminal of the sampling resistor Rs, an inverting input coupled to the second terminal of the sampling resistor Rs, and an output. When the power switch a is turned on, the current amplifier 311 indirectly samples the power switch a through the sampling pipe S, the inductor current flows through the sampling resistor Rs, and a sensing voltage is generated at both ends thereof, which is approximately equal to the product of the inductor current and the sampling resistor value, and then the voltage is amplified through the current amplifier 311 to obtain a current sampling signal.
The oscillator 302 is used to provide an internal clock for switching timing of the circuit (e.g., by generating multiple narrow pulses at constant frequency, adjacent pulses defining a clock cycle), while generating a sawtooth wave, providing a PWM comparator and providing a compensation signal for the slope compensation circuit.
The logic circuit 303 is configured to implement a logic control function of the system, process logic signals of each module that controls the operation states of the switching elements a to D, and generate switching drive signals VA to VD to be supplied to the switching elements a to D. Logic circuit 303 may include a Pulse Width Modulator (PWM) circuit or any other suitable circuit capable of controlling the duty cycle of power switches a-D.
Error amplifier 304 has a non-inverting input that receives reference voltage VREF, an inverting input that receives feedback signal VFB of output voltage Vout, and an output. The error amplifier is adapted to compare said feedback signal VFB with the reference voltage VREF and to generate a first error signal Vc1 at the output. Typically, a compensation network (not shown in fig. 1) consisting of resistors and capacitors is provided between the output of the error amplifier 304 and the reference ground. Although the embodiment shown in fig. 1 employs error amplifier 304, those skilled in the art will recognize that other suitable analog or digital circuits are equally suitable as long as the error amplification function is achieved.
The level shifter circuit 305 has an input coupled to the output of the error amplifier 304 and an output. The level shift circuit 305 is configured to level shift the first error signal Vc1, thereby providing the second error signal Vc2 at the output.
The PWM comparator 306 has a non-inverting input coupled to the output of the error amplifier 304 for receiving the first error signal Vc1, an inverting input for receiving the triangular wave signal Vsum related to the inductor current, and an output. For example, the current sampling signal generated by the current sampling circuit 301 may be superimposed with the slope compensation signal provided by the oscillator 302 to generate the triangular wave signal Vsum. The PWM comparator 306 is adapted to compare the first error signal Vc1 with the triangular wave signal Vsum and generate a first off logic signal RST1 when the two intersect, the first off logic signal RST1 being used to control the switching duty cycle of the buck switching transistor pair 100 in the buck mode.
The PWM comparator 307 has a non-inverting input coupled to the output of the level shifter 305 for receiving the second error signal Vc2, an inverting input for receiving the triangular wave signal Vsum, and an output. The PWM comparator 307 is adapted to compare the second error signal Vc2 with the triangular wave signal Vsum and generate a second off logic signal RST2 when the two intersect, the second off logic signal RST2 being used to control the switching duty ratio of the boost switching transistor pair 200 in boost mode.
The current inverting comparator 308 has a non-inverting input coupled to the first terminal of the rectifying switch D, an inverting input coupled to the second terminal of the rectifying switch D, and an output coupled to the logic circuit 303. The current inverting comparator 308 is configured to detect whether the current flowing through the inductor L crosses zero and to turn off the rectifying switches B and D when the current flowing through the inductor L is detected to be zero.
In accordance with the teachings of the present embodiments, buck-boost converters may operate in and transition from a plurality of modes including, but not limited to, buck mode, boost mode, and buck-boost mode. Further, the buck-boost converter of the present embodiment is configured as a fixed frequency current mode power supply, when the cycle of each clock cycle starts, the oscillator 302 provides the logic circuit 303 with the clock signal SET with a narrow pulse at a fixed frequency, the logic circuit 303 performs logic judgment according to the received clock signal SET in combination with other signals, and controls the operation mode of the buck-boost converter, so that the buck-boost converter operates in the buck mode or the boost mode in the current clock cycle. Further, the controller of the buck-boost converter of the present embodiment controls in a buck-first manner in each clock cycle, and switches to the boost mode only when the buck mode condition is not satisfied. That is, the logic circuit 303 determines whether the first off logic signal RST1 is received before each pulse comes, and if the first off logic signal RST1 is detected, controls the buck-boost converter to operate in the buck mode in the current clock cycle; otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle. Therefore, only one step-down switch tube pair or step-up switch tube pair needs to be switched in one clock period, the switching loss is greatly reduced, and the efficiency of the power supply can be obviously improved. In addition, compared with the traditional voltage mode, the converter in the fixed frequency power supply mode has better load dynamic response, and the transient response speed of the converter can be improved.
Fig. 2 is an operation waveform diagram of the buck-boost converter according to the embodiment of the present invention. As shown in fig. 2, when the input voltage Vin is far greater than the output voltage Vout, the first error signal Vc1 intersects the triangular wave signal Vsum, and the second error signal Vc2 is obtained by translating the first error signal Vc1, so that the second error signal Vc2 does not intersect the triangular wave signal Vsum, and the converter operates in the buck mode at this time, and at the same time, the intersecting portion of the first error signal Vc1 and the triangular wave signal Vsum is used to control the switching duty ratio of the buck switching tube pair 100 in the buck mode. As the input voltage Vin gradually decreases, the first error signal Vc1 gradually increases to generate a larger duty cycle to control the buck switching transistor pair. When the input voltage Vin and the output voltage Vout are equal, the duty ratio of the buck switching tube pair reaches 100%, and at this time, the first error signal Vc1 exceeds the peak portion of the triangular wave signal Vsum, so that the first error signal Vc1 no longer intersects the triangular wave signal Vsum in a later time period, and the second error signal Vc2 intersects the triangular wave signal Vsum, and at this time, the converter operates in the boost mode, and at the same time, the intersecting portion of the second error signal Vc2 and the triangular wave signal Vsum will be used to control the duty ratio of the boost switching tube pair. As the input voltage Vin further decreases, the first error signal Vc1 and the second error signal Vc2 continue to increase, and the second error signal Vc2 generates a larger duty ratio with the triangular wave signal Vsum to control the boost mode. Thus, a buck-boost converter of a fixed frequency current mode can be obtained.
Fig. 3 is a schematic circuit diagram of a logic circuit in a buck-boost converter according to an embodiment of the invention, and fig. 4 is an operational waveform diagram of the logic circuit in the buck-boost converter according to an embodiment of the invention when the input voltage and the output voltage are very close. In the following, it is explained with reference to fig. 3 and 4 how to implement the buck-boost converter of the present embodiment, only one pair of switching tubes operates in one clock cycle when the input voltage and the output voltage are very close.
As shown in fig. 3, the logic circuit 303 of the buck-boost converter of the present embodiment includes a first logic module 331 and a second logic module 332. The first logic module 331 has a first reset terminal R1, a first SET terminal S1, a first positive output terminal Q, and a first negative output terminal QN, wherein the first reset terminal R1 receives the first off logic signal RST1, the first SET terminal S1 receives the clock signal SET, the first positive output terminal Q outputs the buck switch driving signal VA (only the driving signal of the power switch a is shown because the rectifying switch B and the power switch a are complementarily operated), and the first negative output terminal QN outputs a forced clearing signal. The second logic module 332 has a second reset terminal R2, a second SET terminal S2, a third input terminal CD and a second negative output terminal Q2N, wherein the second reset terminal R2 receives the second off logic signal RST2, the second SET terminal S2 receives the clock signal SET, the third input terminal CD is coupled to the first negative output terminal QN of the first logic module 331 to receive the forced clear signal, and the second negative output terminal Q2N is used for outputting the boost switch driving signal VC (similarly, only the driving signal of the power switch C is shown because the rectifying switch D and the power switch C are complementarily operated).
As shown in fig. 4, the clock signal SET is generated by the oscillator 303 at a constant frequency, and each pulse triggers a switching signal once, and the first logic module 331 and the second logic module 332 control the buck switching transistor to operate or the boost switching transistor to operate in the current clock cycle under the triggering of the pulse. Taking the nth pulse (N is a positive integer) as an example, before the nth pulse arrives, the first error signal Vc1 intersects the triangular wave signal Vsum, the first turn-off logic signal RST1 is turned to a high level, the first logic control module 331 generates a high-level step-down switch driving signal VA according to the high-level first turn-off logic signal RST1, and turns off the power switch a and turns on the rectifying switch B. Meanwhile, the first negative output terminal QN of the first logic module 331 outputs a low-level signal (the signals output by the first positive output terminal Q and the first negative output terminal QN are opposite), that is, an effective forced-clearing signal, and the third input terminal CD of the second logic module 332 forcibly clears the boost mode according to the effective forced-clearing signal, so that the second negative output terminal Q2N of the second logic module 332 outputs the boost switch driving signal VC with a low level. Thus, when the nth clock pulse arrives, the first positive output Q of the first logic module 331 is SET to a low level by the clock signal SET, the first negative output QN is SET to a high level, and the second negative output Q2N of the second logic module 332 remains low, so that the buck-boost converter operates in the buck mode during the clock period, i.e. the power switch a and the rectifying switch B operate complementarily, while the power switch C remains turned off and the rectifying switch D remains turned on. In the buck mode, the inductor L is charged by the voltage difference between the input voltage Vin and the output voltage Vout, because the input voltage Vin and the output voltage Vout are very close, the charging energy is very small, the output voltage Vout drops once the load energy is larger than the energy provided by the inductor, and since the first error signal vc1=a (VREF-VFB), a is the amplification factor, the first error signal Vc1 increases when the output voltage Vout drops, and the first error signal Vc1 and the triangular wave signal Vsum will not intersect when the first error signal Vc1 exceeds the peak value of the triangular wave signal Vsum. Before the n+1th pulse arrives, since the first logic module 331 does not detect the first off logic signal RST1 of the high level, the first positive output terminal Q of the first logic module 331 remains to output the low level, and the first negative output terminal QN remains to the high level (i.e., the first logic module 331 does not generate the valid forced clear signal), the boosting mode of the second logic module 332 is not forced clear. Thus, when the n+1th pulse arrives, the second negative output Q2N of the second logic module 332 is SET high by the clock signal SET, so that the buck-boost converter operates in the boost mode during the clock period, i.e. the power switch a remains on, the rectifying switch B remains off, and the power switch C and the rectifying switch D operate complementarily.
Therefore, the buck-boost converter of the embodiment only has the buck switch tube pair or the boost switch tube pair to work in one clock period, and the system only triggers once in each clock according to the balance of input and output energy, so that the times of boosting and reducing are automatically regulated, and the efficiency of a power supply system is greatly improved.
In summary, in the buck-boost converter, the controller and the control method thereof according to the present embodiment, the controller performs control in a buck-first manner in each clock cycle, and switches to the boost mode only when the buck mode condition is not satisfied. The controller judges whether a first turn-off logic signal is received before each clock pulse comes, and if the first turn-off logic signal is detected, the controller controls the buck-boost converter to work in a buck mode in the current clock period; otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle. Therefore, only one step-down switch tube pair or step-up switch tube pair needs to be switched in one clock period, the switching loss is greatly reduced, and the efficiency of the power supply is obviously improved. In addition, compared with the traditional voltage mode, the converter in the fixed frequency power supply mode has better load dynamic response, and the transient response speed of the converter can be improved.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (15)
1. A controller of a buck-boost converter including a buck switching tube pair coupled between an input voltage and a reference ground, a boost switching tube pair coupled between an output voltage and the reference ground, and an inductor, wherein a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forms a first switching node, a common terminal of a second power switch and a second rectifying switch of the boost switching tube pair forms a second switching node, and the inductor is coupled between the first switching node and the second switching node, the controller comprising:
An oscillator for generating a clock signal having a plurality of pulses, adjacent ones of the pulses defining a clock period;
An error amplifier adapted to compare the feedback signal of the output voltage with a reference voltage to generate a first error signal;
A first PWM comparator for comparing a triangular wave signal related to an inductor current with the first error signal and generating a first off logic signal when the first error signal crosses the triangular wave signal; and
And the logic circuit is used for judging whether the first turn-off logic signal is received before each pulse comes, if the first turn-off logic signal is detected, controlling the buck-boost converter to work in a buck mode in the current clock cycle, otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle.
2. The controller of claim 1, wherein the logic circuit is further adapted to control a switching duty cycle of the buck switching tube pair according to the first off logic signal in the buck mode.
3. The controller of claim 1, further comprising:
The level conversion circuit is suitable for level-converting the first error signal to obtain a second error signal; and
A second PWM comparator adapted to compare the triangular wave signal with the second error signal and generate a second off logic signal when the second error signal crosses the triangular wave signal,
The logic circuit is suitable for controlling the switching duty ratio of the boost switching tube pair according to the second turn-off logic signal in the boost mode.
4. The controller of claim 3, wherein the logic circuit comprises:
the first logic module is provided with a first setting end, a first resetting end, a first positive output end and a first negative output end, wherein the first setting end receives the clock signal, the first resetting end receives the first turn-off logic signal, the first positive output end outputs a step-down switch driving signal for controlling the step-down switch tube pair, and the first negative output end outputs a forced emptying signal; and
The second logic module is provided with a second setting end, a second resetting end, a third input end and a second negative output end, wherein the second setting end receives the clock signal, the second resetting end receives the second turn-off logic signal, the third input end receives the forced emptying signal, and the second negative output end outputs a boost switch driving signal for controlling the boost switch tube pair.
5. The controller of claim 4, wherein the first logic module is configured to generate a valid forced flush signal to force a boost mode of the second logic module to flush if the first off logic signal is detected immediately before each pulse.
6. The controller of claim 1, further comprising:
And the current sampling circuit is used for obtaining a current sampling signal representing the inductance current, and the current sampling signal is used for being overlapped with a slope compensation signal to generate the triangular wave signal.
7. The controller of claim 6, wherein the current sampling circuit comprises:
the sampling tube and the sampling resistor are used for sampling the inductance current flowing through the buck switching tube pair; and
And a current amplifier for obtaining the current sampling signal by generating a sensing voltage at both ends of the sampling resistor.
8. The controller of claim 1, further comprising:
And a current inverting comparator for detecting whether the current flowing through the inductor crosses zero, and turning off the first rectifying switch and the second rectifying switch when the current flowing through the inductor is detected to be zero.
9. A control method of a buck-boost converter including a buck switching tube pair coupled between an input voltage and a reference ground, a boost switching tube pair coupled between an output voltage and the reference ground, and an inductor, wherein a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forms a first switching node, a common terminal of a second power switch and a second rectifying switch of the boost switching tube pair forms a second switching node, and the inductor is coupled between the first switching node and the second switching node, the control method comprising:
generating a clock signal having a plurality of pulses, adjacent pulses defining a clock period;
comparing the feedback signal of the output voltage with a reference voltage to generate a first error signal;
Comparing the triangular wave signal related to the inductive current with the first error signal, and generating a first turn-off logic signal when the first error signal and the triangular wave signal intersect; and
Judging whether the first turn-off logic signal is received before each pulse comes, if the first turn-off logic signal is detected, controlling the buck-boost converter to work in a buck mode in the current clock cycle, otherwise, controlling the buck-boost converter to work in a boost mode in the current clock cycle.
10. The control method of claim 9, wherein the first off logic signal is further used to control a switching duty cycle of the buck switching tube pair in the buck mode.
11. The control method according to claim 9, further comprising:
Converting the first error signal level to obtain a second error signal; and
Comparing the triangular wave signal with the second error signal and generating a second turn-off logic signal when the second error signal crosses the triangular wave signal,
Wherein the second off logic signal is adapted to control a switching duty cycle of the boost switching transistor pair in the boost mode.
12. The control method of claim 11, wherein determining whether the first shutdown logic signal is received before each pulse arrives, and if the first shutdown logic signal is detected, controlling the buck-boost converter to operate in buck mode at a current clock cycle comprises:
Generating a buck switch driving signal and a forced emptying signal for controlling the buck switch tube pair according to the clock signal and the first turn-off logic signal;
Generating a boost switch drive signal for controlling the boost switch transistor pair according to the clock signal, the second turn-off logic signal and the forced clear signal,
And if the first turn-off logic signal is detected before each pulse comes, generating an effective forced clearing signal and forcing clearing of the boosting mode.
13. The control method according to claim 9, further comprising:
A current sampling signal representative of the inductor current is obtained and superimposed with a slope compensation signal to produce the triangular wave signal.
14. The control method according to claim 9, further comprising:
Detecting whether a current flowing through the inductor crosses zero;
And if the zero crossing of the current flowing through the inductor is detected, the first rectifying switch and the second rectifying switch are turned off.
15. A buck-boost converter comprising:
A buck switching tube pair coupled between an input voltage and a reference ground, a common terminal of a first power switch and a first rectifying switch of the buck switching tube pair forming a first switching node;
A boost switch tube pair coupled between the output voltage and the reference ground, wherein a common end of a second power switch and a second rectifying switch of the boost switch tube pair form a second switch node;
An inductor coupled between the first switching node and the second switching node; and
The controller of any one of claims 1-8.
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