JP2003319645A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent conversion efficiency from being lowered even if a load current is reduced by constituting a switching element of a plurality of MOSFETs through which an output current is passed. <P>SOLUTION: In a synchronous rectification step-down converter, a semiconductor switch QP is formed by connecting drains and sources of n transistors Qp1 to Qpn and a board in common and connecting divided gate terminals with a P-channel MOSFET gate drive circuit 1 independently. N-channel MOSFETs Qn1 to Qnn constitute a semiconductor switch QN wherein the respective gate terminals are connected with a N-channel MOSFET gate drive circuit 2 and drains and sources thereof are connected in common with a diode D for commutation. Load determining signals Vload outputted from a load determining circuit 5 switch the transistors Qp1 to Qpn and Qn1 to Qnn switches an enable state wherein the turn-on/off of each individual transistor is controlled to a disable state wherein the transistors are kept off. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC-DC converter for supplying a load with a power supply voltage converted into a predetermined DC voltage value by controlling ON / OFF of a semiconductor switch.

[0002]

2. Description of the Related Art DC-converts a DC power supply voltage into a predetermined DC voltage value by controlling ON / OFF of a semiconductor switch.
As the DC converter, a step-down converter or a step-up converter is used because of the relationship between input and output voltages.

FIG. 16 is a circuit diagram showing a structure of a conventional synchronous rectification type step-down converter. In the figure, Vin is a DC power supply voltage whose voltage value fluctuates, and C is a DC power supply voltage Vo.
A smoothing capacitor that suppresses pulsation of ut, Qa is a Pch MOSFET (metal oxide field effect transistor, hereinafter simply referred to as a transistor) as a main switching element, D is a diode for commutation (flywheel diode), and L is output current smoothing. Choke coil, Vout
Is an output voltage applied to a load (not shown).

Reference numeral 16a is a Pch MOSFET gate driving circuit, which is a P-channel MOSFET which controls the semiconductor switches by PWM.
In response to the chMOSFET drive signal, the transistor Qa
A gate signal is generated so as to control ON / OFF. Similarly, Nch MOSFET gate drive circuit 1
6b controls on / off the transistor Qb connected to the commutation diode D by a gate signal.

FIG. 17 is a diagram showing conversion efficiency in a conventional DC-DC converter. This is because in the synchronous rectification type step-down converter as shown in FIG. 16, DC power supply voltage Vin = 3.6 [V] and output voltage Vout = 2.5.
[V] and the output current Iout is 30 [m]
Various losses are calculated for the cases of A] and 300 [mA]. The inductance of the choke coil L is 1 [μH], the capacitance of the smoothing capacitor C is 4.7 [μF], and the switching frequency is 2.5 [MH].
z].

The losses shown in the respective items a to g are values determined by the parameters of the semiconductor integrated circuit constituting the DC-DC converter, and the losses in the items h and i depend on the characteristics of the choke coil. Looking at the respective loss values, in the items a to d and the item h, when the output current is small, the output current Iou is almost
It decreases in proportion to the current value of t. However, the items e to g and the item i are always constant values regardless of the current value.

That is, the output current Iout is 30 [mA].
When the output current and the output power are reduced to 1/10, the total efficiency does not fall to 1/10, and the conversion efficiency decreases as the load current decreases. Focusing on the loss items a to g determined by the parameters of the semiconductor integrated circuit, the items a to d are losses related to the output current, while the items e to g are parasitic capacitances inside the semiconductor integrated circuit. It is presumed that the reason is that the loss is determined by the input voltage.

As described above, when the conventional DC-DC converter is PWM-controlled, the conversion efficiency is low especially when the load current is small. Therefore, as a DC-DC converter for converting a DC power supply voltage into a predetermined DC voltage value, a PW
A PFM control circuit that can reduce the number of times of switching may be used as compared with the case of the M control circuit.

FIG. 18 is a block diagram showing a PFM control circuit for generating a drive signal to the DC-DC converter. In the conventional PFM control circuit, the detection circuit 181 monitors the voltage of the output signal Vout, and when the voltage of the feedback signal Vfb output from the detection circuit 181 falls below the reference voltage signal Vref, the comparison signal Vcmp of the comparison circuit 182. Becomes low level. The one-shot pulse generation circuit 183 receives the comparison signal Vcmp and generates a gate pulse signal Vpulse with a certain pulse width Tw to generate Pc.
Turn on hM0SFETQa. A reference voltage circuit 184 outputs the reference voltage signal Vref.

FIG. 19 is a timing chart showing PFM control waveforms in the PFM control circuit described above. Since the PFM control can perform the switching operation only when necessary, it is used as a converter especially when the output current is small. Since the number of times of switching can be reduced as compared with the case of the PWM control circuit, there is an advantage that the loss due to switching can be reduced and the conversion efficiency is improved.

Conventionally, this PFM control circuit is integrally incorporated with a PWM control circuit, and the converter is controlled by switching to either one of them depending on the magnitude of the output current to the load. A method has been known in which the conversion efficiency of the converter is not reduced even in a small region.

FIG. 20 is a diagram showing a configuration of a DC-DC converter under PWM / PFM switching control. Load 9
A power supply voltage Vin is supplied from a DC power supply E to the DC-DC converter 10 connected to the. The DC-DC converter 10 includes a PWM control circuit 15 and a PFM control circuit 1
6 and the reference voltage signal Vref is supplied from the terminal 17. Based on this reference voltage signal Vref, the load 9
The load determination circuit 18 determines the magnitude of the output current flowing to the PWM control circuit 15, and the result is used as a determination signal.
PFM control circuit 16 and multiplexer (MUX) 1
It is output to 9. In MUX19, depending on the judgment signal,
When the load is light, the PFM control is selected, and when the load is medium to heavy, the PWM control is selected. Control circuit 1 not used
It is also possible to stop 5 and 16 for the purpose of reducing current consumption.

[0013]

DISCLOSURE OF THE INVENTION PWM / PF described above
According to the M switching control, it is possible to prevent the conversion efficiency from decreasing by using the PFM control circuit when the load is light.

However, the PFM is used for the DC-DC converter.
In some applications, control cannot be used. For example, when it is used as a power source for an electronic circuit that uses radio waves, it is necessary to separate the bands so that the frequencies of the carrier wave and the modulated wave do not interfere with the oscillation frequency of the DC-DC converter and its harmonics. However, in the PFM mode, since the oscillation frequency changes depending on conditions such as load current and input / output voltage, the above-mentioned interference may occur, and there is a problem that PFM control cannot be used.

An object of the present invention is to provide a DC-DC converter in which a switching element for flowing an output current is composed of a plurality of MOSFETs so that the conversion efficiency does not decrease even if the load current becomes small. .

[0016]

In order to achieve the above object, there is provided a DC-DC converter for supplying a load with a power supply voltage converted into a predetermined DC voltage value by controlling ON / OFF of a semiconductor switch. To be done. This DC-
In the DC converter, a drain, a source, and a substrate of a plurality of transistors are commonly connected to each other, and a gate signal is supplied to each of the transistors forming the semiconductor switch and each of the transistors forming the semiconductor switch to supply the gate signal to the transistors. P that controls on / off independently
It is composed of a WM control means and a switching means for supplying a load determination signal to the PWM control means so as to switch between an enable state in which the transistor is turned on / off and a disable state in which the transistor is always turned off.

According to the DC-DC converter of the present invention, the number of switching elements used is changed according to the magnitude of the load current, and the number of switching elements used is reduced when the load current is small. The loss due to parasitic capacitance between the gate and the substrate, which is a major loss factor,
You can increase efficiency.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a structure of a synchronous rectification type step-down converter according to an embodiment of the present invention.

In FIG. 1, Vin is a DC power supply voltage whose voltage value fluctuates, C is a smoothing capacitor that suppresses pulsation of the DC power supply voltage Vout, D is a diode for commutation, L is a choke coil for smoothing output current, and Vout is Vout. This is the output voltage applied to the load. n PchM0SFETs Qp1 to Qpn
The semiconductor switch QP composed of 1 corresponds to the main switch element in the conventional step-down converter shown in FIG. In the semiconductor switch QP, the drains, sources, and substrates of the n transistors Qp1 to Qpn are commonly connected, and each divided gate terminal is independently Pc.
It is connected to the hM0SFET gate drive circuit 1.

Similarly, NchM0 divided into n pieces
The gate terminals of SFETs Qn1 to Qnn are NchM0SF
A semiconductor switch QN, which is connected to the ET gate drive circuit 2 and has drains and sources commonly connected to the commutation diode D, is configured. Gate drive circuits 1 and 2
From the PWM control circuit, which will be described later, respectively.
The SFET drive signal 3 and the NchM0SFET drive signal 4 are supplied. The transistors Qp1 to Qpn and Qn1 to Qnn that form these semiconductor switches are independently turned on / off by gate signals from the gate drive circuits 1 and 2.

The gate drive circuits 1 and 2 are load determination circuits 5
The load determination signal Vload for determining the load state is supplied from here. Load judgment signal Vload
Switches the transistors Qp1 to Qpn and Qn1 to Qnn between an enabled state in which they are on / off controlled and a disabled state in which they are always off. Transistors Qp1 to Qpn
Is connected to the VDD terminal 6, and the DC power supply voltage Vin whose voltage value varies is applied to the VDD terminal 6. The drains of the transistors Qp1 to Qpn are connected to the output terminal 7 via the choke coil L. The VSS terminal 8 is grounded.

In the PchM0SFET gate drive circuit 1, a gate signal for switching controlling the transistors Qp1 to Qpn is generated based on the PchMOSFET drive signal 3, but a specific number of transistors are enabled by the load determination signal Vload. To do. Nch
The M0SFET gate drive circuit 2 is also an Nch MOSFET.
A gate signal for performing switching control of the transistors Qn1 to Qnn is generated based on the drive signal 4, and only a specific number of transistors are enabled by the load determination signal Vload, and the other transistors are controlled not to operate. ing. That is, in the enabled state, the gate signal is output to the transistor to perform PWM control,
A signal is output so that the transistor is turned off in the disabled state.

In this way, the load judgment circuit 5 controls the load judgment signal Vload so as to increase the number of disabled transistors when the load current is small, and the number of transistors to which the drive signals 3 and 4 are transmitted. Reduce
The remaining transistors are kept off. Therefore, when the potential of each gate terminal is determined by the drive signals 3 and 4 and the semiconductor switch is turned on / off, D
When the load current of the C-DC converter is small, Nc
By increasing the number of disabled states in the hMOSFET gate drive circuits 1 and 2, the charge / discharge current to the gate / substrate capacitance can be reduced and the loss can be reduced. At this time, the on-resistance increases, but the load current is small, so
The loss that increases due to the on-resistance is small. FIG. 2 is a circuit diagram showing the configuration of another step-down converter. In FIG. 2, Vin is a DC power supply voltage whose voltage value fluctuates, C is a smoothing capacitor that suppresses the pulsation of the DC power supply voltage Vout, and QP
Is a plurality of Pch MOSFETs that form the main switching element
Is a semiconductor switch, D is a diode for commutation (flywheel diode), L is a choke coil for smoothing output current, and Vout is an output voltage applied to a load.

Although only one transistor (PchMOSFET) is shown as the semiconductor switch QP in FIG. 2, it is composed of a plurality of transistors as in FIG. In addition, the PchMOSFET gate drive circuit 1 receives a drive signal for PWM control of the PchMOSFET and generates a plurality of gate signals for ON / OFF controlling each transistor of the semiconductor switch QP.

FIG. 3 is a circuit diagram showing the structure of the boost converter. This step-up converter differs from the step-down converter of FIG. 2 in that a diode D is used instead of the semiconductor switch QP, and a plurality of Nc is used instead of the diode D for commutation.
The point is that a semiconductor switch QN composed of hMOSFETs is used. A plurality of gate signals for controlling ON / OFF of the semiconductor switch QN are generated by the Nch MOSFET gate drive circuit 2 as in the case of FIG.

Further, there is widely known a synchronous rectification type boost converter in which the diode D in the circuit shown in FIG. 3 is replaced with a transistor and the transistor is turned on only during a period when a forward current of the diode flows. .

FIG. 4 is a circuit diagram showing the structure of a synchronous rectification type boost converter. In the boost converter of FIG. 4, a semiconductor switch QP including a plurality of Pch MOSFETs is connected to the diode D, and the semiconductor switch QP is on / off controlled by a gate signal from the gate drive circuit 1.

As the diode D in FIGS. 1 and 4, substrate diodes of the semiconductor switches QN and QP can be used, respectively. In addition, an external Schottky diode may be used in order to reduce the forward voltage to reduce the loss.

In such a DC-DC converter, the relationship between the output voltage and the input voltage is determined by the on / off time of the transistor. For example, in a step-down converter, the ratio of input / output voltage Vout / Vin is the on time of the transistor
If n and the off time are Toff, the relationship shown in the equation (1) is established.

Vout / Vin = Ton / (Ton + Toff) (1) Therefore, when the ratio (duty) of the on period of the transistor is Duty, the ratio Vout / Vin of the input / output voltage is expressed by the equation (2).

Vout / Vin = Duty (2) On the other hand, in the boost converter, the relationship between the input and output voltages can be expressed by the following equation (3).

Vout / Vin = (Ton + Toff) / Toff = 1 / (1-Duty) (3) FIG. 5 is a block diagram showing a PWM control circuit for generating a drive signal to the DC-DC converter. . The DC-DC converter 10 in the figure corresponds to any of the converters shown in FIGS. DC connected to load 9
The DC converter 10 has a power supply voltage V from the DC power supply E.
in is supplied.

A PWM control circuit 15 includes a detection circuit 51, an error amplification circuit 52, a comparison circuit 53, a reference voltage circuit 54, and a triangular wave oscillation circuit 55. DC-D
The output voltage Vout of the C converter 10 is converted into a feedback signal Vfb having an appropriate value by the detection circuit 51 and input to the error amplification circuit 52. The error amplification circuit 52 is supplied with the reference voltage signal Vref from the reference voltage circuit 54, and outputs the error amplification signal Verr to the comparison circuit 53. The triangular wave oscillation circuit 55 supplies the triangular wave signal Vtri to the comparison circuit 53, and the comparison circuit 53 outputs the PWM signal Vpwm to the DC-DC converter 10 based on the reference voltage signal Vref.

Here, the reference voltage signal Vref used to determine the output voltage Vout is given from the reference voltage circuit 54 integrated inside the PWM control circuit 15, but from the outside of the PWM control circuit 15. The given signal may be used as the reference voltage signal Vref. The value of the reference voltage signal Vref may be fixed or may change.

FIG. 6 is a circuit diagram showing a specific structure of the detection circuit in the PWM control circuit of FIG. The DC-DC converter 10 is connected to the input terminal 510 of the detection circuit 51.
Output voltage Vout of the resistor Rb connected in series,
The voltage is divided by Rc and output from the output terminal 511 as a feedback signal Vfb.

FIG. 7 is a circuit diagram showing a specific structure of the error amplifier circuit in the PWM control circuit of FIG. The error amplification circuit 52 includes an operational amplifier 520 and a feedback resistor R.
The operational amplifier 520 is composed of a and a capacitor Ca, and the operational amplifier 520 integrates a value obtained by integrating the difference between the reference voltage signal Vref applied to the negative input terminal 521 and the feedback signal Vfb input to the positive input terminal 522. It has a function of outputting as the error amplified signal Verr.

Next, the control operation of the DC-DC converter will be described. FIG. 8 shows P in the PWM control circuit of FIG.
It is a timing diagram which shows a WM control waveform. The error amplification signal Verr of the error amplification circuit 52 is compared with the triangular wave signal Vtri by the comparison circuit 53. The triangular wave signal Vtri constantly oscillates with a constant cycle, a minimum voltage value, and a maximum voltage value.

FIG. 8A shows that when the output voltage Vout smaller than half the input voltage Vin is output, the low level period of the PWM signal Vpwm output from the comparison circuit 53 becomes shorter than the high level period. ing. Further, even when the feedback signal Vfb obtained from the output terminal 511 of the detection circuit 51 is higher than the reference voltage signal Vref, the error amplification signal Verr from the error amplification circuit 52 decreases with time, so that the PWM signal Vpwm has a low level period. Becomes even shorter. FIG. 8B shows an example opposite to the above case.

The PWM signal Vpw thus formed
m is PchM0S for the step-down converter shown in FIG.
It is supplied as a drive signal to the FET gate drive circuit 1 to drive the PchM0SFETQP as a switching element. Pch MOSFET gate drive circuit 1 in this case
Usually has a function of increasing the buffering capability for the gate signal and converting the voltage level of the gate signal as necessary. The drive signal (PWM signal Vpwm) input to the gate signal and the output gate signal are almost the same. Timing and polarity. Therefore, as shown in FIG. 8B, the output voltage V
Even when out is higher than the target value and the error amplification signal Verr becomes large, the feedback signal Vfb and the reference voltage signal Vre are shortened by shortening the ON time of the PchM0SFETQP.
To reduce the output voltage Vout until f becomes equal,
The feedback operation by the PWM signal Vpwm works.

Although the generally known PWM control has been described above, in such PWM control, FIG.
In addition to the step-down converter shown in FIG. 3, the step-up converter shown in FIG. 3 and the synchronous rectification type shown in FIGS. 1 and 4 similarly perform the feedback operation by the PWM signal Vpwm.

When converting a DC power supply voltage into an output voltage of a predetermined DC voltage value in a synchronous rectification type step-up converter or step-down converter, two switching elements are required, and therefore a gate signal is generated for each of them. There must be. For example, in a synchronous rectification type step-down converter (FIG. 1), two pairs of transistors Qp1 to Qpn and Qn1 to Qnn are used.
If both are turned on at the same time, the input side is short-circuited, and in the case of the boost converter (FIG. 4), the output side is short-circuited. Therefore, in the synchronous rectification type PWM control circuit, it is necessary to generate two gate signals so that the switching elements are not turned on at the same time.

FIG. 9 is a block diagram showing a PWM control circuit for generating a drive signal for the synchronous rectification type converter. The blocks corresponding to the PWM control circuit 15 in FIG. 5 are given the same reference numerals. In the dead time generation circuit 90, the PchM0SFET drive signal and the NchM0SFE are driven based on the PWM signal Vpwm which is the output of the comparison circuit 53.
And a T drive signal is generated. The dead time generation circuit 90 is a synchronous rectification type step-down converter (FIG. 1).
Through the gate drive circuits 1 and 2 of the transistors Qp1 to Qp
It is connected to the gate terminals of pn and Qn1 to Qnn.

FIG. 10 is a circuit diagram showing a specific structure of the dead time generation circuit, and FIG. 11 is a timing chart of the PWM control waveform having the dead time. P
The input terminal 91 to which the WM signal Vpwm is supplied is connected to the inverter INV1, the inverter INV1 is connected to the inverter INV2 via the resistor Rd, and one end of the resistor Rd is grounded via the capacitor Cd. Further, the inverter INV2 is connected to the output terminal 92 via the OR gate ORa, and the AND gate AND
It is connected to the output terminal 93 via a.

Here, the PWM signal Vpwm has a delay time Td due to the resistor Rd and the capacitor Cd between the inverter INV1 and the inverter INV2, but other delays can be ignored. As shown in FIG.
When the WM signal Vpwm is input, the PchM0SFET drive signal output from the output terminal 92 has a low level period shorter by Td than the input signal, and the NchM0SFET drive signal from the output terminal 93 has a high level period from the input signal. It is shortened by Td. This delay time Td
Thus, in the case of the synchronous rectification type step-down converter (FIG. 1), the gate signals having the dead time are output from the gate driving circuits 1 and 2, respectively, and both transistors Qp1 to Qpn and Qn1 to Qnn are turned on at the same time. PWM control is performed so as not to do so.

FIG. 12 is a circuit diagram showing a specific configuration of the load determination circuit 5. In the example shown in FIG. 12A, the detection resistor Re is connected in series with the choke coil L, and the potential difference across the detection resistor Re generated when the output current Iout flows therethrough is used. That is, the potential difference between both ends of the detection resistor Re is (K2 / K1) by the operational amplifier 151, the resistors Rf and Rg (both have resistance values K1), and the resistors Rh and Ri (both have resistance values K2). ) It is output from the operational amplifier 151 as a signal of the multiplied potential.
Since the output current Iout flowing through the detection resistor Re contains an oscillating component, a low-pass filter composed of the resistor Rj and the capacitor C2 is connected to the output side of the operational amplifier 151, and the smoothed average value is taken out. .

In this way, the load signal S having a voltage value proportional to the average value of the output current Iout can be taken out from the output terminal 153. The load signal S is further given to the plus input terminal of the comparator 152. A reference voltage signal Vref1 of an arbitrary level is applied to the minus input terminal of the comparator 152, the reference voltage signal Vref1 is compared with the load signal S, and the load determination signal Vload is output from the output terminal 154. This load determination signal Vload
If the load signal S is lower than the reference voltage signal Vref1, D
The load 9 connected to the C-DC converter 10 is a light load,
If it is high, it is treated as medium or heavy load.

The load determination circuit shown in FIG.
A circuit portion corresponding to the error amplification circuit 52 shown in FIG. That is, the error amplified signal Verr of the operational amplifier 520 is set to the reference voltage signal Vr.
Output terminal 156 by comparing with ef1 and comparator 155
Outputs a load determination signal Vload.

By the way, in the above DC-DC converter 10, the conversion efficiency is one of the important characteristics. Now, assuming that the total loss generated at the time of voltage conversion in the DC-DC converter 10 is Ptotal, the input current is Iin, and the output current is Iout, the conversion efficiency is represented by the following formula (4).

(Vout * Iout) / (Vin * Iin) = (Vout * Iout) / (Ptotal + Vout * Iout) (4) (Second Embodiment) FIG. 13 shows a step-down converter Pc.
It is a circuit diagram which shows the specific structure of the gate drive circuit for driving hM0SFET.

The PchM0SFET gate drive circuit 1 is
OR gates OR1 to ORn-1, buffer gate BUF
N by comparators CMP1 to CMPn-1 for controlling the OR gates OR1 to ORn-1 and resistors R0 to Rn-1.
-1 reference voltage to comparators CMP1 to CMPn-1
It consists of a resistor ladder that feeds the positive input terminal of the. This Pch MOSFET gate drive circuit 1 is
Output terminals 101, 102, 103 ... 104, 1 connected to the gate terminals of n PchM0SFETs Qp1 to Qpn
05, a drive signal input terminal 11 to which the PchM0SFET drive signal 3 is supplied, a power supply terminal 12 to which the power supply voltage VDD is applied, and a control terminal 13 to which the load determination signal Vload is supplied.

From the resistance ladder, each comparator CMP1 to
The potentials set in CMPn-1 are Vp1, Vp2 to Vp, respectively.
Given n-1, the following relationships exist between these potentials. Vp1>Vp2>...> Vpn-1 (5) Here, it is possible to stabilize the output signal by providing each of the comparators CMP1 to CMPn-1 with a predetermined hysteresis function.

Next, the operation of the gate drive circuit shown in FIG. 13 will be described. As described above, as the output current Iout from the load determination circuit 5 increases, the control terminal 13
The potential of the load determination signal Vload supplied to the circuit rises. Now, when the potential of the load determination signal Vload is Vp2>Vload> Vp3, the comparators CMP1 and CMP2 of the PchM0SFET gate drive circuit 1 output a high level and the comparators CMP3 to CMPn-1 output a low level.

As a result, the output terminals 101 and 102 of the PchM0SFET gate drive circuit 1 are OR gate OR.
It is fixed at a high level by 1 and OR2, but at the other output terminals 103 to 105, PchM0SFET
A switching signal according to the drive signal 3 is output as a gate signal.

In the step-down converter of FIG. 2, the gate signal output from the gate drive circuit 1 causes n PchMs.
Of the 0SFETs Qp1 to Qpn, Qp1 and Qp2 remain off, and only the remaining (n-2) transistors Qp3 to Qpn perform normal on / off operation. Therefore, it is possible to reduce the ratio of MOSFETs that perform switching operation at a light load, reduce the charge / discharge loss in the gate capacitance, and improve the conversion efficiency of the converter. (Third Embodiment) FIG. 14 is a block diagram showing an example of an NchM0SFET gate drive circuit.

The NchM0SFET gate drive circuit 2 is
n-1 AND gates AND1 to ANDn-1 and a buffer gate BUF, comparators CMP1 to CMPn-1 which control the AND gates AND1 to ANDn-1, and a resistor R0
~ Rn-1 allows comparator CM for n-1 reference voltage
It is composed of a resistance ladder which is applied to the negative input terminals of P1 to CMPn-1. This NchM0SFET gate drive circuit 2 includes n NchM0SFETs Qn1 to Qnn.
Output terminals 201, 202, 2 connected to the gate terminals of the
03 ... 204, 205, Nch M0SFET drive signal 4
Input terminal 21, to which the power supply voltage VDD is applied, and a control terminal 2 to which the load determination signal Vload is input
Equipped with 3.

The potentials given to the comparators CMP1 to CMPn-1 from the resistance ladder are Vn1 and Vn2, respectively.
.About.Vnn-1, the following relationships exist between them. Vn1>Vn2>...> Vnn-1 (6) Here, the output signal can be stabilized by providing each of the comparators CMP1 to CMPn-1 with a predetermined hysteresis function. Further, similarly to the case described in the second embodiment, in the step-up converter of FIG. 3, the gate signal output from the gate drive circuit 2 causes Qn1 and Qn2 of the n Nch M0SFETs Qn1 to Qnn to remain off. , The remaining (n-2) transistors Q
Only n3 to Qnn will perform normal on / off operation. Therefore, MO that performs switching operation at light load
By reducing the ratio of SFETs, the charge / discharge loss in the gate capacitance can be reduced, and the conversion efficiency of the converter can be increased. (Fourth Embodiment) FIG. 15 is a circuit diagram showing a specific configuration of a gate drive circuit for a Pch / Nch M0SFET in a synchronous rectification type step-down converter. Here, P
n-1 OR gates OR1 to OR1, which independently control on / off of the chMOSFET and the NchMOSFET, respectively.
A resistance ladder and a plurality of comparators CMP1 to CMP for ORn-1 and AND gates AND1 to ANDn-1
MPn-1 is provided in common. Further, these comparators CMP1 to CMPn-1 also have a hysteresis function for stabilizing the output signal.

The operation of the gate drive circuit shown in FIG. 15 will be described. As described with reference to FIG. 12, it is assumed that the load determination signal S1 supplied from the load determination circuit 5 has its potential increased as the output current Iout increases. Now, when the potential of the load determination signal Vload is Vn2>Vload> Vn3, the comparators CMP1 and CMP2 of the PchM0SFET gate drive circuit 1 output a high level and the comparators CMP3 to CMPn-1 output a low level. On the other hand, low levels are output from the comparators CMP1 and CMP2 of the NchM0SFET gate drive circuit 2, and high level signals are output from the comparators CMP3 to CMPn-1.

As a result, the output terminals 101 and 102 of the PchM0SFET gate drive circuit 1 are OR gate OR.
It is fixed at a high level by 1 and OR2, but at the other output terminals 103 to 105, PchM0SFET
A switching signal according to the drive signal 3 is output as a gate signal. On the other hand, the output terminals 201 and 202 of the NchM0SFET gate drive circuit 2 are AND gate AND
1, and it is fixed at a low level by AND2, but at the other output terminals 103 to 105, NchM0SFE
A switching signal corresponding to the T drive signal 4 is output as a gate signal.

The synchronous rectification type step-down converter of FIG.
Due to the gate signal output from the chMOSFET gate drive circuit 1, of the n Pch M0SFETs Qp1 to Qpn, Qp1 and Qp2 are kept in the off state, and the remaining (n-2)
Only the transistors Qp3 to Qpn perform normal on / off operation. Similarly, by the gate signal output from the gate drive circuit 2, n Nch M0SFETs Qn1 to Qnn are output.
Of these, Qn1 and Qn2 remain off, and the remaining (n-
2) Only the transistors Qn3 to Qnn perform normal on / off operation.

In this way, the number of transistors actually switched by the drive signals 3 and 4 is changed according to the voltage level of the load determination signal Vload, so that the synchronization shown in FIG. 1 or FIG. When applied to a rectification type step-down converter, it is possible to reduce the ratio of MOSFETs that perform switching operation at light load, reduce charge / discharge loss in gate capacitance, and improve conversion efficiency of the converter.

Next, the extent to which the conversion efficiency of the conventional converter can be increased in the present invention will be described. Now, consider a case where the ratio of MOSFETs that perform switching operation at a light load is reduced to a quarter. At this time, Vin = 3.6 [V], Vout =
Assuming that the output current Iout is 30 [mA] at 2.5 [V], the ON resistance loss of the PchM0SFET (see FIG. 17).
For item a) shown in (1), since the on-resistance is quadrupled, it increases from 1 [mW] to 4 [mW]. However, Pc
The gate capacitance loss (item e) of hM0SFET is 20
It is reduced from [mW] to 5 [mW].

Similarly, since the on-resistance of the NchM0SFET is quadrupled, its on-resistance loss (item c) is 1 [m
W] to 4 [mW]. However, the gate capacitance loss (item g) is reduced from 10 [mW] to 2.5 [mW]. As a result, considering the total loss (item j),
By subtracting, the loss can be reduced by 16.5 [mW], and the efficiency (item l) is increased by about 10% to 68.7%.

In the above, the case where the ratio of the transistors that perform the switching operation at a light load is reduced to 1/4 has been described. However, the loss power due to the charge / discharge current to the gate capacitance of the semiconductor switch and the loss due to the on resistance of the semiconductor switch are described. PchM0S so that the ratio to power is equal to 1.
By changing the size of the FET and the NchM0SFET, the total loss power (total loss) can be minimized. Therefore, by estimating each loss at each current value in advance and deciding how to set the ratio of transistors that perform switching operation at light load, higher conversion efficiency can be achieved.

Although the effect of the present invention has been described above for the synchronous rectification type converter, even a converter of a type that does not use synchronous rectification has the effect of similarly achieving high conversion efficiency.

[0065]

As described above, the DC of the present invention
According to the -DC converter, by reducing the proportion of MOSFETs that switch at a light load, there is an effect of reducing charge / discharge loss to the gate capacitance and increasing conversion efficiency.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a synchronous rectification type step-down converter according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the configuration of another step-down converter.

FIG. 3 is a circuit diagram showing a configuration of a boost converter.

FIG. 4 is a circuit diagram showing a configuration of a synchronous rectification type boost converter.

FIG. 5 is a block diagram showing a PWM control circuit for generating a drive signal for a DC-DC converter.

6 is a circuit diagram showing a specific configuration of a detection circuit in the PWM control circuit of FIG.

7 is a circuit diagram showing a specific configuration of an error amplification circuit in the PWM control circuit of FIG.

8 is a timing diagram showing PWM control waveforms in the PWM control circuit of FIG.

FIG. 9 is a block diagram showing a PWM control circuit that generates a drive signal for a synchronous rectification converter.

10 is a circuit diagram showing a specific configuration of a dead time generation circuit in the PWM control circuit of FIG.

11 is a timing diagram showing a PWM control waveform having a dead time in the PWM control circuit of FIG.

FIG. 12 is a circuit diagram showing a specific configuration of a load determination circuit.

FIG. 13 is a circuit diagram showing a specific configuration of a gate drive circuit for driving a PchM0SFET of a step-down converter.

FIG. 14 is a circuit diagram showing a specific configuration of a gate drive circuit for driving NchM0SFET of the boost converter.

15 is a circuit diagram showing a specific configuration of a gate drive circuit of Pch / Nch M0SFET in the synchronous rectification type step-down converter of FIG.

FIG. 16 is a circuit diagram showing a configuration of a conventional step-down converter.

FIG. 17 is a diagram showing conversion efficiency in a conventional DC-DC converter.

FIG. 18 is a block diagram showing a PFM control circuit for generating a drive signal for a DC-DC converter.

19 is a timing diagram showing PFM control waveforms in the PFM control circuit of FIG.

FIG. 20: DC-D by PWM / PFM switching control
It is a figure which shows the structure of a C converter.

[Explanation of symbols]

1 PchM0SFET gate drive circuit 2 Nch M0SFET gate drive circuit 3 PchM0SFET drive signal 4 Nch M0SFET drive signal 5 Load judgment circuit L choke coil C smoothing capacitor 6 VDD terminal 7 output terminals 8 VSS terminal 9 load 10 DC-DC converter 11 Drive signal input terminal 12 Resistance ladder power supply terminal 13 Control terminal Vload load judgment signal D diode OR1 to ORn-1 OR gate BUF buffer gate CMP1 to CMPn-1 comparator AND1-ANDn-1 AND gate INV1, INV2 inverter 51 detection circuit 52 Error amplification circuit 53 Comparison circuit 54 Reference voltage circuit 55 Triangle wave oscillator 90 Dead time generation circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H006 CA02 CA07 CA12 CA13 CB03                       CB07 CB09 CC02 DA04                 5H730 AA14 AA16 AS01 AS04 AS05                       BB13 BB14 BB57 BB98 DD04                       DD12 DD13 DD17 DD26 DD32                       EE07 EE08 EE10 EE13 EE60                       FD01 FF02 FG05 FG07 FG22                       XX05 XX36

Claims (8)

[Claims] 1. In a DC-DC converter for supplying a load with a power supply voltage converted into a predetermined DC voltage value by controlling ON / OFF of a semiconductor switch, a drain, a source, and a substrate of a plurality of transistors are common. And a PWM control unit that supplies a gate signal to each of the transistors that form the semiconductor switch and that controls the transistors independently to turn on and off, and A DC-DC converter, comprising: switching means for switching between an enable state for ON / OFF controlling the transistor and a disable state for always turning off the transistor by supplying a load determination signal to the means. 2. The switching means is in the disabled state so that the ratio of the power loss due to the charge / discharge current to the gate capacitance of the semiconductor switch and the power loss due to the ON resistance of the semiconductor switch approaches 1 The DC-D according to claim 1, wherein the number of transistors is controlled.
C converter. 3. The semiconductor switch comprises a plurality of P-channel type metal oxide field effect transistors (PchMO).
2. The DC-DC converter according to claim 1, wherein the DC-DC converter is configured by an SFET and supplies a power supply voltage reduced to a predetermined DC voltage value to a load. 4. The semiconductor switch comprises a plurality of N-channel type metal oxide field effect transistors (NchMOSFETs), and supplies a power supply voltage boosted to a predetermined DC voltage value to a load. The DC-DC converter according to claim 1. 5. The semiconductor switch comprises a plurality of Pch MOSFETs and a plurality of NchMOSFs.
The DC-DC converter according to claim 1, wherein the DC-DC converter is configured as a synchronous rectification transistor by ET. 6. The switching means includes a resistance ladder connected in series between a power supply and a ground, and a plurality of potentials generated by the resistance ladder are connected to one input terminal, respectively, and are connected in series to a choke coil. A plurality of comparators that convert the potential difference generated across the connected resistors to the ground potential and the integrated voltage is connected to the other input terminal, and control the gate signal of each transistor by the output signals of the plurality of comparators. The DC-DC converter according to claim 1, further comprising: a gate circuit that determines an enable / disable state. 7. The switching means is configured such that a resistance ladder connected in series between a power supply and a ground, and a plurality of potentials generated by the resistance ladder are respectively connected to one input terminal and are supplied to the load. A feedback voltage proportional to the output voltage, and a plurality of comparators connected to the other input terminal of a voltage obtained by integrating the difference between the reference voltage used to determine the output voltage, and the output signals of the plurality of comparators. The DC-DC converter according to claim 1, further comprising: a gate circuit that controls a gate signal of each transistor to determine an enable / disable state. 8. A resistance ladder forming the switching means,
8. The DC-DC according to claim 6 or 7, wherein the plurality of comparators are provided in common with PWM control means for independently controlling ON / OFF of the Pch MOSFET and the Nch MOSFET. converter.