JP2014187740A - Switching power supply circuit, electronic device, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply circuit which makes pulse widths of a maximum pulse signal and a minimum pulse signal occupying a frequency of a PWM signal independently of the frequency of the PWM signal.SOLUTION: A switching power supply circuit 1 comprises: transistors 16 and 17 generating a switching voltage; a coil 18 and a capacitor 19 generating a power supply voltage VBAT from the switching voltage; a comparator 9 generating a PWM signal from a feedback voltage VFB and a triangular wave Vcap; an oscillator 12 generating the triangular wave, a maximum pulse signal, and a minimum pulse signal; and an output stage control logic unit 6 generating a drive signal for driving the transistors 16 and 17. The oscillator 12 increases/decreases a pulse width of the maximum pulse signal and the minimum pulse signal in accordance with a frequency of the triangular wave. The control unit outputs the PWM signal as the drive signal in a normal operation, and outputs the maximum pulse signal in a heavy load operation and outputs the minimum pulse signal in a light load operation, as the drive signal.

Description

  The present invention relates to a switching power supply circuit, an electronic device, and a semiconductor integrated circuit device, and is a technique applicable to, for example, a semiconductor integrated circuit device or system having a switching power supply circuit.

  A battery having a secondary battery such as a lithium ion battery and a semiconductor integrated circuit device that controls the secondary battery to be optimally charged / discharged in an electronic device such as a notebook personal computer, a mobile phone, or a digital camera Packs are widely used.

  Further, the electronic device is provided with a power supply circuit that supplies a power supply voltage for charging to the battery pack. As the power supply circuit, for example, a switching power supply circuit such as a switching regulator is widely used. The switching power supply circuit converts a power supply voltage that is externally input by the switching operation of the transistor, that is, a switching power supply voltage into a pulse signal, outputs the pulse signal, and supplies the pulse voltage as a charging power supply voltage.

  This type of switching power supply circuit uses a pulse control technique including a logic circuit that generates a drive signal for driving a switching transistor based on a control pulse signal such as a maximum pulse signal or a minimum pulse signal input from a pulse generator. There is something that has been.

  The maximum pulse signal prevents the overcurrent from flowing because the switching transistor is always turned on in heavy loads that require a large current. The minimum pulse signal is used in light loads where almost no current flows. In order to prevent malfunction of the logic circuit, the maximum pulse signal and the minimum pulse signal are both configured to turn off the switching transistor at a substantially constant interval.

  The minimum pulse signal and the maximum pulse signal in the switching power supply circuit described above generate a substantially constant pulse width using, for example, a C (capacitance) R (resistance) circuit. For this reason, the pulse widths of the minimum pulse signal and the maximum pulse signal are fixed values.

  Some switching power supply circuits can change the switching frequency of a transistor in order to supply an optimum charging current according to a load to be connected. However, as described above, since the control pulse signal is generated with a substantially constant pulse width by a CR circuit or the like, the ratio of the pulse width is changed by changing the switching frequency.

  For example, when the switching frequency is 1 MHz and the pulse width indicates 10% of the switching frequency, the ratio becomes 20% when the switching frequency becomes 2 MHz even with the same pulse width.

  In particular, in the switching power supply circuit, if the ratio of the pulse width in the maximum pulse signal (period in which the potential is high) becomes too small, the on-time of the switching transistor becomes short, and the maximum output current in the charging power supply There is a problem that the value is affected and the charging performance is lowered.

  An object of the present invention is to provide a technique capable of optimally changing the pulse width of the minimum pulse signal or the maximum pulse signal in accordance with the change of the switching frequency.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A typical switching power supply circuit according to the present invention includes a switching unit that generates a switching voltage by switching a first power supply voltage supplied from the outside, and a smoothing unit that smoothes the switching voltage generated by the switching unit. A switching circuit unit that supplies the converted second power supply voltage; and a control unit that controls a switching operation of the switching unit. The control unit generates a triangular wave, a maximum pulse signal, and a minimum pulse signal. A pulse generating unit that compares the voltage level of the second power supply voltage with the voltage displacement of the triangular wave output from the pulse generating unit and generates a PWM signal according to the comparison result; and A control signal output unit that supplies a control unit drive signal for controlling generation.

  The pulse generator has a maximum pulse width that is high for a period that is set based on the timing at which the minimum voltage level is reached from the timing at which the voltage displacement is changed to the next minimum voltage level in accordance with the triangular wave voltage displacement. A pulse signal and a minimum pulse signal set to a minimum pulse width generated at the timing of the maximum voltage level in the triangular wave voltage displacement are generated. The control signal output unit further uses the drive signal generated based on the PWM signal in the first operation state as the drive signal, and the maximum pulse signal generated by the pulse generation unit in the second operation state as the drive signal. In the operation state 3, the minimum pulse signal generated by the pulse generator is output as a drive signal.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) A stable power supply voltage can be generated.

  (2) The generation efficiency of the power supply voltage can be improved.

It is a block diagram which shows the structural example of the switching power supply circuit by embodiment of this invention. FIG. 2 is an explanatory diagram illustrating an example of a configuration of a pulse generator provided in the switching power supply circuit of FIG. 1 and a switching circuit. It is explanatory drawing which shows an example of a structure in the oscillator provided in the pulse generation part of FIG. FIG. 3 is an explanatory diagram illustrating an example of a configuration in an output stage control logic unit provided in the pulse generation unit of FIG. 2. 4 is a timing chart illustrating an example of signal timing of each unit in the oscillator of FIG. 3. 5 is a timing chart showing an example of the output stage control logic unit of FIG. 4 during normal operation. 5 is a timing chart showing an example of the output stage control logic unit of FIG. 4 during heavy load operation. 6 is a timing chart illustrating an example of the output stage control logic unit of FIG. 4 during light load operation. 6 is a timing chart illustrating an example of an output stage control logic unit in FIG. 4 when an overcurrent detection signal is input.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape of the component is substantially the case unless it is clearly specified and the case where it is clearly not apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

<Summary of invention>
The switching power supply circuit (switching power supply circuit 1) for generating a power supply voltage in the first outline of the present invention includes a switching unit (transistors 16 and 17), a smoothing unit (coil 18 and a capacitor 19), and a PWM generation unit (comparator 9). , A pulse generation unit (oscillator 12), and a control unit (output stage control logic unit 6, drivers 14 and 15).

  The switching unit generates a switching voltage by switching the switching power supply voltage (VDD2). The smoothing unit smoothes the switching voltage generated by the switching unit and supplies it as a power supply voltage.

  The PWM generation unit compares the voltage level of the power supply voltage (feedback voltage VFB) with the triangular wave (voltage Vcap) to generate a PWM signal. The pulse generation unit generates a triangular wave, a maximum pulse signal (maximum pulse signal MAXP), and a minimum pulse signal (minimum pulse signal MINP) to be output to the PWM generation unit. The control unit generates drive signals (drive signals Sdv1, Sdv2) for driving the switching unit, and controls generation of the switching voltage.

  Then, the pulse generation unit generates the pulse width of the maximum pulse signal and the pulse width of the minimum pulse signal by increasing or decreasing in accordance with the triangular wave frequency. The control unit outputs a drive signal for driving the switching unit based on the PWM signal in the first operation state (during normal operation), and the pulse generation unit in the second operation state (during heavy load operation). The maximum pulse signal generated by the (oscillator 12) is output as a drive signal for driving the switching unit. Further, the control unit outputs the minimum pulse signal generated by the pulse generation unit as a drive signal for driving the switching unit in the third operation state (during light load operation).

  The semiconductor integrated circuit device according to the second outline of the present invention includes a PWM generation unit (comparator 9), a pulse generation unit, and a control unit (output stage control logic unit 6, drivers 14 and 15).

  The PWM generation unit compares the voltage level (feedback voltage VFB) of the power supply voltage obtained by smoothing the switching voltage with a triangular wave (voltage Vcap), and generates a PWM signal. The pulse generator generates a triangular wave (voltage Vcap), a maximum pulse signal (maximum pulse signal MAXP), and a minimum pulse signal (minimum pulse signal MINP) to be output to the PWM generator. The control unit controls the generation of the switching voltage by generating drive signals (Sdv1, Sdv2) for driving the switching units (transistors 16, 17) that generate the switching voltage by switching the switching power supply voltage (VDD2).

  Further, the pulse generation unit generates the pulse width of the maximum pulse signal and the pulse width of the minimum pulse signal by increasing or decreasing in accordance with the triangular wave frequency. The control unit outputs a drive signal for driving the switching unit based on the PWM signal in the first operation state (normal operation).

  Further, in the second operation state (during heavy load operation), the control unit outputs the maximum pulse signal generated by the pulse generation unit (oscillator 12) as a drive signal for driving the switching unit, and the third operation state ( During a light load operation), the minimum pulse signal generated by the pulse generator (oscillator 12) is output as a drive signal for driving the switching unit.

  Hereinafter, the embodiment will be further described in detail.

<Configuration example of switching power supply circuit>
FIG. 1 is a block diagram showing an example of the configuration of the switching power supply circuit according to this embodiment.

  In the present embodiment, the switching power supply circuit 1 generates a power supply voltage VBAT. The power supply voltage VBAT generated by the switching power supply circuit 1 is supplied to the battery pack BP via the output terminal VOUT and the ground terminal GND (the potential of the reference potential wiring path or neutral point wiring path of the switching power supply circuit device). The battery pack BP is used as a power source for an electronic device such as a notebook personal computer or a mobile phone.

  The battery pack BP includes a battery (not shown), a battery monitoring module, and the like. The battery is composed of a battery set in which, for example, four lithium ion secondary battery cells (the maximum voltage of one cell is about 4.2 V, for example) are connected in series.

  The battery monitoring module includes a battery voltage control IC (Integral Circuit) that performs various types of monitoring such as overcharge, overdischarge, and overcurrent in the battery, battery protection, and the like, a switch, and the like. The switch is connected between the output terminal VOUT from which the power supply voltage VBAT is output from the switching power supply circuit 1 and the positive (+) side electrode of the battery. The battery voltage control IC outputs a control signal to the switch to perform operation control, and controls the battery within a predetermined voltage range.

  As shown in FIG. 1, the switching power supply circuit 1 includes a pulse generation unit 2, a switching circuit 3, and an overcurrent detection unit (power supply voltage detection unit) 4. The pulse generator 2 and the overcurrent detector 4 can be configured as a semiconductor integrated circuit device integrated on a semiconductor substrate.

  The switching circuit 3 is prepared as a semiconductor chip different from the semiconductor chip constituting the semiconductor integrated circuit device as an insulated gate type power FET suitable for high withstand voltage and large current applications. The transistors 16 and 17 of FIG. 2 which are power FETs are configured to be mounted on a printed wiring board together with discrete components such as capacitors and resistors and incorporated into an electronic device.

  Here, the switching circuit 3 is mounted on the printed wiring board by discrete components. However, the switching circuit 3 is configured as a semiconductor integrated circuit device in which power FETs, resistors, and capacitors that form the switching circuit 3 are also formed on the semiconductor substrate. It is good.

  The semiconductor integrated circuit device is supplied with a power supply voltage VDD1 as an operating power supply voltage. The power supply voltage VDD1 is about 3.0V, for example. The switching circuit 3 is supplied with a power supply voltage VDD2 input from the outside as a switching power supply voltage.

  The power supply voltage VDD2 is, for example, about 3.0V to 30V, and the power supply voltage VBAT is generated by switching the power supply voltage VDD2 by the switching circuit 3.

  The pulse generator 2 generates drive signals Sdv1 and Sdv2 to be output to the switching circuit 3, respectively. The switching circuit 3 performs a switching operation based on the drive signals Sdv1 and Sdv2 generated by the pulse generator 2, and generates a power supply voltage VBAT that is a charging power supply from a power supply voltage VDD2 that is an input voltage, thereby generating a battery pack BP. To supply.

  The overcurrent detection unit (power supply voltage detection unit) 4 detects a current flowing through the power supply voltage VBAT, and outputs an overcurrent detection signal KS when the current value becomes equal to or higher than a preset current value.

<Configuration example of pulse generator and switching circuit>
FIG. 2 is an explanatory diagram showing an example of the configuration of the pulse generator provided in the switching power supply circuit of FIG. 1 and the switching circuit.

  The pulse generation unit 2 includes a pulse generation circuit 5, an output stage control logic unit 6, and a pulse output unit 7. The pulse generation circuit 5 includes an operational amplifier 8, a comparator 9, a capacitor 10, a resistor 11, and an oscillator 12.

  The pulse output unit 7 includes drivers 14 and 15. The driver 14 amplifies the pulse signal P1 output from the output stage control logic unit 6 and outputs the amplified signal as the drive signal Sdv1. The driver 15 amplifies the pulse signal P2 output from the output stage control logic unit 6 and outputs the amplified signal as the drive signal Sdv2.

  The switching circuit 3 includes transistors 16 and 17, a coil 18, capacitors 19 and 20, and resistors 21 to 23. A current detection resistor Ri of about several tens of mΩ connected in series is connected to the output terminal VOUT. The overcurrent detection unit (power supply voltage detection unit) 4 detects a current value from the voltage drop of the current detection resistor Ri, and when it detects that the current value exceeds a preset current value, the overcurrent detection signal KS. Is output to the output stage control logic unit 6.

  The reference voltage VREF is input to the positive (+) side input portion of the operational amplifier 8, and the feedback voltage VFB is input to the negative (−) side input portion of the operational amplifier 8.

  The operational amplifier 8 compares the reference voltage VREF and the feedback voltage VFB and outputs the comparison difference to the comparator 9 as an analog voltage. One input part of the comparator 9 and one connection part of the capacitor 10 are connected to the output part of the operational amplifier 8. One connection portion of the resistor 11 is connected to the other connection portion of the capacitor 10, and a feedback voltage VFB is supplied to the other connection portion of the resistor 11.

  The other input part of the comparator 9 is connected so that a triangular wave voltage Vcap outputted from the oscillator 12, a so-called triangular wave, is inputted. The output part of the comparator 9 is connected to the input part of the output stage control logic part 6. Is connected.

  The oscillator 12 is a signal generator and generates and outputs, for example, a triangular wave voltage Vcap, a maximum pulse signal MAXP, and a minimum pulse signal MINP. The comparator 9 compares the analog voltage output from the operational amplifier 8 with the triangular wave voltage Vcap supplied from the oscillator 12 and outputs the comparison result to the output stage control logic unit 6.

  One output unit of the output stage control logic unit 6 is connected to the input unit of the driver 14, and the other output unit of the output stage control logic unit 6 is connected to the input unit of the driver 15. The output stage control logic unit 6 generates pulse signals P1 and P2 based on the output signal of the comparator 9, respectively.

  Further, the control terminal of the output stage control logic unit 6 is connected so that the overcurrent detection signal KS output from the overcurrent detection unit is input. The overcurrent detection unit (power supply voltage detection unit) 4 monitors the current value of the current supplied from the VOUT of the switching circuit, and detects an overcurrent when it is detected that a current greater than a preset current value has flowed. The signal KS is output to the output stage control logic unit 6. When the overcurrent detection signal KS is input, the output stage control logic unit 6 stops outputting the pulse signals P1 and P2. This prevents damage to electronic components constituting the switching circuit such as the coil 18 due to overcurrent flowing.

  The pulse signal P1 output from the output stage control logic unit 6 is connected to be input to the input unit of the driver 14. The pulse signal P2 output from the output stage control logic unit 6 is connected to be input to the input unit of the driver 15.

  The driver 14 amplifies the pulse signal P1 output from the output stage control logic unit 6 and outputs the amplified signal as the drive signal Sdv1. The driver 15 amplifies the pulse signal P2 output from the output stage control logic unit 6 and outputs the amplified signal as the drive signal Sdv2.

  The gate of the transistor 16 is connected to the output portion of the driver 14, and the gate of the transistor 17 is connected to the output portion of the driver 15. The transistor 16 is composed of a P-channel MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor), and the transistor 17 is composed of an N-channel MOS. The transistors 16 and 17 are configured to handle a large current with a high breakdown voltage.

  The transistor 16 performs an on / off operation based on the drive signal Sdv <b> 1 output from the driver 14. The transistor 17 performs an on / off operation based on the drive signal Sdv2 output from the driver 15.

  One end of the source / drain of the transistor 16 is connected to be supplied with the power supply voltage VDD2, and the other end of the source / drain of the transistor 16 is connected to one end of the source / drain of the transistor 17. Yes. A reference potential VSS is connected to the other end of the source / drain of the transistor 17. In the example of FIG. 2, the back gates (semiconductor substrate region side regions) of the transistors 16 and 17 are not shown, but are connected to the electrode sides that operate as sources. That is, the back gate of the transistor 16 is connected to the power supply voltage VDD2, and the back gate of the transistor 17 is connected to the reference potential VSS.

  In addition, one connection portion of a coil 18 that is an inductor is connected to a connection portion between the other end of the source / drain of the transistor 16 and one end of the source / drain of the transistor 17.

  One connection portion of the capacitor 19, one connection portion of the capacitor 20, and one connection portion of the resistor 22 are connected to the other connection portion of the coil 18. The other connection part of the coil 18 serves as an output part of the switching power supply circuit 1, and the power supply voltage VBAT is output via the output terminal VOUT.

  A reference potential VSS is connected to the other connection portion of the capacitor 19, and one connection portion of the resistor 21 is connected to the other connection portion of the capacitor 20. One connection portion of the resistor 23 is connected to the other connection portion of the resistor 22, and the reference potential VSS is connected to the other connection portion of the resistor 23.

  The voltage divided by these resistors 22 and 23 becomes the feedback voltage VFB described above. The feedback voltage VFB is input to the negative (−) side input section of the operational amplifier 8 as described above.

<Example of oscillator configuration>
FIG. 3 is an explanatory diagram showing an example of the configuration of the oscillator provided in the pulse generator of FIG.

  As shown in FIG. 3, the oscillator 12 includes a voltage divider 24, a voltage comparator 25, and a pulse signal generator 26. The voltage dividing unit 24 includes resistors R1 to R6, and the voltage comparison unit 25 includes comparators COMP1 to COMP4.

  The pulse signal generation unit 26 includes inverters Iv1 to Iv5, latch circuits LT1 to LT3, constant current circuits IR1 and IR2, transistors T1 and T2, and a capacitor Cap. The latch circuits LT1 to LT3 are composed of, for example, an SR latch (set / reset latch).

  The resistors R1 to R6 are connected in series between the power supply voltage VDD1 and the reference potential VSS, respectively. A connecting portion between the resistor R1 and the resistor R2 is connected to the positive (+) side input terminal of the comparator COMP1. That is, the voltage Vz1, which is a voltage divided by the resistance value of the resistor R1 and the combined resistance value of the resistors R2 to R6, is input to the positive (+) side input terminal of the comparator COMP1. This voltage Vz1 becomes the first threshold voltage.

  The connection part of the resistor R2 and the resistor R3 is connected to the positive (+) side input terminal of the comparator COMP2, and the connection part of the resistor R4 and the resistor R5 is connected to the positive (+) side input terminal of the comparator COMP3. Has been.

  In this case, the voltage Vz2, which is a voltage divided by the combined resistance value of the resistors R1 and R2 and the combined resistance value of the resistors R3 to R6, is input to the positive (+) side input terminal of the comparator COMP2. The voltage Vz2 becomes the second threshold voltage.

  A voltage Vz3 that is a voltage divided by the combined resistance value of the resistors R1 to R4 and the combined resistance value of the resistors R5 and R6 is input to the positive (+) side input terminal of the comparator COMP3. This voltage Vz3 is the third threshold voltage.

  A connecting portion between the resistor R5 and the resistor R6 is connected to the positive (+) side input terminal of the comparator COMP4. Therefore, the voltage Vz4 that is a voltage divided by the combined resistance value of the resistors R1 to R5 and the resistance value of the resistor R6 is input to the positive (+) side input terminal of the comparator COMP4. This voltage Vz4 is the fourth threshold voltage.

  One input terminal (S) of the latch circuit LT1 and one input terminal (S) of the latch circuit LT2 are connected to the output part of the comparator COMP1, respectively. The input part of the inverter Iv1 is connected to the output part of the comparator COMP2.

  The output part of the comparator COMP4 is connected to the input part of the inverter Iv2 and the input part of the inverter Iv3. One input terminal (S) of the latch circuit LT3 is connected to the output part of the comparator COMP3.

  The other input terminal (R) of the latch circuit LT2 is connected to the output part of the inverter Iv1. The other input terminal (R) of the latch circuit LT1 is connected to the output part of the inverter Iv2. A signal output from the output terminal (Q) of the latch circuit LT2 is the minimum pulse signal MINP.

  The other input terminal (R) of the latch circuit LT3 is connected to the output part of the inverter Iv3. The input terminal of the inverter Iv5 is connected to the output terminal (Q) of the latch circuit LT3. The signal output from the output part of the inverter Iv5 is the maximum pulse signal MAXP.

  The input terminal of the inverter Iv4 is connected to the output terminal (Q) of the latch circuit LT1. The gates of the transistors T1 and T2 are connected to the output part of the inverter Iv4. The transistor T1 is an N channel MOS (Metal Oxide Semiconductor), and the transistor T2 is a P channel MOS. In the example of FIG. 3, the back gates (semiconductor substrate region side regions) of the transistors T <b> 1 and T <b> 2 are not shown, but are connected to the electrode sides that operate as sources. That is, the back gate of the transistor T1 is connected to VDD2, and the back gate of the transistor T2 is connected to VSS.

  A power supply voltage VDD1 is connected to the input portion of the constant current circuit IR1, and one end (the electrode side operating as a source) of the source / drain of the transistor T1 is connected to the output portion of the constant current circuit IR1. One end of the source / drain of the transistor T2 (electrode side operating as a drain) and one connection portion of the capacitor Cap are connected to the other end (electrode side operating as a drain) of the transistor T1.

  The input part of the constant current circuit IR2 is connected to the other end (the electrode side operating as the source) of the source / drain of the transistor T2. A reference voltage VSS is connected to the output part of the constant current circuit IR2 and the other connection part of the capacitor Cap. These constant current circuits IR1 and IR2 are circuits for supplying a substantially constant current.

  The transistors T1 and T2 are turned on / off based on the signal output from the inverter Iv4, thereby charging and discharging the capacitor Cap to generate a triangular wave voltage Vcap.

  The capacitor Cap is a capacitor that determines the frequency of the triangular wave to be generated. As described above, the capacitor Cap is mounted on the printed wiring board by discrete components or the like, so that a capacitor having a capacity selected by the user can be mounted.

  The capacity of the mounted capacitor Cap can be selected by the user in consideration of the supply capability of the charging power supply voltage in the switching power supply circuit 1. For example, when the capacitance value of the capacitor Cap is increased, the frequency of the triangular wave is delayed, the switching frequency of the transistors 16 and 17 is decreased, and the supply capability is decreased. Further, when the capacitance value of the capacitor Cap is decreased, the frequency of the triangular wave is increased, the switching frequency of the transistors 16 and 17 is increased, and the supply capability is improved.

  The comparator COMP1 compares the voltage Vz1 with the triangular wave voltage Vcap generated at the connection portion of the transistors T1 and T2, and outputs the comparison result. The comparator COMP2 compares the voltage Vz2 with the voltage Vcap and outputs the comparison result. The comparator COMP3 compares the voltage Vz3 and the voltage Vcap and outputs the comparison result, and the comparator COMP4 compares the voltage Vz4 and the voltage Vcap and outputs the comparison result.

  The latch circuit LT1 receives the comparison result of the comparator COMP1 and the inverted signal of the comparison result of the comparator COMP4, and generates a clock signal for driving the transistors T1 and T2.

  The latch circuit LT2 receives the comparison result of the comparator COMP1 and the inverted signal of the comparison result of the comparator COMP2, and generates a minimum pulse signal MINP. The latch circuit LT3 generates a maximum pulse signal MAXP by inverting the pulse signal generated with the comparison result of the comparator COMP3 and the inverted signal of the comparison result of the comparator COMP4 as inputs by the inverter Iv5.

  Further, the triangular wave voltage Vcap output from the oscillator 12 is connected to be input to the other input section of the comparator 9 as described above. The minimum pulse signal MINP and the maximum pulse signal MAXP output from the oscillator 12 are connected to be input to the output stage control logic unit 6 respectively.

<Configuration example of output stage control logic unit>
FIG. 4 is an explanatory diagram showing an example of the configuration of the output stage control logic unit provided in the pulse generation unit of FIG.

  As shown in FIG. 4, the output stage control logic unit 6 is composed of an OR circuit OR1 and AND circuits AND1 and AND2. A signal output from the comparator 9 is connected to one input portion of the OR circuit OR1. The other input part of the OR circuit OR1 is connected so that the minimum pulse signal MINP output from the oscillator 12 is input.

  One input part of the AND circuit AND1 is connected to the output part of the OR circuit OR1, and the maximum pulse signal MAXP output from the oscillator 12 is input to the other input part of the AND circuit AND1. Connected to be.

  One input part of the AND circuit AND2 is connected to the output part of the AND circuit AND1, and the other input part of the AND circuit AND2 is the overcurrent detection output from the overcurrent detection part 4. The signal KS is connected to be input. The signals output from the AND circuit AND2 are output to the drivers 14 and 15 as pulse signals P1 and P2, respectively.

<Oscillator operation example>
Next, an example of the operation of the oscillator of FIG. 3 according to the present embodiment will be described with reference to FIG.

  FIG. 5 is a timing chart showing an example of signal timing of each part in the oscillator of FIG. In FIG. 5, from the top to the bottom, the triangular wave voltage Vcap, the output signal of the comparator COMP1, the output signal of the comparator COMP2, the output signal of the comparator COMP3, the output signal of the comparator COMP4, the minimum pulse signal MINP output from the latch circuit LT2, And the signal timing in the maximum pulse signal MAXP output from the inverter Iv5.

  As shown in the figure, the comparator COMP1 outputs a low signal while the voltage Vcap is lower than the voltage Vz1, and a period when the voltage Vcap is equal to or higher than the voltage Vz1 (FIG. 5 illustrates the state of Vcap≈Vz1). The comparator COMP2 outputs a low signal while the voltage Vcap is lower than the voltage Vz2, and outputs a high signal when the voltage Vcap is higher than the voltage Vz2.

  Similarly, the comparator COMP3 outputs a low signal while the voltage Vcap is lower than the voltage Vz3, and outputs a high signal when the voltage Vcap is higher than the voltage Vz3. The comparator COMP4 outputs the voltage Vcap that is equal to or higher than the voltage Vz4. A low signal is output during a lower period (FIG. 5 illustrates the state of Vcap≈Vz4), and a high signal is output during a period when the voltage Vcap is higher than the voltage Vz4.

  The latch circuit LT1 receives the comparison result of the comparator COMP1 and the inverted signal of the comparison result of the comparator COMP4. The latch circuit LT2 receives the comparison result of the comparator COMP1 and the inverted signal of the comparison result of the comparator COMP2. Is entered. The comparison result of the comparator COMP3 and the inverted signal of the comparison result of the comparator COMP4 are input to the latch circuit LT3.

  Therefore, as shown in the figure, the latch circuit LT2 outputs a minimum pulse signal MINP whose voltage is high during the period from when the triangular wave voltage Vcap is the voltage Vz1 to when the voltage drops to the voltage Vz2.

  Further, as shown in the figure, the voltage from the latch circuit LT3 starts at the timing when the triangular wave voltage Vcap rises starting at the voltage voltage Vz4 and becomes the voltage Vz3, and the voltage becomes high during the period corresponding to the timing when the voltage Vz4 falls. The maximum pulse signal MAXP is output.

<Operation example of pulse generator and switching circuit>
Here, operations in the pulse generator 2 and the switching circuit 3 will be described.

  The operational amplifier 8 compares the reference voltage VREF and the feedback voltage VFB obtained by dividing the power supply voltage VBAT by the resistors 22 and 23 and outputs the comparison difference to the comparator 9 as an analog voltage.

  The comparator 9 compares the analog voltage output from the operational amplifier 8 with the triangular wave voltage Vcap output from the oscillator 12 to generate a PWM (Pulse Width Modulation) signal. Therefore, the frequency of the PWM signal for driving the transistors 16 and 17 is determined by the triangular wave voltage Vcap. The PWM signal output from the comparator 9 is input to the output stage control logic unit 6.

  When the switching power supply circuit 1 is in a normal operation, the output stage control logic unit 6 generates pulse signals P1 and P2 based on the input PWM signal. Here, the normal operation time is an operation mode when the load connected to the switching power supply circuit 1 performs normal operation.

  The pulse signals P1 and P2 output from the output stage control logic unit 6 are output at substantially the same voltage level, but the timing is set so that the transistors 16 and 17 are not simultaneously turned on by a logic circuit (not shown). Are shifted and output.

  The pulse signal P1 output from the output stage control logic unit 6 is input to the driver 14. The pulse signal P1 is amplified by the driver 14, is output as the drive signal Sdv1, and is input to the gate of the transistor 16. The transistor 16 is driven based on the drive signal Sdv1.

  The pulse signal P2 output from the output stage control logic unit 6 is amplified by the driver 15, output as the drive signal Sdv2, and input to the gate of the transistor 17. The transistor 17 is driven based on the drive signal Sdv2.

  The transistors 16 and 17 are switched on / off based on the drive signals Sdv1 and Sdv2 input to the gates, and perform switching operations. As a result, a rectangular switching voltage VP is output from the connection node between the transistors 16 and 17.

  When the drive signals Sdv1 and Sdv2 are at a low level and the transistor 16 is turned on and the transistor 17 is turned off, a current flows through the coil 18, the capacitor 20, and the load. At this time, electrical energy is stored in the coil 18 and the capacitor 20.

  Subsequently, when the drive signals Sdv1 and Sdv2 are at a high level and the transistor 16 is turned off and the transistor 17 is turned on, a current flows through the load by the electrical energy stored in the coil 18 and the capacitor 20.

  As a result, the switching voltage VP output from the connection portion between the transistor 16 and the transistor 17 is smoothed by the coil 18 and the capacitor 20 and output as the power supply voltage VBAT.

  In the switching power supply circuit 1, the current of the power supply voltage VBAT supplied from VOUT is adjusted by the duty ratio of the PWM signal, that is, the on time of the transistor 16. For example, when a large amount of current is required, the current supply capability is increased by increasing the duty ratio of the PWM signal and increasing the on-time of the transistor 16.

  On the other hand, when the load is light, the duty ratio of the PWM signal is reduced to reduce the ON time of the transistor 16, thereby reducing the output period of the switching voltage VP, thereby reducing the current supply capability.

  In the switching power supply circuit, when the load is very heavy and a large current flows (hereinafter, referred to as “heavy load operation”), the voltage level of the feedback voltage VFB greatly decreases below the voltage level of the reference voltage VREF, and the PWM signal output from the comparator 9 There was a problem that the voltage level was always high. The heavy load operation is a mode in which the load connected to the switching power supply circuit 1 is a heavy load that requires a large amount of current.

  Further, when the load is very light and almost no current flows (hereinafter referred to as “light load operation”), the voltage level of the feedback voltage VFB rises higher than the voltage level of the reference voltage VREF and is output from the comparator 9 There was a problem that the voltage level of the signal was always low. The light load operation is a mode in which the load connected to the switching power supply circuit 1 is a light load due to a standby state or the like.

  When the voltage level of the PWM signal becomes high and the transistor 16 is always turned on during heavy load operation, an excessive current flows in the current path from the switching transistor 16 to the output terminal VOUT, causing the coil 18 shown in FIG. There is a risk of damage to the smoothing circuit and the like. Further, during light load operation, a PWM signal having a predetermined voltage level is not input to the output stage control logic unit 6, so that the output stage control logic unit 6 may malfunction.

  In order to prevent them, the output stage control logic unit 6 according to the present invention outputs the maximum pulse signal MAXP generated by the oscillator 12 to the drivers 14 and 15 as pulse signals P1 and P2, respectively, during heavy load operation. Further, during light load operation, the minimum pulse signal MINP generated by the oscillator 12 is output to the drivers 14 and 15 as pulse signals P1 and P2, respectively.

  In the present invention, as shown in FIG. 5, the maximum pulse signal MAXP and the minimum pulse signal MINP are generated depending on the frequency of the triangular wave voltage Vcap, that is, the frequency of the PWM signal that drives the transistors 16 and 17. Therefore, even for different PWM signal frequencies, the ratio of the pulse width (period in which the potential is high) in the maximum pulse signal MAXP and the minimum pulse signal MINP can be made substantially constant. This makes it possible to optimize the pulse width of the minimum pulse signal or maximum pulse signal according to the switching frequency fluctuation, thus preventing overcurrent supply to the output circuit during heavy load operation and light load operation. It is possible to prevent malfunction of the output stage control logic unit at the time. This allows the user to select the capacitance value of the capacitor Cap in order to set the desired frequency of the PWM signal.

  As a result, when the frequency of the triangular wave voltage Vcap is varied, for example, the pulse width of the maximum pulse signal MAXP becomes too small with respect to the frequency of the voltage Vcap, thereby preventing a decrease in output current during heavy load operation. it can.

<Operation example of output stage control logic unit>
Here, an example of the operation in the output stage control logic unit of FIG. 4 will be described with reference to FIGS.

  FIG. 6 is a timing chart showing an example of the output stage control logic unit of FIG. 4 during normal operation. FIG. 7 is a timing chart showing an example of the output stage control logic unit of FIG. 4 during heavy load operation. FIG. 8 is a timing chart showing an example of the output stage control logic unit of FIG. 4 during light load operation. FIG. 9 is a timing chart showing an example of the output stage control logic unit of FIG. 4 when the overcurrent detection signal KS is input.

  When the switching power supply circuit 1 is in normal operation, the PWM signal output from the comparator 9 is output from the output stage control logic unit 6 as pulse signals P1 and P2, as shown in FIG. The drivers 14 and 15 amplify the PWM signal output from the comparator 9 and drive the transistors 16 and 17, respectively.

  Subsequently, when the switching power supply circuit 1 is in a heavy load operation, the PWM signal is always a high level signal as shown in FIG. Further, as in FIG. 6, since no overcurrent is detected, the overcurrent detection signal KS is at an inactive high level. Therefore, the maximum pulse signal MAXP is output from the output stage control logic unit 6 as the pulse signals P1 and P2.

  Therefore, the drivers 14 and 15 amplify the maximum pulse signal MAXP output from the output stage control logic unit 6 and drive the transistors 16 and 17, respectively.

  Further, when the switching power supply circuit 1 is in a light load operation, the PWM signal is always a low level signal as shown in FIG. Similarly to FIG. 6, since no overcurrent is detected, the overcurrent detection signal KS is at a high level. Therefore, the minimum pulse signal MINP is output from the output stage control logic unit 6 as the pulse signals P1 and P2.

  Therefore, the drivers 14 and 15 amplify the minimum pulse signal MINP output from the output stage control logic unit 6, and drive the transistors 16 and 17, respectively.

  When the overcurrent detection unit 4 detects an overcurrent, an overcurrent detection signal KS that is an active low level signal is output from the overcurrent detection unit 4 as shown in FIG. Thus, the output of the pulse signals P1 and P2 from the output stage control logic unit 6 is stopped while the output stage control logic unit 6 is in the low level signal period, that is, the overcurrent detection signal KS is active.

  Therefore, the drivers 14 and 15 amplify the pulse signals P1 and P2 that are substantially synchronized with the overcurrent detection signal KS that is a low-level signal output from the output stage control logic unit 6, and drive the transistors 16 and 17, respectively. .

  Note that the pulse widths of the maximum pulse signal MAXP and the minimum pulse signal MINP were respectively divided by selecting a desired resistance value as the resistance value in the resistors R1 to R6 in FIG. 3 in the design of the switching power supply circuit, for example. It is possible to set the voltages Vz1 to Vz4, which are voltages, to desired values.

  For example, when the pulse width (high period) of the maximum pulse signal MAXP is increased, the voltage level of the voltage Vz3 is brought close to the voltage level of the voltage Vz4, and when the pulse width of the maximum pulse signal MAXP is decreased, the voltage is The voltage level of Vz3 is brought close to the voltage level of voltage Vz2.

  Similarly, when the pulse width of the minimum pulse signal MINP is increased, the voltage level of the voltage Vz2 is brought close to the voltage level of the voltage Vz3, and when the pulse width of the minimum pulse signal MINP is decreased, the voltage level of the voltage Vz2. To be close to the voltage level of the voltage Vz1.

  As described above, since the pulse widths of the maximum pulse signal MAXP and the minimum pulse signal MINP are generated in accordance with the triangular wave voltage Vcap that determines the switching frequency of the transistors 16 and 17, various designs can be made in the switching power supply circuit design. Even when a switching frequency corresponding to the application is set, a switching power supply circuit device that makes the pulse widths of the maximum pulse signal MAXP and the minimum pulse signal MINP occupying the switching frequency substantially constant can be provided. The charging efficiency can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In addition, this invention is not limited to above-described embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.

  Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

DESCRIPTION OF SYMBOLS 1 Switching power supply circuit 2 Pulse generation part 3 Switching circuit 4 Overcurrent detection part 5 Pulse generation circuit 6 Output stage control logic part 7 Pulse output part 8 Operational amplifier 9 Comparator 10 Capacitor 11 Resistance 12 Oscillator 14 Driver 15 Driver 16 Transistor 17 Transistor 18 Coil 19 capacitor 20 capacitor 21 resistor 22 resistor 23 resistor 24 voltage dividing unit 25 voltage comparing unit 26 pulse signal generating unit BP battery pack Cap capacitor Ri current detection resistor R1 resistor R2 resistor R3 resistor R4 resistor R5 resistor R6 resistor COMP1 comparator COMP2 comparator COMP3 Comparator COMP4 Comparator Iv1 Inverter Iv2 Inverter Iv3 Inverter Iv4 Inverter Iv5 Inverter LT1 Latch circuit LT2 Latch Road LT3 latch circuit IR1 constant current circuit IR2 constant current circuit T1 transistor T2 transistor OR1 OR circuit AND1 AND circuit AND2 AND circuit

Claims (13)

A second power supply voltage that has been subjected to switching conversion, including a switching unit that generates a switching voltage by switching a first power supply voltage supplied from the outside, and a smoothing unit that smoothes the switching voltage generated by the switching unit. A switching circuit unit that supplies a triangular wave, a pulse generation unit that generates a maximum pulse signal and a minimum pulse signal, a voltage level of the second power supply voltage and a voltage displacement of the triangular wave output from the pulse generation unit A control unit including a PWM generation unit that generates a PWM signal according to a comparison result, and a control signal output unit that supplies a drive signal that controls generation of the switching voltage to the switching unit;
Have
The pulse generation unit has a pulse width that is high for a period set based on a timing at which the minimum voltage level in the voltage displacement becomes the next minimum voltage level in accordance with the voltage displacement of the triangular wave. Generating the maximum pulse signal and the minimum pulse signal set to the minimum pulse width generated at the timing of the maximum voltage level in the voltage displacement of the triangular wave,
The control signal output unit uses the drive signal generated based on the PWM signal in the first operation state as the drive signal, and the maximum pulse signal generated by the pulse generation unit in the second operation state as the drive signal. In the third operation state, the switching power supply circuit outputs the minimum pulse signal generated by the pulse generator as the drive signal. The switching power supply circuit according to claim 1,
The pulse generator includes means for setting first to fourth threshold values, wherein the first threshold value is a maximum voltage, the fourth threshold value is a minimum voltage, and the second threshold value is The threshold voltage is set lower than the first threshold by a predetermined value, and the third threshold voltage is set higher than the fourth threshold by a predetermined value. Generating the minimum pulse signal having a pulse width in which the voltage becomes high during a period from the timing when the displacement becomes the voltage of the first threshold to the timing when the displacement becomes lower than the voltage of the second threshold; The maximum pulse width has a pulse width that is high during a period from a timing at which the voltage displacement of the voltage rises higher than the third threshold voltage at the time of rise to a timing at which the voltage at the fourth threshold value at the time of fall. Generate a pulse signal. Etching the power supply circuit. The switching power supply circuit according to claim 2,
The second operating state is a state in which more current is supplied than in the first operating state,
The switching power supply circuit, wherein the third operation state is a state in which less current is supplied than in the first operation state. The switching power supply circuit according to claim 1,
And an overcurrent detection unit that outputs an overcurrent detection signal when it is detected that an overcurrent flows in the current path for supplying the second power supply voltage;
The switching power supply circuit, wherein the control unit stops outputting the drive signal during a period in which the overcurrent detection signal output from the overcurrent detection unit is active. A first terminal to which a first power supply voltage is supplied from the outside; a second terminal for supplying a second power supply voltage subjected to switching conversion; a switching unit for switching the first power supply voltage to generate a switching voltage; A smoothing unit that smoothes the switching voltage generated by the switching unit, and the switching circuit unit that supplies the second power supply voltage that has been subjected to the switching conversion from the second terminal;
A pulse generator that generates a triangular wave, a maximum pulse signal, and a minimum pulse signal, and compares the voltage level of the second power supply voltage with the voltage displacement of the triangular wave output from the pulse generator to generate a PWM signal based on the comparison result A control unit that includes a PWM generation unit that performs control, and a control signal output unit that supplies a drive signal that controls generation of the switching voltage to the switching unit;
Have
The pulse generation unit has a pulse width that is high for a period set based on a timing at which the minimum voltage level in the voltage displacement becomes the next minimum voltage level in accordance with the voltage displacement of the triangular wave. Generating the maximum pulse signal and the minimum pulse signal set to the minimum pulse width generated at the timing of the maximum voltage level in the voltage displacement of the triangular wave,
The control signal output unit outputs the drive signal generated based on the PWM signal in the first operation state, and the maximum pulse signal generated by the pulse generation unit in the second operation state. The electronic device further includes a switching power supply circuit configured to output the minimum pulse signal generated by the pulse generator as the drive signal in the third operation state. The electronic device according to claim 5.
The pulse generation unit includes means for setting first to fourth threshold values, wherein the first threshold value is set to a maximum voltage, the fourth threshold value is set to a minimum voltage, and the second threshold value is set. The threshold voltage is set lower than the first threshold by a predetermined value, and the third threshold voltage is set higher than the fourth threshold by a predetermined value. Generating the minimum pulse signal having a pulse width that is high during a period from the timing when the displacement becomes the voltage of the first threshold to the timing when the displacement becomes lower than the voltage of the second threshold; The maximum pulse signal having a pulse width that is high during a period from a timing at which the displacement becomes higher than the third threshold voltage at the time of rising to a timing at which the voltage becomes the fourth threshold voltage at the time of falling. Configuration configuration to generate Having etching power circuit, an electronic device. The electronic device according to claim 6.
The second operating state is a state in which more current is supplied than in the first operating state,
The electronic device, wherein the third operating state is a state in which less current is supplied than in the first operating state. The electronic device according to claim 5.
And an overcurrent detection unit that outputs an overcurrent detection signal when it is detected that an overcurrent flows in a current path of the second power supply voltage supplied from the second terminal,
The electronic device, wherein the control unit stops outputting the drive signal while the overcurrent detection signal output from the overcurrent detection unit is active. A switching circuit configured to supply a switching-converted second power supply voltage, including: a transistor circuit that generates a switching voltage from a first power supply voltage supplied from outside; and a smoothing unit that smoothes the generated switching voltage. A semiconductor integrated circuit device mounted with a control unit for controlling the switching operation of the transistor circuit,
The control unit compares the voltage level of the second power supply voltage with the voltage displacement of the triangular wave output from the pulse generation unit and compares the triangular wave, the maximum pulse signal, and the minimum pulse signal to generate a comparison result. A PWM generation unit that generates a PWM signal based on the control signal output unit that generates a drive signal for controlling the switching operation of the transistor circuit and supplies the drive signal to the control electrode of the transistor;
Have
The pulse generation unit has a pulse width that is high for a period set based on a timing at which the minimum voltage level in the voltage displacement becomes the next minimum voltage level in accordance with the voltage displacement of the triangular wave. Generating the maximum pulse signal and the minimum pulse signal set to the minimum pulse width generated at the timing of the maximum voltage level in the voltage displacement of the triangular wave,
The control signal output unit uses the drive signal generated based on the PWM signal in the first operation state as the drive signal, and the maximum pulse signal generated by the pulse generation unit in the second operation state as the drive signal. In the third operation state, the semiconductor integrated circuit device outputs the minimum pulse signal generated by the pulse generator as the drive signal. The semiconductor integrated circuit device according to claim 9.
The pulse generator is
Means for setting first to fourth threshold values, wherein the first threshold value is a maximum voltage, the fourth threshold value is a minimum voltage, and the voltage of the second threshold value is The third threshold voltage is set to be smaller than the first threshold value by a predetermined value and larger than the fourth threshold value by a predetermined value;
The minimum pulse signal having a pulse width that is high during a period from the timing when the voltage displacement of the triangular wave becomes the first threshold voltage to the timing when it becomes lower than the second threshold voltage, and the triangular wave The maximum pulse width having a pulse width that starts at a timing when the voltage displacement of the first voltage becomes higher than the voltage of the third threshold value at the time of rising and becomes high for a period until the voltage becomes the voltage of the fourth threshold value at the time of falling. A semiconductor integrated circuit device that generates a pulse signal. The semiconductor integrated circuit device according to claim 10.
The second operating state is a state in which more current is supplied than in the first operating state,
The semiconductor integrated circuit device is a state in which the third operation state supplies a smaller current than the first operation state. The semiconductor integrated circuit device according to claim 9.
And an overcurrent detection unit that outputs an overcurrent detection signal when it is detected that an overcurrent flows in the current path for supplying the second power supply voltage;
The semiconductor integrated circuit device, wherein the control unit stops outputting the drive signal while the overcurrent detection signal output from the overcurrent detection unit is active. A switching circuit configured to supply a switching-converted second power supply voltage, including a transistor circuit that generates a switching voltage from a first power supply voltage supplied from outside, and a smoothing unit that smoothes the generated switching voltage. A semiconductor integrated circuit device equipped with a control unit for controlling a switching operation of the transistor circuit, which is used together with a circuit,
The controller is
Including means for generating a triangular wave, means for setting first to fourth threshold values, maximum pulse signal generating means, and minimum pulse signal generating means, wherein the first to fourth threshold values are The first threshold value is the maximum voltage, the fourth threshold value is the minimum voltage, the second threshold voltage is smaller than the first threshold value by a predetermined value, The threshold voltage of 3 is set to be larger than the fourth threshold by a predetermined value, and the minimum pulse signal generating means is configured so that the voltage displacement of the triangular wave becomes the voltage of the first threshold. To generate a minimum pulse signal having a pulse width that is high for a period from when the voltage becomes lower than the second threshold voltage, and the maximum pulse signal generating means generates the third pulse signal when the voltage displacement of the triangular wave increases. Timing of the threshold voltage A pulse generator arrangement for generating a maximum pulse signal having a pulse width period becomes high up to the timing at which the voltage of the fourth threshold at the time of the beginning descent,
A PWM generator that compares the voltage level of the second power supply voltage with the voltage displacement of the triangular wave output from the pulse generator and generates a PWM signal based on the comparison result;
A control signal output unit that generates a drive signal for controlling the switching operation of the transistor circuit and supplies the drive signal to the transistor circuit;
An overcurrent detection unit that monitors a current in a current path for supplying the second power supply voltage and outputs an overcurrent detection signal when it is detected that an overcurrent flows;
Have
The control signal output unit is
When the amount of current for supplying the second power supply voltage is in the first operating state, a drive signal generated based on the PWM signal is output,
In the second operation state in which more current is supplied than in the first operation state, the maximum pulse signal generated by the pulse generation unit is output as the drive signal,
In the third operation state in which less current is supplied than in the first operation state, the minimum pulse signal generated by the pulse generation unit is output as the drive signal,
A semiconductor integrated circuit device, wherein output of the drive signal is stopped while the overcurrent detection signal output from the overcurrent detection unit is active.

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