JP6794249B2 - Phase compensation circuit and DC / DC converter using it - Google Patents

Description

The present invention relates to a phase compensation circuit and a DC / DC converter using the same.

Conventionally, a DC / DC converter (so-called switching power supply) that turns on / off an output transistor to generate a desired output voltage from an input voltage has been used as a power supply means for various applications.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

Japanese Unexamined Patent Publication No. 2008-61433

FIG. 15 is a circuit diagram showing a first conventional example of a DC / DC converter. In the DC / DC converter X1 of this conventional example, when the load is light (XSLP = L), the output transistor X11 and the synchronous rectifier transistor X12 are both turned off, and then the error amplifier X30, the oscillator X50, the PWM comparator X60, etc. It has a function to shift to sleep mode with low power consumption by stopping.

By the way, the on-duty Don of the DC / DC converter X1 (= the ratio of the on-period Ton of the output transistor X11 to the predetermined period T) is the first voltage VC and the second voltage RAMP input to the PWM comparator X60, respectively. It depends on the comparison result. Therefore, if the error amplifier X30 that generates the first voltage VC is stopped when shifting to the sleep mode, the DC / DC converter X1 is used until the start of the error amplifier X30 is completed when the sleep mode is released. On-duty Don becomes unstable.

Therefore, the DC / DC converter X1 of this conventional example sets the first voltage VC to an appropriate bias value (= the initial value of the first voltage VC when the sleep mode is released) while the error amplifier X30 is stopped in the sleep mode. It has a bias portion X80 that is fixed to (corresponding to).

However, in the DC / DC converter X1 of the present conventional example, since the bias unit X80 consumes power even in the sleep mode, there is room for further improvement in reducing the power consumption.

FIG. 16 is a circuit diagram showing a second conventional example of the DC / DC converter. The DC / DC converter Y1 of this conventional example is a step-down switching power supply of the current mode control method, and has a function of limiting the coil current IL of the switch output stage Y10 to the upper limit current value ILMT or less by using the clamper Y110 (so-called OCP [ It has an over current protection function).

FIG. 17 is a COMP-IL characteristic diagram for explaining the OCP function by the clamper Y110. The horizontal axis shows the error voltage COMP generated by the error amplifier Y30, and the vertical axis shows the average value IL (ave) of the coil current IL.

The clamper Y110 limits the error voltage COMP to the upper limit voltage value VLMT or less. As a result, in the differential amplifier Y80, the output feedback control is applied so as to limit the current sense voltage CSNS corresponding to the coil current IL to the upper limit voltage value VLMT or less, so that the coil current IL becomes the upper limit current value ILMT or less. Be restricted.

In order to suppress the rush current (= excessive coil current IL) that occurs when the switch output stage Y10 is short-circuited abnormally, the DC / DC converter Y1 is turned on following a sudden fluctuation in the output voltage Vo or the input voltage Vi. It is necessary to sharply change the duty Don (which is, by extension, the first voltage VC input from the differential amplifier Y80 to the PWM comparator Y60). In order to meet this demand, it is conceivable to increase the response speed of the differential amplifier Y80 and the clamper Y110 by increasing the drive current, for example.

However, if the response speed of the differential amplifier Y80 or the clamper Y110 is carelessly increased, there is a problem that the voltage loop characteristics change and the oscillation risk increases.

The invention disclosed in the present specification is a phase compensation circuit capable of reducing power consumption or suppressing rush current of a DC / DC converter in view of the above-mentioned problems found by the inventors of the present application. It is an object of the present invention to provide a DC / DC converter using this.

The phase compensation circuit disclosed in the present specification compensates for the phase of the first voltage input to the PWM comparator of the DC / DC converter provided with the sleep mode, and is a phase compensation resistor unit including a resistor. And; a phase compensation capacitance section including a plurality of capacitors; in the sleep mode, each capacitor is switched to the first connection state and at least one capacitor is charged with the first bias voltage, while when the sleep mode is released, the sleep mode is released. It has a configuration (first configuration) having a switch group that switches each capacitor to the second connection state and sets the first voltage to a desired initial value.

In the phase compensation circuit having the first configuration, the switch group may have a configuration (second configuration) in which at least one connection destination of the plurality of capacitors is switched according to the sleep control signal.

Further, in the phase compensation circuit having the second configuration, the phase compensation capacitance section includes a first capacitor and a second capacitor, each of which has a first end connected to a ground end, and the switch group includes the first capacitor. The first switch that conducts / cuts off between the second end of the capacitor and the grounded end and the second end of the second capacitor are connected to the application end of the first bias voltage or the second of the first capacitor. It is preferable to have a configuration (third configuration) including a second switch for switching whether to connect to the end.

Further, in the phase compensation circuit having the third configuration, when the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) (however, A configuration (fourth) in which 0 <k <1) is satisfied and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage. The configuration of) should be used.

Further, in the phase compensation circuit having the third configuration, the phase compensation capacitance section further includes a third capacitor whose first end is connected to the ground end, and the switch group includes a second capacitor of the third capacitor. A configuration (fifth configuration) further includes a third switch for switching whether the end is connected to an application end of a second bias voltage different from the first bias voltage or to the second end of the first capacitor. Good.

Further, the phase compensation circuit having the fifth configuration is C1 when the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and the capacitance value of the third capacitor is C3. : C2: C3 = {1- (k + k')}: k: k'(where 0 <k <1 and 0 <k'<1) is satisfied, and the PWM comparator meets the first voltage. The amplitude of the second voltage to be compared may be set to k times the input voltage or the output voltage (sixth configuration).

Further, in the phase compensation circuit having any of the third to sixth configurations, the first end of the resistor is connected to the input end of the PWM comparator, and the second end is the second end of the first capacitor. It is preferable to use a configuration (seventh configuration) connected to.

Further, the phase compensation circuit having the seventh configuration is configured to further have a switch for conducting / blocking between the input end of the PWM comparator and the previous stage circuit in response to the sleep control signal (eighth configuration). Good.

Further, the DC / DC converter disclosed in the present specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier that generates an error signal, a phase compensation circuit that generates a first voltage by receiving the input of the error signal, an oscillator that generates a second voltage of a lamp waveform, and the first voltage and the second voltage. A PWM comparator that generates a comparison signal by comparing the above, and a driver that generates a drive signal of the switch output stage in response to the comparison signal. The phase compensation circuit includes any of the first to eighth phases. It is preferable to use a configuration (9th configuration) in which a phase compensation circuit composed of the configurations is used.

In the DC / DC converter having the ninth configuration, the switch output stage is a step-down type, the first bias voltage is the output voltage, and the amplitude of the second voltage fluctuates according to the input voltage. It is preferable to use a configuration (10th configuration) which is a value.

Further, in the DC / DC converter having the ninth configuration, the switch output stage is a step-up type, the first bias voltage is the input voltage, and the amplitude of the second voltage fluctuates according to the output voltage. The configuration may be a value (11th configuration).

Further, the phase compensation circuit disclosed in the present specification compensates for the phase of the first voltage input to the PWM comparator of the DC / DC converter adopting the current mode control method, and is a phase compensation resistor. The phase compensation resistor section and one of the phase compensation capacitance sections include a plurality of resistors or a plurality of capacitors, and among the plurality of resistors or the plurality of capacitors, the phase compensation resistor section and the phase compensation capacitance section include a plurality of resistors and a plurality of capacitors. The output voltage or input voltage of the DC / DC converter is applied to at least one ground side node as a monitoring target voltage (12th configuration).

In the phase compensation circuit having the twelfth configuration, the phase compensation capacitance section is connected to a first capacitor whose first end is connected to the ground end and to the application end of the monitored voltage at the first end. The phase compensation resistor portion includes a second capacitor, and the phase compensation resistor section includes a resistor whose first end is connected to the input end of the PWM comparator and whose second end is connected to the second end of each capacitor (13th). (Structure of).

Further, in the phase compensation circuit having the thirteenth configuration, when the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) ( However, 0 <k <1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage (third). It is preferable to use the configuration of 14).

Further, in the phase compensation circuit having the twelfth configuration, the phase compensation resistor portion is connected to the first resistor whose first end is connected to the ground end and the first end to which the monitoring target voltage is applied. The phase compensation capacitance section includes a second resistor, and the phase compensation capacitance section includes a capacitor whose first end is connected to the input end of the PWM comparator and whose second end is connected to the second end of each resistor (15th). The configuration of) should be used.

Further, in the phase compensation circuit having the fifteenth configuration, when the resistance value of the first resistor is R1 and the resistance value of the second resistor is R2, R1 / R2 = k / (1-k) (however, The configuration (16th) in which 0 <k <1) is satisfied and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage. The configuration of) is recommended.

Further, the phase compensation circuit having the thirteenth or fourteenth configuration conducts / conducts between the second end of the first capacitor and the grounded end as a means for switching the connection state of each capacitor according to the sleep control signal. A configuration (17th configuration) further including a first switch for shutting off and a second switch for switching whether the first end of the second capacitor is connected to the application end of the monitored voltage or the ground end. ).

Further, the phase compensation circuit having the 15th or 16th configuration conducts / conducts between the second end of the first resistor and the grounding end as a means for switching the connection state of each resistor according to the sleep control signal. Between the first switch that shuts off, the second switch that conducts / cuts off between the first end of the second resistor and the application end of the monitored voltage, and the first end of the capacitor and the grounded end. It is preferable to have a configuration (18th configuration) further including a third switch for conducting / interrupting.

Further, the phase compensation circuit having the 17th or 18th configuration further includes a switch that conducts / cuts off between the input end of the PWM comparator and the previous stage circuit in response to the sleep control signal (19th configuration). ).

Further, the DC / DC converter disclosed in the present specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. A first amplifier that generates a first error signal, a first phase compensation circuit that generates an error voltage by receiving the input of the first error signal, and a clamper that limits the error voltage to a predetermined upper limit voltage value or less. A current detection unit that generates a current sense voltage according to the coil current of the switch output stage, a second amplifier that generates a second error signal corresponding to the difference between the error voltage and the current sense voltage, and the first 2 A comparison signal is obtained by comparing a second phase compensation circuit that receives an input of an error signal and outputs a first voltage, an oscillator that generates a second voltage of a lamp waveform, and the first voltage and the second voltage. It has a PWM comparator to be generated and a driver to generate a drive signal of the switch output stage according to the comparison signal, and as the second phase compensation circuit, phase compensation having the configuration of any one of 12th to 19th. It is said that the circuit is used (the 20th configuration).

Further, the DC / DC converter disclosed in the present specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier that generates an error signal, a phase compensation circuit that generates an error voltage by receiving the input of the error signal, a clamper that limits the error voltage to a predetermined upper limit voltage value or less, and a coil current of the switch output stage. A current detector that generates a current sense voltage according to the above, an arithmetic unit that generates a first voltage by arithmetic processing of the error voltage and the current sense voltage, an oscillator that generates a second voltage of a lamp waveform, and the above. The phase compensation circuit includes a PWM comparator that compares the first voltage with the second voltage to generate a comparison signal, and a driver that generates a drive signal for the switch output stage in response to the comparison signal. , The configuration (21st configuration) is such that a phase compensation circuit having any of the 12th to 19th configurations is used.

Further, the DC / DC converter disclosed in the present specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier that generates an error signal, a phase compensation circuit that generates a first voltage by receiving the input of the error signal, a clamper that limits the first voltage to a predetermined upper limit voltage value or less, and a switch output stage. A current detector that generates a current sense voltage according to the coil current, an oscillator that generates a second voltage of the lamp waveform, and an arithmetic unit that generates a third voltage by arithmetic processing of the second voltage and the current sense voltage. A PWM comparator that compares the first voltage with the third voltage to generate a comparison signal, and a driver that generates a drive signal for the switch output stage in response to the comparison signal. As the compensation circuit, a phase compensation circuit having any of the 12th to 19th configurations is used (the 22nd configuration).

In the DC / DC converter having any of the 20th to 22nd configurations, the switch output stage is a step-down type, the monitored voltage is the output voltage, and the amplitude of the second voltage is the input voltage. It is preferable to use a configuration (23rd configuration) that is a variable value according to the above.

Further, in the DC / DC converter having any of the 20th to 22nd configurations, the switch output stage is a step-up type, the monitored voltage is the input voltage, and the amplitude of the second voltage is the output voltage. The configuration (the 24th configuration) may be a variable value according to the above.

According to the invention disclosed in the present specification, a phase compensation circuit capable of reducing power consumption or suppressing rush current of a DC / DC converter, and a DC / DC converter using the same are provided. Is possible.

A circuit diagram showing a first embodiment of a DC / DC converter Timing chart showing the duty initial value setting operation in the first embodiment A circuit diagram showing a second embodiment of a DC / DC converter Timing chart showing the duty initial value setting operation in the second embodiment A circuit diagram showing a third embodiment of a DC / DC converter Timing chart showing the duty initial value setting operation in the third embodiment A circuit diagram showing a fourth embodiment of a DC / DC converter Timing chart showing rush current suppression operation in the fourth embodiment A circuit diagram showing a fifth embodiment of a DC / DC converter A circuit diagram showing a sixth embodiment of a DC / DC converter A circuit diagram showing a seventh embodiment of a DC / DC converter A circuit diagram showing an eighth embodiment of a DC / DC converter A circuit diagram showing a ninth embodiment of a DC / DC converter A circuit diagram showing a tenth embodiment of a DC / DC converter Circuit diagram showing a first conventional example of a DC / DC converter Circuit diagram showing a second conventional example of a DC / DC converter COMP-IL characteristic diagram for explaining OCP function by clamper

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a DC / DC converter. The DC / DC converter 1 of the present embodiment is a step-down switching of a PWM [pulse width modulation] drive system that generates an output voltage Vo from an input voltage Vi and supplies it to a load (CPU [central processing unit] or the like) (not shown). It is a power supply, and has a switch output stage 10, a feedback voltage generation unit 20, an error amplifier 30, a phase compensation circuit 40, an oscillator 50, a PWM comparator 60, and a driver 70.

In addition to the circuit elements described above, the DC / DC converter 1 may appropriately incorporate other protection circuits (undervoltage protection circuit, overvoltage protection circuit, overcurrent protection circuit, temperature protection circuit, etc.).

The switch output stage 10 is a step-down type that lowers the input voltage Vi to generate a desired output voltage Vo, and is synchronously rectified with the output transistor 11 (PMOSFET [P channel type metal oxide semiconductor field effect transistor] in this figure). A transistor 12 (NMOSFET [N channel type MOSFET] in this figure), a coil 13, and a capacitor 14 are included.

The source of the output transistor 11 is connected to the application end of the input voltage Vi. The drain of the output transistor 11 is connected to the first end of the coil 13. The gate of the output transistor 11 is connected to the application end of the gate signal G1. The output transistor 11 turns off when the gate signal G1 is high level and turns on when the gate signal G1 is low level.

The source of the synchronous rectifier transistor 12 is connected to the ground end (= the application end of the ground voltage GND). The drain of the synchronous rectifier transistor 12 is connected to the first end of the coil 13. The gate of the synchronous rectifier transistor 12 is connected to the application end of the gate signal G2. The synchronous rectifier transistor 12 turns on when the gate signal G2 is at a high level and turns off when the gate signal G2 is at a low level.

When a high voltage is applied to the switch output stage 10, high withstand voltage elements such as a power MOSFET, an IGBT [insulated gate bipolar transistor], and a SiC transistor are used as the output transistor 11 and the synchronous rectifier transistor 12, respectively. Good.

The output transistor 11 and the synchronous rectifier transistor 12 are complementarily turned on / off according to the gate signals G1 and G2. By such an on / off operation, a rectangular wave-shaped switch voltage Vsw that is pulse-driven between the input voltage Vi and the ground voltage GND is generated at the first end of the coil 13. The wording "complementary" is not only when the on / off states of the output transistor 11 and the synchronous rectifier transistor 12 are completely reversed, but also a simultaneous off period (dead time) of both transistors is provided. Including the case where.

The coil 13 and the capacitor 14 form an LC filter that rectifies and smoothes the switch voltage Vsw to generate an output voltage Vo. As described above, the first end of the coil 13 is connected to the drains (= application ends of the switch voltage Vsw) of the output transistor 11 and the synchronous rectifier transistor 12. Both the second end of the coil 13 and the first end of the capacitor 14 are connected to the application end of the output voltage Vo. The second end of the capacitor 14 is connected to the grounded end.

The feedback voltage generation unit 20 includes resistors 21 and 22 connected in series between the application end and the ground end of the output voltage Vo, and the feedback voltage Vfb (output voltage) corresponding to the output voltage Vo from the connection node between the two resistors. (Voltage divided voltage of Vo) is output. If the output voltage Vo is within the input dynamic range of the error amplifier 30, the feedback voltage generation unit 20 may be omitted and the output voltage Vo may be directly input to the error amplifier 30.

The error amplifier 30 is a current output type transconductance amplifier (so-called gm amplifier), and has a feedback voltage Vfb applied to the inverting input end (−) and a reference voltage Vref applied to the non-inverting input end (+). The error current signal I30 corresponding to the difference is generated. The error current signal I30 flows in the positive direction (= direction from the error amplifier 30 toward the phase compensation circuit 40) when the feedback voltage Vfb is lower than the reference voltage Vref, and in the negative direction (= direction when the feedback voltage Vfb is higher than the reference voltage Vref). = Flow from the phase compensation circuit 40 toward the error amplifier 30). The error amplifier 30 is in the operating state when the sleep control signal XSLP is at a high level (= logic level when the sleep mode is released), and the sleep control signal XSLP is at a low level (= logic level when the sleep mode is released). Sometimes it goes into a stopped state.

The phase compensation circuit 40 is connected between the error amplifier 30 and the PWM comparator 60, and receives the input of the error current signal I30 to generate the first voltage VC. The configuration and operation of the phase compensation circuit 40 will be described later.

The oscillator 50 uses a second voltage RAMP of a ramp waveform (= triangular waveform, saw waveform, or nth-order slope waveform (for example, n = 2)) pulse-driven at a predetermined switching frequency fsw (= 1 / T). Generate. Further, in the oscillator 50, the amplitude of the second voltage RAMP is set to a fluctuation value (= k × Vi) according to the input voltage Vi. Therefore, the amplitude of the second voltage RAMP increases as the input voltage Vi increases and decreases as the input voltage Vi decreases, but its technical significance will be described later. The oscillator 50 is in the operating state when the sleep control signal XSLP is at a high level, and is in a stopped state when the sleep control signal XSLP is at a low level, like the error amplifier 30 described above.

The PWM comparator 60 compares the first voltage VC applied to the non-inverting input end (+) with the second voltage RAMP applied to the inverting input terminal (−) to generate a comparison signal CMP. The comparison signal CMP has a high level when the first voltage VC is higher than the second voltage RAMP and a low level when the first voltage VC is lower than the second voltage RAMP. The PWM comparator 60, like the error amplifier 30 and the oscillator 50 described above, is in the operating state when the sleep control signal XSLP is at a high level, and is in a stopped state when the sleep control signal XSLP is at a low level.

The driver 70 includes a NAND gate 71 and an AND gate 72, and generates gate signals G1 and G2 (= corresponding to drive signals of the switch output stage 10 respectively) according to the comparison signal CMP. More specifically, the NAND gate 71 outputs a negative logical product operation signal of the sleep control signal XSLP and the comparison signal CMP as the gate signal G1. Further, the AND gate 72 outputs a logical product operation signal of the sleep control signal XSLP and the comparison signal CMP which is inverted and input as the gate signal G2.

Therefore, when the sleep control signal XSLP is at a high level, the gate signals G1 and G2 are basically logic inversion signals of the comparison signal CMP. More specifically, when the comparison signal CMP is at a high level, both the gate signals G1 and G2 are at a low level, so that the output transistor 11 is turned on and the synchronous rectifier transistor 12 is turned off. On the contrary, when the comparison signal CMP is at a low level, both the gate signals G1 and G2 are at a high level, so that the output transistor 11 is turned off and the synchronous rectifier transistor 12 is turned on.

On the other hand, when the sleep control signal XSLP is low level, the gate signal G1 becomes high level without depending on the comparison signal CMP, and the gate signal G2 becomes low level regardless of the comparison signal CMP. Therefore, both the output transistor 11 and the synchronous rectifier transistor 12 are turned off.

As described above, in the DC / DC converter 1 of the present embodiment, when the sleep control signal XSLP is at a low level, both the output transistor 11 and the synchronous rectifier transistor 12 are turned off, and then the error amplifier 30, the oscillator 50, and the oscillator 50, It also has a function of shifting to a sleep mode with low power consumption by stopping the PWM comparator 60 and the like.

It is desirable that the sleep control signal XSLP is set to a low level when the load is light (or no load). As a method for detecting the light load state, for example, a method for detecting the backflow of the coil current IL (= zero cross detection of the switch voltage Vsw) can be considered.

<Phase compensation circuit>
Subsequently, the configuration and operation of the phase compensation circuit 40 will be described in detail with reference to FIG. The phase compensation circuit 40 of this figure includes a phase compensation resistor section 41, a phase compensation capacitance section 42, and switches 43 to 45, compensates the phase of the first voltage VC, and prevents oscillation of the output feedback loop.

The phase compensation capacitance section 42 includes capacitors C1 and C2. The first end of each of the capacitors C1 and C2 is connected to the ground end. When the capacitance value of the entire phase compensation capacitance section 42 is C, the capacitance value of the capacitor C1 is C1, and the capacitance value of the capacitor C2 is C2, C = C1 + C2 and C2 / C1 = k / (1-k). (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitance section 42 of the present embodiment, the phase compensation capacitor is divided into two, and the technical significance thereof will be described later.

The phase compensation resistor unit 41 includes a resistor whose first end is connected to the non-inverting input end (+) of the PWM comparator 60 and whose second end is connected to the second end of the capacitor C1.

The switch 43 conducts / cuts off between the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 according to the sleep control signal XSLP. Specifically, the switch 43 is turned on when the sleep control signal XSLP is at a high level, conducts between the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30, and sleeps. When the control signal XSLP is at a low level, it is turned off to cut off between the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30.

The switch 44 conducts / cuts off between the second end and the ground end of the capacitor C1 according to the sleep control signal XSLP. Specifically, the switch 44 is turned on when the sleep control signal XSLP is at a low level to conduct between the second end and the ground end of the capacitor C1 and when the sleep control signal XSLP is at a high level. Turns off to cut off between the second end and the ground end of the capacitor C1.

The switch 45 switches whether the second end of the capacitor C2 is connected to the application end of the output voltage Vo (= corresponding to the first bias voltage) or the second end of the capacitor C1 according to the sleep control signal XSLP. Specifically, the switch 45 connects the second end of the capacitor C2 to the application end of the output voltage Vo when the sleep control signal XSLP is at a low level, and the capacitor when the sleep control signal XSLP is at a high level. The second end of C2 is connected to the second end of capacitor C1.

In this way, the switches 44 and 45 switch the connection destinations of the capacitors C1 and C2 according to the sleep control signal XSLP, so that the capacitors C1 and C2 are switched to the first connection state in the sleep mode (XSLP = L). While charging between both ends of the capacitor C2 with the output voltage Vo, when the sleep mode is released (XSLP = H), the capacitors C1 and C2 are switched to the second connection state and the first voltage VC is set to the desired initial value ( = K × Vo) functions as a group of switches to be set.

In the above first connection state, the switch 44 conducts between the second end of the capacitor C1 and the ground end, and the switch 45 connects the second end of the capacitor C2 to the application end of the output voltage Vo. Refers to the state of being. On the other hand, in the above-mentioned second connection state, the switch 44 cuts off between the second end of the capacitor C1 and the ground end, and the switch 45 connects the second end of the capacitor C2 to the second end of the capacitor C1. Refers to the state of being.

Next, the duty initial value setting operation when the sleep mode is released in the first embodiment will be described in detail with reference to FIG.

FIG. 2 is a timing chart showing an example of the duty initial value setting operation in the first embodiment, in order from the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and The comparison signal CMP is depicted.

Before the time t11, the sleep control signal XSLP is set to a low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are cut off, and the second end of the capacitor C1 and the ground end are electrically connected. Then, the second end of the capacitor C2 is connected to the application end of the output voltage Vo. Therefore, both ends of the capacitor C1 are in a discharged state, and both ends of the capacitor C2 are charged with the output voltage Vo. Further, in the sleep mode, both the first voltage VC and the second voltage RAMP become 0V, and the comparison signal CMP becomes a low level.

When the sleep control signal XSLP is raised to a high level at time t11, the DC / DC converter 1 returns to the wakeup mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are conducted, and the second end of the capacitor C1 and the ground end are cut off. Then, the second end of the capacitor C2 is connected to the second end of the capacitor C1.

That is, the phase compensation capacitance unit 42 is in a state in which the capacitor C1 discharged between both ends thereof and the capacitor C2 charged with the output voltage Vo are connected in parallel between both ends thereof when the sleep mode is released.

As a result, the first voltage VC follows the charge distribution law between the capacitors C1 and C2, and quickly reaches VC = k × Vo (= {C2 / (C1 + C2)} × Vo) without waiting for the start of the error amplifier 30. Is pulled up to.

Further, since the oscillator 50 is in the operating state after the time t11, the second voltage RAMP of the lamp waveform pulse-driven at the switching frequency fsw (= 1 / T) is generated. As described above, the amplitude of the second voltage RAMP is a fluctuation value (= k × Vi) according to the input voltage Vi.

Here, the on-duty Don (= Ton / T) of the DC / DC converter 1 is determined according to the comparison result between the first voltage VC and the second voltage RAMP. Specifically, from the timing when the first voltage VC (= k × Vo) and the second voltage RAMP (= (k × Vi / T) × Ton) match, the on-duty Don (= duty) when the sleep mode is released (Corresponding to the initial value) is Vo / Vi. This initial duty value is in agreement with the theoretical duty value when the input voltage Vi is stepped down to generate the desired output voltage Vo. Therefore, it is possible to prevent overshoot and undershoot of the output voltage Vo when the sleep mode is released.

If the phase compensation circuit 40 is used to set the initial duty value when the sleep mode is released, unlike the DC / DC converter X1 in FIG. 15, it is not necessary to move the bias unit X80 in the sleep mode. , Its power consumption can be significantly reduced.

Further, since the capacitor C2 does not pass a current after the charging is completed, the power consumption of the phase compensation circuit 40 in the sleep mode is also zero.

Further, in the DC / DC converter 1 of the present embodiment, the initial duty value at the time of releasing the sleep mode can be set by switching the switches 43 to 45 of the phase compensation circuit 40, so that the DC / DC converter 1 The restart time (= recovery time) of is ideally reduced to zero.

<Second Embodiment>
FIG. 3 is a circuit diagram showing a second embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the first embodiment (FIG. 1), and is characterized in that the capacitor C3 and the switch 46 are further included as components of the phase compensation circuit 40. Therefore, the same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 1 to omit duplicated explanations, and the feature portions of the second embodiment will be mainly described below.

Like the capacitors C1 and C2, the capacitor C3 is a component of the phase compensation capacitance section 42, and its first end is connected to the ground end. When the capacitance value of the entire phase compensation capacitance section 42 is C, the capacitance value of the capacitor C1 is C1, the capacitance value of the capacitor C2 is C2, and the capacitance value of the capacitor C3 is C3, C = C1 + C2 + C3, C1. : C2: C3 = {1- (k + k')}: k: k'(where 0 <k <1 and 0 <k'<1) is satisfied. As described above, in the phase compensation capacitance section 42 of the present embodiment, the phase compensation capacitor is divided into three, and the technical significance thereof will be described later.

Like the switches 44 and 45, the switch 46 is a component of a group of switches that switches the connection state of the capacitors C1 to C3 according to the sleep control signal XSLP, and the second end of the capacitor C3 is input voltage Vi (= first bias). It switches between connecting to the application end (corresponding to the second bias voltage different from the voltage) and connecting to the second end of the capacitor C1. Specifically, the switch 46 connects the second end of the capacitor C3 to the application end of the input voltage Vi when the sleep control signal XSLP is at low level, and the capacitor when the sleep control signal XSLP is at high level. The second end of C3 is connected to the second end of capacitor C1.

Next, the duty initial value setting operation when the sleep mode is released in the second embodiment will be described in detail with reference to FIG.

FIG. 4 is a timing chart showing an example of the duty initial value setting operation in the second embodiment, in order from the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and The comparison signal CMP is depicted.

Before the time t21, the sleep control signal XSLP is set to a low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are cut off, and the second end of the capacitor C1 and the ground end are electrically connected. Then, the second end of the capacitor C2 is connected to the application end of the output voltage Vo, and the second end of the capacitor C3 is connected to the application end of the input voltage Vi. Therefore, both ends of the capacitor C1 are discharged, both ends of the capacitor C2 are charged with the output voltage Vo, and both ends of the capacitor C3 are charged with the input voltage Vi. Further, in the sleep mode, both the first voltage VC and the second voltage RAMP become 0V, and the comparison signal CMP becomes a low level.

When the sleep control signal XSLP is raised to a high level at time t21, the DC / DC converter 1 returns to the wake-up mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are conducted, and the second end of the capacitor C1 and the ground end are cut off. , The second ends of each of the capacitors C2 and C3 are connected to the second end of the capacitor C1.

That is, the phase compensation capacitance section 42 connects in parallel the capacitor C1 whose both ends are discharged when the sleep mode is released, and the capacitors C2 and C3 whose ends are charged with the output voltage Vo and the input voltage Vi. It will be in the state of

As a result, the first voltage VC follows the charge distribution law between the capacitors C1 to C3, and VC = k × Vo + k'× Vi (= (C2 × Vo + C3 × Vi) / ( It is quickly pulled up to C1 + C2 + C3)}). That is, in the present embodiment, the initial value of the first voltage VC at the time of releasing the sleep mode is offset higher by k'× Vi as compared with the previous first embodiment.

Further, since the oscillator 50 is in the operating state after the time t21, the second voltage RAMP of the lamp waveform pulse-driven at the switching frequency fsw (= 1 / T) is generated. As described above, the amplitude of the second voltage RAMP is a fluctuation value (= k × Vi) according to the input voltage Vi.

Therefore, the on-duty Don (= corresponding to the initial duty value) when the sleep mode is released is (Vo / Vi) + (k'/ k). That is, the initial duty value in the present embodiment is a value intentionally increased from the theoretical duty value (= Vo / Vi) when the input voltage Vi is stepped down to generate a desired output voltage Vo.

The first voltage VC is lowered until VC = k × Vo due to the action of the output feedback loop. That is, the on-duty Don of the DC / DC converter 1 converges to the above theoretical duty value (= Vo / Vi) with the passage of time.

In this way, by setting the number of capacitor divisions in the phase compensation capacitance section 42 to 3 or more and charging each capacitor with a different bias voltage, the same effect as that of the first embodiment can be enjoyed, and then the first voltage. The initial value of VC can be adjusted arbitrarily. Therefore, for example, the initial duty value at the time of releasing the sleep mode can be optimized while considering the output loop characteristics of the DC / DC converter 1, so that overshooting and undershooting of the output voltage Vo can be prevented more appropriately. It will be possible.

In particular, by using the existing output voltage Vo and input voltage Vi for the DC / DC converter 1 as the bias voltage for charging the capacitors C2 and C3, it is not necessary to prepare a separate bias voltage. However, if it is not desired to increase the number of divisions of the capacitor, in the first embodiment (FIG. 1), the present embodiment is charged by charging the capacitor C2 with an arbitrary bias voltage (= Vo + α) higher than the output voltage Vo. It is possible to achieve the same effect as.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the first embodiment (FIG. 1), and is characterized in that the switch output stage 10 is changed from a step-down type to a step-up type. Therefore, the same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 1 to omit duplicated explanations, and the feature portions of the third embodiment will be mainly described below.

The switch output stage 10 is a boost type that boosts the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 15 (NMOSFET in this figure), a synchronous rectifier transistor 16 (PMOSFET in this figure), and a coil. 17 and a capacitor 18 are included.

The first end of the coil 17 is connected to the input end of the input voltage Vi. The second end of the coil 17 is connected to the drain of the output transistor 15 and the drain of the synchronous rectifier transistor 16. The source of the output transistor 15 is connected to the ground end. Both the source of the synchronous rectifier transistor 16 and the first end of the capacitor 18 are connected to the application end of the output voltage Vo. The second end of the capacitor 18 is connected to the grounded end.

The gate of the output transistor 15 is connected to the application end of the gate signal G3. The output transistor 15 turns on when the gate signal G3 is high level and turns off when the gate signal G4 is low level. The gate of the synchronous rectifier transistor 16 is connected to the application end of the gate signal G4. The synchronous rectifier transistor 16 turns off when the gate signal G4 is high level and turns on when the gate signal G4 is low level.

The output transistor 15 and the synchronous rectification transistor 16 are complementarily turned on / off according to the gate signals G3 and G4. By such an on / off operation, a rectangular wave-shaped switch voltage Vsw that is pulse-driven between the input voltage Vi and the ground voltage GND is generated at the second end of the coil 17. The wording "complementary" is not only when the on / off states of the output transistor 15 and the synchronous rectifier transistor 16 are completely reversed, but also a simultaneous off period (dead time) of both transistors is provided. Including the case where.

When the output transistor 15 is turned on and the synchronous rectifying transistor 16 is turned off, a coil current IL toward the ground end flows through the coil 17 via the output transistor 15 and its electric energy is stored. At this time, the switch voltage Vsw drops to almost the ground voltage GND via the output transistor 15. Since the synchronous rectifier transistor 16 is turned off, no current flows from the capacitor 18 toward the output transistor 15.

On the other hand, when the output transistor 15 is turned off and the synchronous rectifying transistor 16 is turned on, the electric energy stored in the coil 17 is released as a current due to the counter electromotive force generated in the coil 17. At this time, the coil current IL flowing through the synchronous rectifier transistor 16 flows into the load from the output end of the output voltage Vo as an output current, and also flows into the ground end via the capacitor 18, and the capacitor 18 is charged. By repeating the above operation, the load is supplied with the output voltage Vo in which the input voltage Vi is boosted.

When a high voltage is applied to the switch output stage 10, high voltage elements such as power MOSFETs, IGBTs, and SiC transistors may be used as the output transistor 15 and the synchronous rectifier transistor 16, respectively. This point is the same as in the first to third embodiments.

Further, as the switch output stage 10 is changed from the step-down type to the step-up type, the phase compensation circuit 40, the oscillator 50, the PWM comparator 60, and the driver 70 are also changed. The changes in each part will be described below.

In the phase compensation circuit 40, the bias voltage for charging the capacitor C2 is changed from the output voltage Vo to the input voltage Vi.

In the oscillator 50, the amplitude of the second voltage RAMP is changed from a fluctuation value (= k × Vi) according to the input voltage Vi to a fluctuation value (= k × Vo) according to the output voltage Vo.

The input polarity of the PWM comparator 60 is reversed from that of the first to third embodiments. That is, the first voltage VC is input to the inverting input end (−) of the PWM comparator 60, and the second voltage RAMP is input to the non-inverting input end (+) of the PWM comparator 60. Therefore, the logic level of the comparison signal CMP becomes a low level when the first voltage VC is higher than the second voltage RAMP, and the first voltage VC is the second voltage RAMP, contrary to that of the first to third embodiments. Higher level when lower than.

Further, the driver 70 includes an AND gate 73 and an OR gate 74 instead of the NAND gate 71 and the AND gate 72, and corresponds to the gate signals G3 and G4 (= corresponding to the drive signals of the switch output stage 10 respectively) according to the comparison signal CMP. ) Is generated. More specifically, the AND gate 73 outputs a logical product operation signal of the sleep control signal XSLP and the comparison signal CMP as the gate signal G3. Further, the OR gate 74 outputs the OR operation signal of the comparison signal CMP and the sleep control signal XSLP which is inverted and input as the gate signal G4.

Therefore, when the sleep control signal XSLP is at a high level, the gate signals G3 and G4 are basically the same logic signals as the comparison signal CMP. More specifically, when the comparison signal CMP is at a high level, both the gate signals G3 and G4 are at a high level, so that the output transistor 15 is turned on and the synchronous rectifier transistor 16 is turned off. On the contrary, when the comparison signal CMP is at a low level, both the gate signals G3 and G4 are at a low level, so that the output transistor 15 is turned off and the synchronous rectifier transistor 16 is turned on.

On the other hand, when the sleep control signal XSLP is low level, the gate signal G3 becomes low level without depending on the comparison signal CMP, and the gate signal G4 becomes high level regardless of the comparison signal CMP. Therefore, both the output transistor 15 and the synchronous rectifier transistor 16 are turned off.

FIG. 6 is a timing chart showing an example of the duty initial value setting operation in the third embodiment, in order from the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and The comparison signal CMP is depicted.

Before the time t31, the sleep control signal XSLP is set to a low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are cut off, and the second end of the capacitor C1 and the ground end are electrically connected. Then, the second end of the capacitor C2 is connected to the application end of the output voltage Vo. Therefore, both ends of the capacitor C1 are discharged, and both ends of the capacitor C2 are charged with the input voltage Vi. Further, in the sleep mode, both the first voltage VC and the second voltage RAMP become 0V, and the comparison signal CMP becomes a low level. There is no difference in these points except that the bias voltage applied to the capacitor C2 is changed from the output voltage Vo to the input voltage Vi.

When the sleep control signal XSLP is raised to a high level at time t31, the DC / DC converter 1 returns to the wakeup mode. At this time, in the phase compensation circuit 40, the non-inverting input end (+) of the PWM comparator 60 and the output end of the error amplifier 30 are conducted, and the second end of the capacitor C1 and the ground end are cut off. Then, the second end of the capacitor C2 is connected to the second end of the capacitor C1.

That is, the phase compensation capacitance unit 42 is in a state in which the capacitor C1 whose both ends are discharged and the capacitor C2 whose both ends are charged by the input voltage Vi are connected in parallel when the sleep mode is released.

As a result, the first voltage VC follows the charge distribution law between the capacitors C1 and C2, and quickly reaches VC = k × Vi (= {C2 / (C1 + C2)} × Vi) without waiting for the start of the error amplifier 30. Is pulled up to.

Further, since the oscillator 50 is in the operating state after the time t31, the second voltage RAMP of the lamp waveform pulse-driven at the switching frequency fsw (= 1 / T) is generated. As described above, the amplitude of the second voltage RAMP is a fluctuation value (= k × Vo) according to the output voltage Vo.

Here, the on-duty Don (= Ton / T) of the DC / DC converter 1 is determined according to the comparison result between the first voltage VC and the second voltage RAMP. Specifically, the on-duty when the sleep mode is released from the timing when the first voltage VC (= k × Vi) and the second voltage RAMP (= (k × Vo / T) × (T-Ton)) match. Don (= corresponding to the initial duty value) is 1- (Vi / Vo). This initial duty value is in agreement with the theoretical duty value when the input voltage Vi is boosted to generate the desired output voltage Vo. Therefore, even when the switch output stage 10 is a step-up type, it is possible to prevent overshoot and undershoot of the output voltage Vo when the sleep mode is released.

Of course, even when this embodiment is adopted, it goes without saying that the same effect as that of the first embodiment, that is, reduction of power consumption and shortening of restart time can be achieved.

Further, in this embodiment, an example in which the switch output stage 10 is changed to a step-up type while being based on the first embodiment (FIG. 1) is given, but the second embodiment (FIG. 3) may also be used as a base. it can. In that case, for example, the first bias voltage for charging the capacitor C2 may be the input voltage Vi, and the second bias voltage for charging the capacitor C3 may be the output voltage Vo.

In the first to third embodiments described above, as the output format of the switch output stage 10, the step-down type (FIGS. 1 and 3) and the step-up type (FIG. 5) are given as examples, but the buck-boost type and the reversing type are mentioned. May be adopted. Further, the rectification method of the switch output stage 10 is not limited to the above-mentioned synchronous rectification method, and can be changed to a diode rectification method (= a method using a rectifier diode instead of the synchronous rectifier transistor). Further, the output feedback control method of the DC / DC converter 1 is not limited to the voltage mode control method described above, and may be a current mode control method.

<Fourth Embodiment>
FIG. 7 is a circuit diagram showing a fourth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is a step-down switching power supply that employs a current mode control method, and includes a switch output stage 10, a feedback voltage generator 20, an error amplifier 30 (corresponding to the first amplifier), and The first phase compensation circuit 40, the oscillator 50, the PWM comparator 60, the driver 70, the differential amplifier 80 (corresponding to the second amplifier), the second phase compensation circuit 90, the current detection unit 100, and the clamper 110. And have.

Most of the above components are common to those of the first embodiment (FIG. 1). Therefore, with respect to the same components as those in the first embodiment, the same reference numerals as those in FIG. 1 are used to omit duplicated explanations, and the feature portions of the fourth embodiment will be mainly described below.

The switch output stage 10, the feedback voltage generation unit 20, and the error amplifier 30 are exactly the same as those in the first embodiment (FIG. 1).

The first phase compensation circuit 40 corresponds to the phase compensation circuit 40 of the first embodiment (FIG. 1), and receives an input of the first error current signal I30 from the error amplifier 30 to generate an error voltage COMP. However, in the DC / DC converter 1 of the present embodiment, since the transition function to the sleep mode is omitted, unlike the first embodiment (FIG. 1), the capacitor of the phase compensation capacitance section 42 is divided into a plurality of capacitors. No, and switches 43 to 45 are not provided.

The oscillator 50 and the PWM comparator 60 are exactly the same as those in the first embodiment (FIG. 1).

Due to the omission of the sleep mode, the driver 70 has been changed to a configuration including the inverters 75 and 76 instead of the NAND gate 71 and the AND gate 72. The inverters 75 and 76 output the logic inversion signals of the comparison signal CMP as gate signals G1 and G2, respectively. Therefore, when the comparison signal CMP is at a high level, both the gate signals G1 and G2 are at a low level, so that the output transistor 11 is turned on and the synchronous rectifying transistor 12 is turned off. On the contrary, when the comparison signal CMP is at a low level, both the gate signals G1 and G2 are at a high level, so that the output transistor 11 is turned off and the synchronous rectifier transistor 12 is turned on.

Like the error amplifier 30, the differential amplifier 80 is a current output type transmission amplifier (so-called gm amplifier), and is applied to the error voltage COMP applied to the inverting input terminal (-) and the non-inverting input terminal (+). The second error current signal I80 corresponding to the difference from the current sense voltage CSNS is generated. The second error current signal I80 flows in the positive direction (= the direction from the differential amplifier 80 toward the second phase compensation circuit 90) when the error voltage COMP is lower than the current sense voltage CSNS, and the error voltage COMP flows in the current sense voltage CSNS. When it is higher than, it flows in the negative direction (= the direction from the second phase compensation circuit 90 toward the differential amplifier 80).

The second phase compensation circuit 90 is connected between the differential amplifier 80 and the PWM comparator 60, and receives the input of the second error current signal I80 to generate the first voltage VC. The configuration and operation of the second phase compensation circuit 90 will be described later.

The current detection unit 100 generates a current sense voltage CSNS corresponding to the coil current IL flowing in the switch output stage 10. For example, the larger the average value IL (ave) of the coil current IL, the higher the current sense voltage CSNS, and conversely, the smaller the average value IL (ave) of the coil current IL, the lower the current sense voltage CSNS.

The clamper 110 limits the error voltage COMP to a predetermined upper limit voltage value VLMT or less. As a result, in the differential amplifier 80, the output feedback control is applied so as to limit the current sense voltage CSNS corresponding to the coil current IL to the upper limit voltage value VLMT or less, so that the coil current IL becomes the upper limit current value ILMT or less. Be restricted.

<Second phase compensation circuit>
Subsequently, the configuration and operation of the second phase compensation circuit 90 will be described in detail with reference to FIG. 7. The second phase compensation circuit 90 in the figure includes a phase compensation resistor section 91 and a phase compensation capacitance section 92, compensates the phase of the first voltage VC, and prevents oscillation of the output feedback loop.

The phase compensation capacitance unit 92 includes capacitors C4 and C5. The first end of the capacitor C4 is connected to the ground end. On the other hand, the first end of the capacitor C5 is connected to the application end of the output voltage Vo. When the capacitance value of the entire phase compensation capacitance section 92 is C, the capacitance value of the capacitor C4 is C4, and the capacitance value of the capacitor C5 is C5, C = C4 + C5 and C5 / C4 = k / (1-k). (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitance section 92 of the present embodiment, the capacitor for phase compensation is divided into two, and at least one ground side node (the first end of the capacitor C5 in this figure) is DC. The output voltage Vo of the / DC converter 1 is applied as the monitoring target voltage, and its technical significance will be described later.

The phase compensation resistor unit 91 includes a resistor whose first end is connected to the non-inverting input end (+) of the PWM comparator 60 and whose second end is connected to the second end of each of the capacitors C4 and C5.

FIG. 8 is a timing chart showing an example of the rush current suppression operation in the fourth embodiment, in order from the top, the output voltage Vo, the first voltage VC (solid line), the second voltage RAMP (broken line), and the comparison signal CMP. , And the coil current IL is depicted.

Before the time t43, since the switch output stage 10 is not short-circuited, the output voltage Vo is maintained at the target value Vo1. Further, since the first voltage VC is maintained at k × Vo1 by the action of the output feedback loop, the on-duty Don (= Ton / T) of the DC / DC converter 1 lowers the input voltage Vi to a desired level. It matches the theoretical duty value (= Vo1 / Vi) when the output voltage Vo (= Vo1) is generated.

On the other hand, when the switch output stage 10 is short-circuited at time t43 and the output voltage Vo suddenly drops from the target value Vo1 to the abnormal value Vo2, the first voltage VC outputs according to the charge distribution law between the capacitors C4 and C5. Without waiting for the response of the feedback loop, the voltage drops sharply with the same behavior as the output voltage Vo.

In particular, in the DC / DC converter 1 of the present embodiment, since C5 / C4 = k / (1-k) (however, 0 <k <1) is satisfied, when the output voltage Vo fluctuates by ΔV, the first One voltage VC fluctuates by k × ΔV. Further, as described above, the amplitude of the second voltage RAMP is a variable value (= k × Vi) according to the input voltage Vi.

With such a setting, the on-duty Don of the DC / DC converter 1 has a theoretical duty value (= Vo2 / Vi) corresponding to the abnormal value Vo2 of the output voltage Vo at the same time as the short circuit of the switch output stage 10 occurs. Will be shifted to. As a result, the rush current (= excessive coil current IL) generated when the switch output stage 10 is short-circuited abnormally can be effectively suppressed, so that deterioration of the element forming the switch output stage 10 can be prevented. ..

If the second phase compensation circuit 90 is used to realize duty tracking control according to the transient fluctuation of the output voltage Vo, it is not necessary to increase the response speed of the differential amplifier 80 or the clamper 110. Therefore, since the voltage loop characteristic does not change, the oscillation risk does not increase.

Further, in the case of the DC / DC converter 1 of the present embodiment, since the amplitude of the second voltage RAMP fluctuates depending on the input voltage Vi, the on-duty of the DC / DC converter 1 even when the input voltage Vi suddenly changes. It is possible to adjust the Don to an appropriate value and suppress the rush current.

<Fifth Embodiment>
FIG. 9 is a circuit diagram showing a fifth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the fourth embodiment (FIG. 7), and is included in the phase compensation resistor section 91 instead of dividing the capacitor included in the phase compensation capacitance section 92 into a plurality of capacitors. It is characterized by dividing the resistor into multiple parts. Therefore, the same components as those in the fourth embodiment are designated by the same reference numerals as those in FIG. 7, and duplicated explanations are omitted. Hereinafter, the characteristic portions of the fifth embodiment will be mainly described.

The phase compensation resistor unit 91 includes resistors R1 and R2. The first end of the resistor R1 is connected to the ground end. The first end of the resistor R2 is connected to the application end of the output voltage Vo. When the resistance value of the entire phase compensation resistance unit 91 is R, the resistance value of the resistance R1 is R1, and the resistance value of the resistance R2 is R2, R = R1 // R2 and R1 / R2 = k / (1-). k) (where 0 <k <1) is satisfied. As described above, in the phase compensation resistor portion 91 of the present embodiment, the phase compensation resistor is divided into two, and at least one ground side node (the first end of the resistor R2 in this figure) is DC. The output voltage Vo of the / DC converter 1 is applied as the monitoring target voltage.

The phase compensation capacitance unit 92 includes a capacitor whose first end is connected to the non-inverting input end (+) of the PWM comparator 60 and whose second end is connected to the second end of each of the resistors R1 and R2.

In the DC / DC converter 1 of the present embodiment, for example, when the switch output stage 10 is short-circuited and the output voltage Vo drops sharply, the first voltage VC is caused by the voltage dividing action of the resistors R1 and R2 to form an output feedback loop. Without waiting for a response, it drops sharply with the same behavior as the output voltage Vo. Therefore, the same effect as that of the fourth embodiment (FIG. 7) can be enjoyed.

In particular, in the present embodiment, the voltage dividing voltage of the output voltage Vo is applied to the capacitor of the phase compensation capacitance unit 92. Therefore, even when the output voltage Vo is relatively high, it is not necessary to unnecessarily increase the withstand voltage of the capacitor, which is suitable for integration into a semiconductor device.

<Sixth Embodiment>
FIG. 10 is a circuit diagram showing a sixth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the fourth embodiment (FIG. 7) and is characterized in that it has a function of shifting to the sleep mode in accordance with the above-mentioned first embodiment (FIG. 1). Has. Therefore, the same components as those in the fourth embodiment are designated by the same reference numerals as those in FIG. 7, and duplicated explanations are omitted. Hereinafter, the characteristic portions of the fifth embodiment will be mainly described.

With the introduction of the sleep mode, changes have been made to the error amplifier 30, the oscillator 50, the PWM comparator 60, the driver 70, the differential amplifier 80, and the second phase compensation circuit 90, respectively. The changes in each part will be described below.

The error amplifier 30, the oscillator 50, the PWM comparator 60, and the differential amplifier 80 are in the operating state when the sleep control signal XSLP is at a high level (= logical level when the sleep mode is released), and the sleep control signal XSLP is low. It is in a stopped state when it is at the level (= logical level in sleep mode).

The driver 70 includes a NAND gate 71 and an AND gate 72 instead of the inverters 75 and 76, and generates gate signals G1 and G2 according to the comparison signal CMP and the sleep control signal XSLP. Since the circuit configuration and operation are the same as those in the first embodiment (FIG. 1), duplicate explanations will be omitted.

The second phase compensation circuit 90 includes switches 93 to 95 in addition to the phase compensation resistor unit 91 and the phase compensation capacitance unit 92.

The switch 93 conducts / cuts off between the non-inverting input end (+) of the PWM comparator 60 and the output end of the differential amplifier 80 according to the sleep control signal XSLP. Specifically, the switch 93 is turned on when the sleep control signal XSLP is at a high level to conduct conduction between the non-inverting input end (+) of the PWM comparator 60 and the output end of the differential amplifier 80. When the sleep control signal XSLP is at a low level, it is turned off to cut off between the non-inverting input end (+) of the PWM comparator 60 and the output end of the differential amplifier 80.

The switch 94 conducts / cuts off between the second end and the ground end of the capacitor C4 according to the sleep control signal XSLP. Specifically, the switch 94 is turned on when the sleep control signal XSLP is at a low level to conduct between the second end and the ground end of the capacitor C4, and when the sleep control signal XSLP is at a high level. Turns off to cut off between the second end of the capacitor C4 and the ground end.

The switch 95 switches whether the second end of the capacitor C5 is connected to the application end of the output voltage Vo (corresponding to the monitored voltage) or to the ground end according to the sleep control signal XSLP. Specifically, the switch 95 connects the second end of the capacitor C5 to the ground end when the sleep control signal XSLP is low level, and the second end of the capacitor C5 when the sleep control signal XSLP is high level. Connect the end to the application end of the output voltage Vo.

In the second phase compensation circuit 90 having the above configuration, when the sleep mode is released (XSLP = H), the non-inverting input end (+) of the PWM comparator 60 and the output end of the differential amplifier 80 are conducted with each other. The second end of the capacitor C4 and the ground end are cut off, and the second end of the capacitor C5 is connected to the application end of the output voltage Vo.

That is, the phase compensation capacitance unit 92 is in a state in which the capacitors C4 and C5 are connected in series between the application end and the ground end of the output voltage Vo as the sleep mode is released. As a result, the first voltage VC quickly reaches VC = k × Vo (= {C4 / (C4 + C5)} × Vo) without waiting for the start of the differential amplifier 80 due to the capacitance voltage division of the capacitors C4 and C5. It will be pulled up. Therefore, as in the first embodiment (FIG. 1), the initial duty value at the time of releasing the sleep mode is set by using the second phase compensation circuit 90.

Further, after the sleep mode is released, the connection state of the phase compensation capacitance unit 92 is completely equivalent to that in FIG. 7. Therefore, as in the fourth embodiment (FIG. 7), the duty tracking control according to the transient fluctuation of the output voltage Vo can be realized by using the second phase compensation circuit 90, so that the switch output stage 10 is short-circuited. It is possible to effectively suppress the rush current generated at the time of abnormality.

As described above, the DC / DC converter 1 of the present embodiment can enjoy the effects of both the first embodiment (FIG. 1) and the fourth embodiment (FIG. 7).

<7th Embodiment>
FIG. 11 is a circuit diagram showing a seventh embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the sixth embodiment (FIG. 10), and is included in the phase compensation resistor section 91 instead of dividing the capacitor included in the phase compensation capacitance section 92 into a plurality of capacitors. It is characterized by dividing the resistor into multiple parts. Further, with this change, the second phase compensation circuit 90 is provided with switches 96 to 98 in place of the switches 94 and 95. Therefore, the same components as those in the sixth embodiment are designated by the same reference numerals as those in FIG. 10, and duplicated explanations will be omitted. Hereinafter, the characteristic portions of the seventh embodiment will be mainly described.

The phase compensation resistor unit 91 includes resistors R1 and R2. The first end of the resistor R1 is connected to the ground end. The first end of the resistor R2 is connected to the application end of the output voltage Vo via the switch 97. When the resistance value of the entire phase compensation resistance unit 91 is R, the resistance value of the resistance R1 is R1, and the resistance value of the resistance R2 is R2, then R = R1 // R2 and R1 / R2 = k / ( 1-k) (where 0 <k <1) is satisfied. This point is the same as that of the fifth embodiment (FIG. 9).

The phase compensation capacitance unit 92 includes a capacitor whose first end is connected to the non-inverting input end (+) of the PWM comparator 60 and whose second end is connected to the second end of each of the resistors R1 and R2.

The switch 96 conducts / cuts off between the second end of the resistor R1 and the ground end according to the sleep control signal XSLP. More specifically, the switch 96 is turned on when the sleep control signal XSLP is at a low level to conduct between the second end of the resistor R1 and the ground end, and the sleep control signal XSLP is at a high level. Sometimes it is turned off to cut off between the second end of the resistor R1 and the ground end.

The switch 97 conducts / cuts off between the second end of the resistor R2 and the application end of the output voltage Vo (= corresponding to the monitored voltage) according to the sleep control signal XSLP. More specifically, the switch 97 is turned off when the sleep control signal XSLP is at a low level to cut off between the second end of the resistor R2 and the application end of the output voltage Vo, and the sleep control signal XSLP is generated. When it is at a high level, it is turned on to conduct conduction between the second end of the resistor R2 and the application end of the output voltage Vo.

The switch 98 conducts / cuts off between the first end and the ground end of the phase compensation capacitance unit 92 according to the sleep control signal XSLP. More specifically, the switch 98 is turned on when the sleep control signal XSLP is at a low level to conduct conduction between the first end and the ground end of the phase compensation capacitance section 92, and the sleep control signal XSLP is high. When it is at the level, it is turned off to cut off between the first end of the phase compensation capacitance unit 92 and the ground end.

In the second phase compensation circuit 90 having the above configuration, when the sleep mode is released (XSLP = H), the non-inverting input end (+) of the PWM comparator 60 and the output end of the differential amplifier 80 are conducted with each other. , The space between the second end of the resistor R1 and the ground end, and the space between the first end of the phase compensation capacitance section 92 and the ground end are cut off, and the second end of the resistor R2 is the end where the output voltage Vo is applied. It will be connected to.

That is, the phase compensation resistor unit 91 is in a state in which resistors R1 and R2 are connected in series between the application end and the ground end of the output voltage Vo as the sleep mode is released. As a result, the first voltage VC quickly reaches VC = k × Vo (= {R1 / (R1 + R2)} × Vo) without waiting for the start of the differential amplifier 80 due to the resistance voltage division of the resistors R1 and R2. It will be pulled up. Therefore, as in the first embodiment (FIG. 1), the initial duty value at the time of releasing the sleep mode is set by using the second phase compensation circuit 90.

Further, after the sleep mode is released, the connection state of the phase compensation resistor unit 91 is completely equivalent to that in FIG. Therefore, as in the fifth embodiment (FIG. 9) above, the duty tracking control according to the transient fluctuation of the output voltage Vo can be realized by using the second phase compensation circuit 90, so that the switch output stage 10 is short-circuited. It is possible to effectively suppress the rush current generated at the time of abnormality.

In particular, in the present embodiment, the voltage dividing voltage of the output voltage Vo is applied to the capacitor of the phase compensation capacitance unit 92. Therefore, even when the output voltage Vo is relatively high, it is not necessary to unnecessarily increase the withstand voltage of the capacitor, which is suitable for integration into a semiconductor device.

As described above, the DC / DC converter 1 of the present embodiment can enjoy the effects of both the first embodiment (FIG. 1) and the fifth embodiment (FIG. 9).

<8th Embodiment>
FIG. 12 is a circuit diagram showing an eighth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the fourth embodiment (FIG. 7), and is characterized in that the current sense voltage CSNS is input back to the arithmetic unit 120 instead of the differential amplifier 80. Further, with this change, the second phase compensation circuit 90 is omitted, and its function is transferred to the phase compensation circuit 40. Therefore, with respect to the same components as those in the fourth embodiment, the same reference numerals as those in FIG. 7 are used to omit duplicated explanations, and the feature portions of the eighth embodiment will be mainly described below.

The phase compensation circuit 40 includes a phase compensation resistor unit 41 and a phase compensation capacitance unit 42, compensates the phase of the error voltage COMP, and prevents the oscillation of the output feedback loop.

The phase compensation capacitance section 42 includes capacitors C6 and C7. The first end of the capacitor C6 is connected to the ground end. On the other hand, the first end of the capacitor C7 is connected to the application end of the output voltage Vo. When the capacitance value of the entire phase compensation capacitance section 42 is C, the capacitance value of the capacitor C6 is C6, and the capacitance value of the capacitor C7 is C7, C = C6 + C7 and C7 / C6 = k / (1-k). (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitance section 42 of the present embodiment, the capacitor for phase compensation is divided into two, and at least one ground side node (the first end of the capacitor C7 in this figure) is DC. The output voltage Vo of the / DC converter 1 is applied as the monitoring target voltage.

The phase compensation resistor portion 41 includes a resistor whose first end is connected to the output end of the error amplifier 30 and whose second end is connected to the second end of each of the capacitors C6 and C7.

The arithmetic unit 120 generates a first voltage VC (= COMP-CSNS) by performing arithmetic processing of the error voltage COMP and the current sense voltage CSNS (for example, subtraction processing of subtracting the current sense voltage CSNS from the error voltage COMP). To do.

In this way, even when the current mode control method is realized by using the arithmetic unit 120, the phase compensation circuit 40 has a circuit configuration equivalent to that of FIG. 7, and is the same as that of the fourth embodiment (FIG. 7). It is possible to enjoy the effect of. Further, the phase compensation circuit 40 may have a circuit configuration equivalent to that shown in FIG.

<9th embodiment>
FIG. 13 is a circuit diagram showing a ninth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the eighth embodiment (FIG. 12), and is characterized in that the arithmetic unit 130 is used instead of the arithmetic unit 120. Therefore, with respect to the same components as those in the fourth embodiment, the same reference numerals as those in FIG. 7 are used to omit duplicated explanations, and the feature portions of the eighth embodiment will be mainly described below.

The arithmetic unit 130 performs arithmetic processing of the second voltage RAMP and the current sense voltage CSNS (for example, addition processing of adding the second voltage RAMP and the current sense voltage CSNS), thereby performing the third voltage RAMP'(= RAMP + CSNS). ) Is generated.

With the above change, the PWM comparator 60 compares the first voltage VC input to the non-inverting input end (+) with the third voltage RAMP'input to the inverting input terminal (-) to compare signals. Generate CMP.

In this way, even when the current mode control method is realized by using the arithmetic unit 130, the phase compensation circuit 40 has a circuit configuration equivalent to that of FIG. 7, and is the same as that of the fourth embodiment (FIG. 7). It is possible to enjoy the effect of. Further, the phase compensation circuit 40 may have a circuit configuration equivalent to that shown in FIG.

<10th Embodiment>
FIG. 14 is a circuit diagram showing a tenth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the fourth embodiment (FIG. 7), and is characterized in that the switch output stage 10 is changed from a step-down type to a step-up type. Therefore, with respect to the same components as those in the fourth embodiment, duplicate explanations will be omitted by assigning the same reference numerals as those in FIG. 7, and the feature portions of the tenth embodiment will be mainly described below.

The switch output stage 10 is a boost type that boosts the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 15 (NMOSFET in this figure), a synchronous rectifier transistor 16 (PMOSFET in this figure), and a coil. 17 and a capacitor 18 are included. Since the circuit configuration and operation are the same as those in the third embodiment (FIG. 5), duplicate explanations will be omitted.

Further, with the change of the switch output stage 10 from the step-down type to the step-up type, the oscillator 50, the PWM comparator 60, the driver 70, and the second phase compensation circuit 90 are also changed. The changes in each part will be described below.

In the oscillator 50, the amplitude of the second voltage RAMP is changed from a fluctuation value (= k × Vi) according to the input voltage Vi to a fluctuation value (= k × Vo) according to the output voltage Vo.

The input polarity of the PWM comparator 60 is reversed from that of the fourth to ninth embodiments. That is, the first voltage VC is input to the inverting input end (−) of the PWM comparator 60, and the second voltage RAMP is input to the non-inverting input end (+) of the PWM comparator 60. Therefore, the logic level of the comparison signal CMP becomes a low level when the first voltage VC is higher than the second voltage RAMP, and the first voltage VC is the second voltage RAMP, contrary to that of the fourth to ninth embodiments. Higher level when lower than.

The driver 70 includes buffers 77 and 78 instead of the inverters 75 and 76. The buffers 77 and 78 generate gate signals G3 and G4 having the same logic level as the comparison signal CMP, respectively. Therefore, when the comparison signal CMP is at a high level, both the gate signals G3 and G4 are at a high level, so that the output transistor 15 is turned on and the synchronous rectifying transistor 16 is turned off. On the contrary, when the comparison signal CMP is at a low level, both the gate signals G3 and G4 are at a low level, so that the output transistor 15 is turned off and the synchronous rectifier transistor 16 is turned on.

Further, in the second phase compensation circuit 90, the monitored voltage applied to the second end of the capacitor C5 is changed from the output voltage Vo to the input voltage Vi.

According to the DC / DC converter 1 of the present embodiment, the duty tracking control according to the transient fluctuation of the input voltage Vi can be realized by using the second phase compensation circuit 90. Therefore, even when the switch output stage 10 is a step-up type, it is possible to enjoy the effect of suppressing the rush current.

Further, in the case of the DC / DC converter 1 of the present embodiment, since the amplitude of the second voltage RAMP fluctuates depending on the output voltage Vo, the on-duty of the DC / DC converter 1 even when the output voltage Vo suddenly changes. It is possible to adjust the Don to an appropriate value and suppress the rush current.

<Other variants>
In addition to the above-described embodiment, various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. For example, mutual replacement between a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, it should be considered that the above embodiments are exemplary in all respects and are not restrictive, and the technical scope of the present invention is not the description of the above embodiments but the claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

The DC / DC converter disclosed in the present specification can be used as a power source means for various applications.

1 DC / DC converter 10 Switch output stage 11, 15 Output transistor 12, 16 Synchronous rectifier transistor 13, 17 Coil 14, 18 Capacitor 20 Feedback voltage generator 21, 22 Resistance 30 Error amplifier 40 Phase compensation circuit (1st phase compensation circuit) )
41 Phase Compensation Resistor 42 Phase Compensation Capacitor 43, 44, 45, 46 Switch 50 Oscillator 60 PWM Comparator 70 Driver 71 NAND Gate 72, 73 AND Gate 74 OR Gate 75, 76 Inverter 77, 78 Buffer 80 Differential Amplifier 90th 2 Phase Compensation Circuit 91 Phase Compensation Resistor 92 Phase Compensation Capacitor 93, 94, 95, 96, 97, 98 Switch 100 Current Detection 110 Clamper 120, 130 Comparator C1, C2, C3, C4, C5, C6, C7 Capacitors R1, R2 resistors

Claims (8)

A phase compensation circuit that compensates for the phase of the first voltage input to the PWM comparator of a DC / DC converter equipped with a sleep mode.
With the phase compensation resistor including the resistor;
With a phase compensation capacitance section containing multiple capacitors;
In the sleep mode, each capacitor is switched to the first connection state and at least one capacitor is charged with the first bias voltage, while when the sleep mode is released, each capacitor is switched to the second connection state and the first connection state is performed. With a group of switches that set the voltage to the desired initial value;
Have a,
The switch group switches the connection destination of at least one of the plurality of capacitors according to the sleep control signal.
The phase compensation capacitance section includes a first capacitor and a second capacitor, each of which has its first end connected to a grounded end, and the switch group is located between the second end of the first capacitor and the grounded end. A first switch that conducts / cuts off, and a second switch that switches whether the second end of the second capacitor is connected to the application end of the first bias voltage or the second end of the first capacitor. Including
The resistance is a phase compensation circuit characterized in that the first end is connected to the input end of the PWM comparator and the second end is connected to the second end of the first capacitor . When the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) (where 0 <k <1) is satisfied. the amplitude of the second voltage which is compared with the first voltage in the PWM comparator, phase compensation according to claim 1, characterized in that it is set to k times the DC / DC converter input voltage or the output voltage circuit. The phase compensation capacitance section further includes a third capacitor whose first end is connected to the grounded end.
The switch group is a third switch that switches whether the second end of the third capacitor is connected to an application end of a second bias voltage different from the first bias voltage or to the second end of the first capacitor. The phase compensation circuit according to claim 1 , further comprising. When the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and the capacitance value of the third capacitor is C3, C1: C2: C3 = {1- (k + k')}: k: k'(where 0 <k <1 and 0 <k'<1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is the DC / DC. The phase compensation circuit according to claim 3 , wherein the input voltage or the output voltage of the converter is set to k times. The phase compensation according to any one of claims 1 to 4, further comprising a switch that conducts / cuts off between the input end of the PWM comparator and the pre-stage circuit in response to the sleep control signal. circuit. A switch output stage that generates an output voltage from an input voltage,
An amplifier that generates an error signal according to the difference between the output voltage or the feedback voltage corresponding thereto and a predetermined reference voltage, and
A phase compensation circuit that receives the input of the error signal and generates a first voltage,
An oscillator that generates a second voltage for the ramp waveform,
A PWM comparator that compares the first voltage with the second voltage to generate a comparison signal,
A driver that generates a drive signal for the switch output stage in response to the comparison signal,
Have,
A DC / DC converter according to any one of claims 1 to 5 , wherein the phase compensation circuit according to any one of claims 1 to 5 is used as the phase compensation circuit. The sixth aspect of claim 6 , wherein the switch output stage is a step-down type, the first bias voltage is the output voltage, and the amplitude of the second voltage is a variable value corresponding to the input voltage. DC / DC converter. The sixth aspect of claim 6 , wherein the switch output stage is a step-up type, the first bias voltage is the input voltage, and the amplitude of the second voltage is a variable value corresponding to the output voltage. DC / DC converter.

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