JP2018107930A - Phase compensation circuit and dc/dc converter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a DC/DC converter.SOLUTION: A phase compensation circuit 40 that compensates a phase of a first voltage VC inputted to a PWM comparator 60 of a DC/DC converter 1 having a sleep mode, comprises: a phase compensation resistance part 41 that includes a resistor; a phase compensation capacitance part 42 that includes a plurality of capacitors (C1 and C2); and switch groups 44 and 45 that, in the sleep mode, switch each capacitor to a first connection state to charge at least one capacitor with a first bias voltage (e.g., an output voltage Vo), and at the release of the sleep mode, switch each capacitor to a second connection state to set the first voltage VC to a desired initial value (e.g., VC=k×Vo). In addition, the switch groups 44 and 45 switch at least one connection destination of a plurality of capacitors depending on a sleep control signal XSLP.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a phase compensation circuit and a DC / DC converter using the same.

  Conventionally, a DC / DC converter (so-called switching power supply) that generates a desired output voltage from an input voltage by turning on / off an output transistor has been used as a power supply means for various applications.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2008-61433 A

  FIG. 15 is a circuit diagram showing a first conventional example of a DC / DC converter. The DC / DC converter X1 of the conventional example turns off both the output transistor X11 and the synchronous rectification transistor X12 at light load (XSLP = L), and then the error amplifier X30, the oscillator X50, the PWM comparator X60, etc. The function of shifting to the sleep mode with low power consumption is provided.

  By the way, the on-duty Don of the DC / DC converter X1 (= the ratio of the on-period Ton of the output transistor X11 to the predetermined period T) is the difference between the first voltage VC and the second voltage RAMP respectively input to the PWM comparator X60. It depends on the comparison result. Therefore, if the error amplifier X30 that generates the first voltage VC is stopped when shifting to the sleep mode, until the error amplifier X30 is completely started when the sleep mode is canceled, the DC / DC converter X1 The on-duty Don becomes unstable.

  Therefore, the DC / DC converter X1 of the conventional example sets the first voltage VC to an appropriate bias value (= the initial value of the first voltage VC when the sleep mode is canceled) while the error amplifier X30 is stopped in the sleep mode. A bias portion X80 that is fixed to the equivalent).

  However, in the DC / DC converter X1 of this conventional example, since the bias unit X80 consumes power even in the sleep mode, there is room for further improvement in reducing power consumption.

  FIG. 16 is a circuit diagram showing a second conventional example of a DC / DC converter. The conventional DC / DC converter Y1 is a current mode control step-down switching power supply, and uses a clamper Y110 to limit the coil current IL of the switch output stage Y10 to an upper limit current value ILMT or less (so-called OCP [ over current protection] function).

  FIG. 17 is a COMP-IL characteristic diagram for explaining the OCP function by the clamper Y110. The horizontal axis represents the error voltage COMP generated by the error amplifier Y30, and the vertical axis represents the average value IL (ave) of the coil current IL.

  The clamper Y110 limits the error voltage COMP to the upper limit voltage value VLMT or less. As a result, in the differential amplifier Y80, output feedback control is performed so as to limit the current sense voltage CSNS corresponding to the coil current IL to the upper limit voltage value VLMT or less, and therefore the coil current IL is set to the upper limit current value ILMT or less. Limited.

  In order to suppress the rush current (= excessive coil current IL) generated when the switch output stage Y10 is short-circuited abnormally, the DC / DC converter Y1 is turned on following the sudden change in the output voltage Vo or the input voltage Vi. The duty Don (and hence the first voltage VC input from the differential amplifier Y80 to the PWM comparator Y60) needs to be abruptly changed. In order to meet this requirement, for example, it is conceivable to increase the response speed by increasing the drive current of the differential amplifier Y80 and the clamper Y110.

  However, if the response speeds of the differential amplifier Y80 and the clamper Y110 are increased carelessly, there is a problem that the voltage loop characteristics change and the oscillation risk increases.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in the present specification is a phase compensation circuit capable of reducing power consumption or suppressing rush current of a DC / DC converter, and An object of the present invention is to provide a DC / DC converter using the same.

  A phase compensation circuit disclosed in the present specification compensates the phase of a first voltage input to a PWM comparator of a DC / DC converter having a sleep mode, and includes a phase compensation resistor unit including a resistor A phase compensation capacitor including a plurality of capacitors; in the sleep mode, each capacitor is switched to a first connection state and at least one capacitor is charged with a first bias voltage, while at the time of canceling the sleep mode, A switch group that switches each capacitor to the second connection state and sets the first voltage to a desired initial value (first configuration).

  In the phase compensation circuit having the first configuration, the switch group may be configured to switch at least one connection destination of the plurality of capacitors according to a sleep control signal (second configuration).

  Further, in the phase compensation circuit having the second configuration, the phase compensation capacitance unit includes a first capacitor and a second capacitor each having a first terminal connected to a ground terminal, and the switch group includes the first capacitor A first switch that conducts / cuts off between a second end of the capacitor and the ground end; and a second end of the second capacitor is connected to an application end of the first bias voltage or a second switch of the first capacitor. It is good to make it the structure (3rd structure) containing the 2nd switch which switches whether it connects to an end.

  In the phase compensation circuit having the third configuration, when the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) (where 0 <k <1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage (fourth) (Configuration).

  In the phase compensation circuit having the third configuration, the phase compensation capacitance unit further includes a third capacitor having a first terminal connected to the ground terminal, and the switch group includes a second capacitor of the third capacitor. When the configuration further includes a third switch (fifth configuration) for switching whether the end is connected to an application end of a second bias voltage different from the first bias voltage or to the second end of the first capacitor. Good.

  In the phase compensation circuit having the fifth configuration, when the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and the capacitance value of the third capacitor is C3, C1 : C2: C3 = {1- (k + k ′)}: k: k ′ (where 0 <k <1, and 0 <k ′ <1) are satisfied, and the PWM comparator compares the first voltage with the first voltage. The amplitude of the second voltage to be compared may be configured to be set to k times the input voltage or the output voltage (sixth configuration).

  In the phase compensation circuit having any one of the third to sixth configurations, the resistor has a first end connected to the input end of the PWM comparator, and a second end connected to the second end of the first capacitor. (7th configuration).

  Further, when the phase compensation circuit having the seventh configuration has a configuration (eighth configuration) further including a switch for conducting / cutting off between the input terminal of the PWM comparator and the preceding circuit according to the sleep control signal. Good.

  Further, the DC / DC converter disclosed in this specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier that generates an error signal, a phase compensation circuit that receives the input of the error signal and generates a first voltage, an oscillator that generates a second voltage having a ramp waveform, the first voltage and the second voltage, A PWM comparator that generates a comparison signal and a driver that generates a drive signal for the switch output stage according to the comparison signal. A configuration in which a phase compensation circuit having the configuration is used (a ninth configuration) may be used.

  In the DC / DC converter having the ninth configuration, the switch output stage is a step-down type, the first bias voltage is the output voltage, and the amplitude of the second voltage varies according to the input voltage. It is good to set it as the structure (10th structure) which is a value.

  In the DC / DC converter having the ninth configuration, the switch output stage is a step-up type, the first bias voltage is the input voltage, and the amplitude of the second voltage varies according to the output voltage. You may make it the structure (11th structure) which is a value.

  The phase compensation circuit disclosed in the present specification compensates the phase of the first voltage input to the PWM comparator of the DC / DC converter that employs the current mode control method, and includes a phase compensation resistor. A phase compensation capacitor unit, and one of the phase compensation resistor unit and the phase compensation capacitor unit includes a plurality of resistors or a plurality of capacitors, and the plurality of resistors or the plurality of capacitors, The output voltage or the input voltage of the DC / DC converter is applied to at least one ground side node as a monitoring target voltage (a twelfth configuration).

  In the phase compensation circuit having the twelfth configuration, the phase compensation capacitor unit includes a first capacitor having a first end connected to a ground terminal and a first end connected to an application terminal for the monitoring target voltage. The phase compensation resistor unit includes a resistor having a first end connected to an input end of the PWM comparator and a second end connected to a second end of each capacitor (a thirteenth configuration). (Configuration).

  In the phase compensation circuit having the thirteenth configuration, when the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) ( However, 0 <k <1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage (first 14 configuration).

  In the phase compensation circuit having the twelfth configuration, the phase compensation resistor unit includes a first resistor having a first terminal connected to the ground terminal, and a first terminal connected to the application terminal for the monitoring target voltage. The phase compensation capacitance unit includes a capacitor having a first end connected to the input end of the PWM comparator and a second end connected to the second end of each resistor (fifteenth). (Configuration).

  In the phase compensation circuit having the fifteenth configuration, when the resistance value of the first resistor is R1 and the resistance value of the second resistor is R2, R1 / R2 = k / (1-k) (however, 0 <k <1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage (the sixteenth) (Configuration).

  In addition, the phase compensation circuit having the thirteenth or fourteenth configuration is a means for switching the connection state of each capacitor in accordance with the sleep control signal, between the second end of the first capacitor and the ground end. A first switch that cuts off, and a second switch that switches between connecting the first terminal of the second capacitor to the application terminal of the monitoring target voltage or the ground terminal (a seventeenth structure) ).

  In addition, the phase compensation circuit having the fifteenth or sixteenth configuration is a means for switching the connection state of each resistor in accordance with the sleep control signal, and connecting / disconnecting between the second end of the first resistor and the ground end. A first switch that cuts off, a second switch that conducts / cuts off between the first end of the second resistor and the application end of the monitoring target voltage, and between the first end of the capacitor and the ground end. It is preferable to have a configuration (18th configuration) further including a third switch for conducting / interrupting.

  In addition, the phase compensation circuit having the seventeenth or eighteenth configuration further includes a switch for connecting / shutting off between the input terminal of the PWM comparator and the preceding circuit in accordance with the sleep control signal (a nineteenth configuration). ).

  Further, the DC / DC converter disclosed in this specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. A first amplifier for generating a first error signal, a first phase compensation circuit for receiving an input of the first error signal and generating an error voltage, and a clamper for limiting the error voltage to a predetermined upper limit voltage value or less. A current detection unit that generates a current sense voltage according to a coil current of the switch output stage; a second amplifier that generates a second error signal according to a difference between the error voltage and the current sense voltage; (2) a second phase compensation circuit for receiving a first error signal and outputting a first voltage; an oscillator for generating a second voltage having a ramp waveform; and comparing the first voltage and the second voltage to obtain a comparison signal. PW to be generated A comparator that generates a drive signal for the switch output stage in response to the comparison signal, and the phase compensation circuit having any of the twelfth to nineteenth configurations is used as the second phase compensation circuit. It is set as the structure (20th structure).

  Further, the DC / DC converter disclosed in this specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier for generating an error signal, a phase compensation circuit for generating an error voltage upon receiving the error signal, a clamper for limiting the error voltage to a predetermined upper limit voltage value or less, and a coil current of the switch output stage A current detection unit that generates a current sense voltage corresponding to the current voltage, a calculator that generates a first voltage by a calculation process of the error voltage and the current sense voltage, an oscillator that generates a second voltage of a ramp waveform, A PWM comparator that compares the first voltage with the second voltage to generate a comparison signal; and a driver that generates a drive signal for the switch output stage according to the comparison signal. And, wherein the phase compensation circuit, there is a twelfth 19 configuration phase compensation circuit is used consisting of any one of the configurations (configuration of the 21).

  Further, the DC / DC converter disclosed in this specification corresponds to a switch output stage that generates an output voltage from an input voltage, and a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. An amplifier that generates an error signal, a phase compensation circuit that receives the error signal and generates a first voltage, a clamper that limits the first voltage to a predetermined upper limit voltage value, and a switch output stage. A current detection unit for generating a current sense voltage corresponding to the coil current; an oscillator for generating a second voltage having a ramp waveform; and a calculator for generating a third voltage by an arithmetic process of the second voltage and the current sense voltage. A PWM comparator that compares the first voltage with the third voltage to generate a comparison signal, and a driver that generates a drive signal for the switch output stage according to the comparison signal. And, wherein the phase compensation circuit, there is a twelfth 19 configuration phase compensation circuit is used consisting of any one of the configurations (configuration of the 22).

  Note that in the DC / DC converter having any one of the twentieth to twenty-second configurations, the switch output stage is a step-down type, the monitoring target voltage is the output voltage, and the amplitude of the second voltage is the input voltage. It is preferable to adopt a configuration (a twenty-third configuration) having a variation value according to the above.

  In the DC / DC converter having any one of the twentieth to twenty-second configurations, the switch output stage is a step-up type, the monitored voltage is the input voltage, and the amplitude of the second voltage is the output voltage. It is also possible to adopt a configuration (24th configuration) with a variation value according to the above.

  According to the invention disclosed in the present specification, it is possible to provide a phase compensation circuit capable of realizing power consumption reduction or rush current suppression of a DC / DC converter, and a DC / DC converter using the same. Is possible.

Circuit diagram showing a first embodiment of a DC / DC converter Timing chart showing duty initial value setting operation in the first embodiment Circuit diagram showing a second embodiment of a DC / DC converter Timing chart showing duty initial value setting operation in the second embodiment Circuit diagram showing a third embodiment of a DC / DC converter Timing chart showing duty initial value setting operation in the third embodiment Circuit diagram showing a fourth embodiment of a DC / DC converter Timing chart showing rush current suppression operation in the fourth embodiment Circuit diagram showing a fifth embodiment of a DC / DC converter Circuit diagram showing a sixth embodiment of a DC / DC converter Circuit diagram showing a seventh embodiment of a DC / DC converter Circuit diagram showing an eighth embodiment of a DC / DC converter Circuit diagram showing a ninth embodiment of a DC / DC converter Circuit diagram showing a tenth embodiment of a DC / DC converter Circuit diagram showing a first conventional example of a DC / DC converter Circuit diagram showing a second conventional example of a DC / DC converter COMP-IL characteristic diagram for explaining OCP function by clamper

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a DC / DC converter. The DC / DC converter 1 according to this embodiment generates a voltage Vo from an input voltage Vi and supplies it to a load (not shown) such as a CPU (central processing unit). It is a power supply, and includes a switch output stage 10, a feedback voltage generation unit 20, an error amplifier 30, a phase compensation circuit 40, an oscillator 50, a PWM comparator 60, and a driver 70.

  In addition to the circuit elements described above, the DC / DC converter 1 may incorporate other protection circuits (such as a voltage drop protection circuit, an overvoltage protection circuit, an overcurrent protection circuit, and a temperature protection circuit) as appropriate.

  The switch output stage 10 is a step-down type that steps down the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 11 (PMOSFET (P channel type metal oxide semiconductor field effect transistor) in this figure) and synchronous rectification. The transistor 12 (NMOSFET [N channel type MOSFET] in this figure), the coil 13, and the capacitor 14 are included.

  The source of the output transistor 11 is connected to the application terminal for the input voltage Vi. The drain of the output transistor 11 is connected to the first end of the coil 13. The gate of the output transistor 11 is connected to the application terminal of the gate signal G1. The output transistor 11 is turned off when the gate signal G1 is at a high level, and turned on when the gate signal G1 is at a low level.

  The source of the synchronous rectification transistor 12 is connected to the ground terminal (= application terminal of the ground voltage GND). The drain of the synchronous rectification transistor 12 is connected to the first end of the coil 13. The gate of the synchronous rectification transistor 12 is connected to the application terminal of the gate signal G2. The synchronous rectification transistor 12 is turned on when the gate signal G2 is at a high level, and is turned off when the gate signal G2 is at a low level.

  When a high voltage is applied to the switch output stage 10, a high voltage device such as a power MOSFET, IGBT (insulated gate bipolar transistor), or SiC transistor is used as the output transistor 11 or the synchronous rectification transistor 12, respectively. Good.

  The output transistor 11 and the synchronous rectification transistor 12 are turned on / off complementarily according to the gate signals G1 and G2. By such an on / off operation, a rectangular wave switch voltage Vsw that is pulse-driven between the input voltage Vi and the ground voltage GND is generated at the first end of the coil 13. The term “complementary” is not limited to the case where the on / off states of the output transistor 11 and the synchronous rectification transistor 12 are completely reversed, but also includes a simultaneous off period (dead time) of both transistors. This includes cases where

  The coil 13 and the capacitor 14 form an LC filter that rectifies and smoothes the switch voltage Vsw to generate the output voltage Vo. As described above, the first end of the coil 13 is connected to the drains of the output transistor 11 and the synchronous rectification transistor 12 (= application terminal of the switch voltage Vsw). The second end of the coil 13 and the first end of the capacitor 14 are both connected to the application end of the output voltage Vo. The second end of the capacitor 14 is connected to the ground end.

  The feedback voltage generator 20 includes resistors 21 and 22 connected in series between the application terminal of the output voltage Vo and the ground terminal, and a feedback voltage Vfb (output voltage) corresponding to the output voltage Vo from a connection node between the two resistors. Vo divided voltage) is output. When the output voltage Vo is within the input dynamic range of the error amplifier 30, the feedback voltage generator 20 may be omitted and the output voltage Vo may be directly input to the error amplifier 30.

  The error amplifier 30 is a current output type transconductance amplifier (so-called gm amplifier), and is a feedback voltage Vfb applied to the inverting input terminal (−) and a reference voltage Vref applied to the non-inverting input terminal (+). An error current signal I30 corresponding to the difference is generated. The error current signal I30 flows in the positive direction (= direction toward the phase compensation circuit 40 from the error amplifier 30) when the feedback voltage Vfb is lower than the reference voltage Vref, and in the negative direction when the feedback voltage Vfb is higher than the reference voltage Vref. = Flowing from the phase compensation circuit 40 toward the error amplifier 30). The error amplifier 30 is in an operating state when the sleep control signal XSLP is at a high level (= logic level when the sleep mode is canceled), and the sleep control signal XSLP is at a low level (= logic level when in the sleep mode). Sometimes it is stopped.

  The phase compensation circuit 40 is connected between the error amplifier 30 and the PWM comparator 60, and receives the error current signal I30 and generates the first voltage VC. The configuration and operation of the phase compensation circuit 40 will be described later.

  The oscillator 50 generates a second voltage RAMP having a ramp waveform (= triangular waveform, sawtooth waveform, or nth-order slope waveform (eg, n = 2)) that is pulse-driven at a predetermined switching frequency fsw (= 1 / T). Generate. In the oscillator 50, the amplitude of the second voltage RAMP is set to a fluctuation value (= k × Vi) corresponding to the input voltage Vi. Therefore, the amplitude of the second voltage RAMP increases as the input voltage Vi increases, and decreases as the input voltage Vi decreases. The technical significance thereof will be described later. The oscillator 50 is in an operating state when the sleep control signal XSLP is at a high level, and is in a stopped state when the sleep control signal XSLP is at a low level, like the error amplifier 30 described above.

  The PWM comparator 60 compares the first voltage VC applied to the non-inverting input terminal (+) and the second voltage RAMP applied to the inverting input terminal (−) to generate a comparison signal CMP. The comparison signal CMP is at a high level when the first voltage VC is higher than the second voltage RAMP, and is at a low level when the first voltage VC is lower than the second voltage RAMP. The PWM comparator 60 is in an operating state when the sleep control signal XSLP is at a high level, and is in a stopped state when the sleep control signal XSLP is at a low level, like the error amplifier 30 and the oscillator 50 described above.

  The driver 70 includes a NAND gate 71 and an AND gate 72, and generates gate signals G1 and G2 (= corresponding to drive signals for the switch output stage 10) according to the comparison signal CMP. More specifically, the NAND gate 71 outputs a NAND operation signal of the sleep control signal XSLP and the comparison signal CMP as the gate signal G1. Further, the AND gate 72 outputs a logical product operation signal of the sleep control signal XSLP and the comparison signal CMP that is inverted and inputted as the gate signal G2.

  Therefore, when the sleep control signal XSLP is at a high level, the gate signals G1 and G2 are basically logical inversion signals of the comparison signal CMP. More specifically, when the comparison signal CMP is at a high level, the gate signals G1 and G2 are both at a low level, so that the output transistor 11 is turned on and the synchronous rectification transistor 12 is turned off. Conversely, when the comparison signal CMP is at a low level, both the gate signals G1 and G2 are at a high level, so that the output transistor 11 is turned off and the synchronous rectification transistor 12 is turned on.

  On the other hand, when the sleep control signal XSLP is at low level, the gate signal G1 is at high level without depending on the comparison signal CMP, and the gate signal G2 is at low level without depending on the comparison signal CMP. Therefore, both the output transistor 11 and the synchronous rectification transistor 12 are turned off.

  As described above, when the sleep control signal XSLP is at the low level, the DC / DC converter 1 of the present embodiment turns off the output transistor 11 and the synchronous rectification transistor 12, and then the error amplifier 30, the oscillator 50, Also, a function of shifting to a sleep mode with low power consumption is provided by stopping the PWM comparator 60 and the like.

  Note that the sleep control signal XSLP is preferably at a low level when the light load state (or no load state) is reached. As a method for detecting the light load state described above, for example, a method of detecting a reverse flow of the coil current IL (= zero cross detection of the switch voltage Vsw) is conceivable.

<Phase compensation circuit>
Next, the configuration and operation of the phase compensation circuit 40 will be described in detail with reference to FIG. The phase compensation circuit 40 in this figure includes a phase compensation resistor unit 41, a phase compensation capacitor unit 42, and switches 43 to 45, and compensates the phase of the first voltage VC to prevent oscillation of the output feedback loop.

  The phase compensation capacitance unit 42 includes capacitors C1 and C2. The first ends of the capacitors C1 and C2 are connected to the ground end. When the capacitance value of the entire phase compensation capacitor 42 is C, the capacitance value of the capacitor C1 is C1, and the capacitance value of the capacitor C2 is C2, C = C1 + C2, C2 / C1 = k / (1-k) (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitor unit 42 of the present embodiment, the phase compensation capacitor is divided into two, and the technical significance thereof will be described later.

  The phase compensation resistor unit 41 includes a resistor having a first end connected to the non-inverting input end (+) of the PWM comparator 60 and a second end connected to the second end of the capacitor C1.

  The switch 43 conducts / cuts off between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 according to the sleep control signal XSLP. More specifically, the switch 43 is turned on when the sleep control signal XSLP is at a high level, and conducts between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 to sleep. When the control signal XSLP is at a low level, it is turned off to cut off between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30.

  The switch 44 conducts / cuts off between the second end of the capacitor C1 and the ground end in accordance with the sleep control signal XSLP. Specifically, the switch 44 is turned on when the sleep control signal XSLP is at a low level, and conducts between the second end of the capacitor C1 and the ground terminal, and when the sleep control signal XSLP is at a high level. To turn off the second terminal of the capacitor C1 and the ground terminal.

  The switch 45 switches whether the second end of the capacitor C2 is connected to the application end of the output voltage Vo (= corresponding to the first bias voltage) or the second end of the capacitor C1 according to the sleep control signal XSLP. More specifically, the switch 45 connects the second terminal of the capacitor C2 to the application terminal of the output voltage Vo when the sleep control signal XSLP is at a low level, and switches the capacitor 45 when the sleep control signal XSLP is at a high level. The second end of C2 is connected to the second end of capacitor C1.

  Thus, the switches 44 and 45 switch the connection destinations of the capacitors C1 and C2 according to the sleep control signal XSLP, thereby switching the capacitors C1 and C2 to the first connection state in the sleep mode (XSLP = L). While both ends of the capacitor C2 are charged with the output voltage Vo, when the sleep mode is canceled (XSLP = H), the capacitors C1 and C2 are switched to the second connection state and the first voltage VC is set to a desired initial value ( = K × Vo) functions as a set of switches.

  In the first connection state, the switch 44 is electrically connected between the second end of the capacitor C1 and the ground end, and the switch 45 connects the second end of the capacitor C2 to the application end of the output voltage Vo. Refers to the state of On the other hand, in the second connection state, the switch 44 cuts off the connection between the second end of the capacitor C1 and the ground end, and the switch 45 connects the second end of the capacitor C2 to the second end of the capacitor C1. Refers to the state of

  Next, the duty initial value setting operation when the sleep mode is released in the first embodiment will be described in detail with reference to FIG.

  FIG. 2 is a timing chart showing an example of the duty initial value setting operation in the first embodiment. From the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and A comparison signal CMP is depicted.

  Prior to time t11, the sleep control signal XSLP is at a low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are blocked, and the second terminal of the capacitor C1 and the ground terminal are electrically connected. Thus, the second end of the capacitor C2 is connected to the application end of the output voltage Vo. Therefore, both ends of the capacitor C1 are discharged, and both ends of the capacitor C2 are charged with the output voltage Vo. In the sleep mode, both the first voltage VC and the second voltage RAMP are 0V, and the comparison signal CMP is at a low level.

  When the sleep control signal XSLP is raised to a high level at time t11, the DC / DC converter 1 returns to the wake-up mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are electrically connected, and the second terminal of the capacitor C1 and the ground terminal are disconnected. Thus, the second end of the capacitor C2 is connected to the second end of the capacitor C1.

  That is, the phase compensation capacitor unit 42 is in a state in which the capacitor C1 discharged between both ends thereof and the capacitor C2 charged between the both ends with the output voltage Vo are connected in parallel with the release of the sleep mode.

  As a result, the first voltage VC promptly reaches VC = k × Vo (= {C2 / (C1 + C2)} × Vo) in accordance with the charge distribution rule between the capacitors C1 and C2, without waiting for the error amplifier 30 to start. To be raised.

  Further, since the oscillator 50 is in an operating state after time t11, a ramp voltage second voltage RAMP that is pulse-driven at the switching frequency fsw (= 1 / T) is generated. Note that the amplitude of the second voltage RAMP is a variation value (= k × Vi) corresponding to the input voltage Vi as described above.

  Here, the on-duty Don (= Ton / T) of the DC / DC converter 1 is determined according to the comparison result between the first voltage VC and the second voltage RAMP. Specifically, from the timing when the first voltage VC (= k × Vo) and the second voltage RAMP (= (k × Vi / T) × Ton) coincide with each other, the on-duty Don (= duty at the time of canceling the sleep mode). (Corresponding to the initial value) is Vo / Vi. This initial duty value coincides with a theoretical duty value when the input voltage Vi is stepped down to generate a desired output voltage Vo. Therefore, overshoot and undershoot of the output voltage Vo when the sleep mode is canceled can be prevented.

  Note that, if the configuration is such that the duty initial value when the sleep mode is canceled using the phase compensation circuit 40, unlike the DC / DC converter X1 of FIG. 15, it is not necessary to move the bias unit X80 in the sleep mode. The power consumption can be greatly reduced.

  Further, since the capacitor C2 stops flowing current after the completion of charging, the power consumption of the phase compensation circuit 40 in the sleep mode is zero.

  Furthermore, in the case of the DC / DC converter 1 of the present embodiment, the duty initial value when the sleep mode is canceled can be set by switching the switches 43 to 45 of the phase compensation circuit 40. Therefore, the DC / DC converter 1 It is possible to ideally reduce the restart time (= restoration time) to zero.

Second Embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is characterized in that it further includes a capacitor C3 and a switch 46 as components of the phase compensation circuit 40, while being based on the first embodiment (FIG. 1). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The capacitor C3, like the capacitors C1 and C2, is a constituent element of the phase compensation capacitance unit 42, and the first end thereof is connected to the ground end. When the capacitance value of the entire phase compensation capacitor 42 is C, the capacitance value of the capacitor C1 is C1, the capacitance value of the capacitor C2 is C2, and the capacitance value of the capacitor C3 is C3, C = C1 + C2 + C3, C1 : C2: C3 = {1- (k + k ′)}: k: k ′ (where 0 <k <1 and 0 <k ′ <1) are satisfied. As described above, in the phase compensation capacitor unit 42 of the present embodiment, the phase compensation capacitor is divided into three, and the technical significance thereof will be described later.

  Similarly to the switches 44 and 45, the switch 46 is a component of a switch group that switches the connection state of the capacitors C1 to C3 according to the sleep control signal XSLP, and the second end of the capacitor C3 is connected to the input voltage Vi (= first bias). Switching to the application terminal of the second bias voltage different from the voltage) or to the second terminal of the capacitor C1. Specifically, the switch 46 connects the second terminal of the capacitor C3 to the application terminal of the input voltage Vi when the sleep control signal XSLP is at a low level, and the capacitor 46 when the sleep control signal XSLP is at a high level. The second end of C3 is connected to the second end of capacitor C1.

  Next, the duty initial value setting operation when the sleep mode is released in the second embodiment will be described in detail with reference to FIG.

  FIG. 4 is a timing chart showing an example of the duty initial value setting operation in the second embodiment. In order from the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and A comparison signal CMP is depicted.

  Prior to time t21, the sleep control signal XSLP is at a low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are blocked, and the second terminal of the capacitor C1 and the ground terminal are electrically connected. Thus, the second end of the capacitor C2 is connected to the application end of the output voltage Vo, and the second end of the capacitor C3 is connected to the application end of the input voltage Vi. Therefore, both ends of the capacitor C1 are discharged, both ends of the capacitor C2 are charged with the output voltage Vo, and both ends of the capacitor C3 are charged with the input voltage Vi. In the sleep mode, both the first voltage VC and the second voltage RAMP are 0V, and the comparison signal CMP is at a low level.

  When the sleep control signal XSLP is raised to a high level at time t21, the DC / DC converter 1 returns to the wake-up mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are conducted, and the second terminal of the capacitor C1 and the ground terminal are blocked. The second ends of the capacitors C2 and C3 are both connected to the second end of the capacitor C1.

  That is, the phase compensation capacitor 42 is connected in parallel with the capacitor C1 that is discharged between both ends in response to the release of the sleep mode and the capacitors C2 and C3 that are charged between the both ends with the output voltage Vo and the input voltage Vi. It will be in the state.

  As a result, the first voltage VC follows the charge distribution rule between the capacitors C1 to C3, and without waiting for the error amplifier 30 to start up, VC = k × Vo + k ′ × Vi (= (C2 × Vo + C3 × Vi) / ( C1 + C2 + C3)}). That is, in the present embodiment, the initial value of the first voltage VC when the sleep mode is canceled is offset higher by k ′ × Vi than in the first embodiment.

  Further, since the oscillator 50 is in an operating state after the time t21, the ramp voltage second voltage RAMP that is pulse-driven at the switching frequency fsw (= 1 / T) is generated. Note that the amplitude of the second voltage RAMP is a variation value (= k × Vi) corresponding to the input voltage Vi as described above.

  Accordingly, the on-duty Don (= corresponding to the initial duty value) when the sleep mode is canceled is (Vo / Vi) + (k ′ / k). That is, the duty initial value in the present embodiment is a value that is intentionally higher than the theoretical duty value (= Vo / Vi) when the input voltage Vi is stepped down to generate the desired output voltage Vo.

  Note that the first voltage VC decreases until VC = k × Vo due to the function of the output feedback loop. That is, the on-duty Don of the DC / DC converter 1 converges to the above-described theoretical duty value (= Vo / Vi) as time passes.

  As described above, the number of capacitor divisions in the phase compensation capacitance unit 42 is set to 3 or more, and each capacitor is charged with a different bias voltage. The initial value of VC can be adjusted arbitrarily. Therefore, for example, the duty initial value when the sleep mode is canceled can be optimized in consideration of the output loop characteristics of the DC / DC converter 1, so that overshoot and undershoot of the output voltage Vo can be more appropriately prevented. It becomes possible.

  In particular, by using the existing output voltage Vo and input voltage Vi for the DC / DC converter 1 as the bias voltage for charging the capacitors C2 and C3, it is not necessary to prepare a separate bias voltage. However, if it is not desired to increase the number of divisions of the capacitor, the present embodiment is obtained by charging the capacitor C2 with an arbitrary bias voltage (= Vo + α) higher than the output voltage Vo in the first embodiment (FIG. 1). It is possible to achieve the same effect as.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is characterized in that the switch output stage 10 is changed from a step-down type to a step-up type while being based on the first embodiment (FIG. 1). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, the characteristic portions of the third embodiment are mainly described.

  The switch output stage 10 is a boost type that boosts the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 15 (NMOSFET in this figure), a synchronous rectification transistor 16 (PMOSFET in this figure), a coil 17 and the capacitor 18 are included.

  The first end of the coil 17 is connected to the input end of the input voltage Vi. The second end of the coil 17 is connected to the drain of the output transistor 15 and the drain of the synchronous rectification transistor 16. The source of the output transistor 15 is connected to the ground terminal. Both the source of the synchronous rectification transistor 16 and the first end of the capacitor 18 are connected to the application end of the output voltage Vo. The second end of the capacitor 18 is connected to the ground end.

  The gate of the output transistor 15 is connected to the application terminal of the gate signal G3. The output transistor 15 is turned on when the gate signal G3 is at a high level and turned off when the gate signal G4 is at a low level. The gate of the synchronous rectification transistor 16 is connected to the application terminal of the gate signal G4. The synchronous rectification transistor 16 is turned off when the gate signal G4 is at a high level, and turned on when the gate signal G4 is at a low level.

  The output transistor 15 and the synchronous rectification transistor 16 are complementarily turned on / off according to the gate signals G3 and G4. By such an on / off operation, a rectangular wave switch voltage Vsw that is pulse-driven between the input voltage Vi and the ground voltage GND is generated at the second end of the coil 17. The term “complementary” is not limited to the case where the on / off states of the output transistor 15 and the synchronous rectification transistor 16 are completely reversed, and a simultaneous off period (dead time) of both transistors is provided. This includes cases where

  When the output transistor 15 is turned on and the synchronous rectification transistor 16 is turned off, the coil current IL flows to the coil 17 via the output transistor 15 and the electrical energy is stored. At this time, the switch voltage Vsw decreases to the ground voltage GND through the output transistor 15. Since the synchronous rectification transistor 16 is turned off, no current flows from the capacitor 18 toward the output transistor 15.

  On the other hand, when the output transistor 15 is turned off and the synchronous rectification transistor 16 is turned on, the electrical energy stored therein is released as a current by the back electromotive force generated in the coil 17. At this time, the coil current IL flowing through the synchronous rectification transistor 16 flows from the output terminal of the output voltage Vo to the load as an output current, and also flows to the ground terminal through the capacitor 18, and the capacitor 18 is charged. By repeating the above operation, the output voltage Vo obtained by boosting the input voltage Vi is supplied to the load.

  When a high voltage is applied to the switch output stage 10, high voltage elements such as power MOSFETs, IGBTs, and SiC transistors may be used as the output transistor 15 and the synchronous rectification transistor 16, respectively. This is the same as in the first to third embodiments.

  Further, as the switch output stage 10 is changed from the step-down type to the step-up type, the phase compensation circuit 40, the oscillator 50, the PWM comparator 60, and the driver 70 are also changed. Below, the change of each part is demonstrated.

  In the phase compensation circuit 40, the bias voltage for charging the capacitor C2 is changed from the output voltage Vo to the input voltage Vi.

  In the oscillator 50, the amplitude of the second voltage RAMP is changed from a fluctuation value (= k × Vi) corresponding to the input voltage Vi to a fluctuation value (= k × Vo) corresponding to the output voltage Vo.

  The input polarity of the PWM comparator 60 is inverted from that of the first to third embodiments. That is, the first voltage VC is input to the inverting input terminal (−) of the PWM comparator 60, and the second voltage RAMP is input to the non-inverting input terminal (+) of the PWM comparator 60. Accordingly, the logical level of the comparison signal CMP is low when the first voltage VC is higher than the second voltage RAMP, contrary to that of the first to third embodiments, and the first voltage VC becomes the second voltage RAMP. High level when lower than

  The driver 70 includes an AND gate 73 and an OR gate 74 instead of the NAND gate 71 and the AND gate 72, and gate signals G3 and G4 (= corresponding to drive signals for the switch output stage 10 respectively) according to the comparison signal CMP. ) Is generated. More specifically, the AND gate 73 outputs a logical product operation signal of the sleep control signal XSLP and the comparison signal CMP as the gate signal G3. The OR gate 74 outputs a logical sum operation signal of the comparison signal CMP and the sleep control signal XSLP input in an inverted manner as the gate signal G4.

  Therefore, when the sleep control signal XSLP is at a high level, the gate signals G3 and G4 are basically the same logic signal as the comparison signal CMP. More specifically, when the comparison signal CMP is at a high level, the gate signals G3 and G4 are both at a high level, so that the output transistor 15 is turned on and the synchronous rectification transistor 16 is turned off. Conversely, when the comparison signal CMP is at a low level, the gate signals G3 and G4 are both at a low level, so that the output transistor 15 is turned off and the synchronous rectification transistor 16 is turned on.

  On the other hand, when the sleep control signal XSLP is at a low level, the gate signal G3 is at a low level without depending on the comparison signal CMP, and the gate signal G4 is at a high level without depending on the comparison signal CMP. Accordingly, both the output transistor 15 and the synchronous rectification transistor 16 are turned off.

  FIG. 6 is a timing chart showing an example of the duty initial value setting operation in the third embodiment. From the top, the sleep control signal XSLP, the first voltage VC (solid line), the second voltage RAMP (broken line), and A comparison signal CMP is depicted.

  Prior to time t31, the sleep control signal XSLP is at the low level, and the DC / DC converter 1 is shifted to the power saving sleep mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are blocked, and the second terminal of the capacitor C1 and the ground terminal are electrically connected. Thus, the second end of the capacitor C2 is connected to the application end of the output voltage Vo. Therefore, both ends of the capacitor C1 are discharged, and both ends of the capacitor C2 are charged with the input voltage Vi. In the sleep mode, both the first voltage VC and the second voltage RAMP are 0V, and the comparison signal CMP is at a low level. These points are the same except that the bias voltage applied to the capacitor C2 is changed from the output voltage Vo to the input voltage Vi.

  When the sleep control signal XSLP is raised to a high level at time t31, the DC / DC converter 1 returns to the wake-up mode. At this time, in the phase compensation circuit 40, the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the error amplifier 30 are electrically connected, and the second terminal of the capacitor C1 and the ground terminal are disconnected. Thus, the second end of the capacitor C2 is connected to the second end of the capacitor C1.

  That is, the phase compensation capacitor unit 42 is in a state in which the capacitor C1 discharged between both ends thereof and the capacitor C2 charged between the both ends with the input voltage Vi are connected in parallel with the cancellation of the sleep mode.

  As a result, the first voltage VC quickly follows VC = k × Vi (= {C2 / (C1 + C2)} × Vi) without waiting for the error amplifier 30 to start according to the charge distribution rule between the capacitors C1 and C2. To be raised.

  Further, since the oscillator 50 is in an operating state after time t31, a second voltage RAMP having a ramp waveform that is pulse-driven at the switching frequency fsw (= 1 / T) is generated. Note that the amplitude of the second voltage RAMP is a variation value (= k × Vo) corresponding to the output voltage Vo, as described above.

  Here, the on-duty Don (= Ton / T) of the DC / DC converter 1 is determined according to the comparison result between the first voltage VC and the second voltage RAMP. Specifically, from the timing when the first voltage VC (= k × Vi) and the second voltage RAMP (= (k × Vo / T) × (T−Ton)) coincide with each other, the on-duty when the sleep mode is released Don (= corresponding to the initial duty value) is 1- (Vi / Vo). This initial duty value coincides with the theoretical duty value when the input voltage Vi is boosted to generate the desired output voltage Vo. Therefore, even when the switch output stage 10 is a boost type, overshoot and undershoot of the output voltage Vo when the sleep mode is canceled can be prevented.

  Of course, even when this embodiment is adopted, it is needless to say that the same effect as that of the first embodiment, that is, reduction of power consumption and restart time can be achieved.

  Further, in the present embodiment, an example in which the switch output stage 10 is changed to the boost type while taking the first embodiment (FIG. 1) as a base has been described, but the second embodiment (FIG. 3) may be used as a base. it can. In this case, for example, the first bias voltage for charging the capacitor C2 may be set as the input voltage Vi, and the second bias voltage for charging the capacitor C3 may be set as the output voltage Vo.

  In the first to third embodiments, the step-down type (FIGS. 1 and 3) and the step-up type (FIG. 5) are given as examples of the output format of the switch output stage 10. May be adopted. Further, the rectification method of the switch output stage 10 is not limited to the above-described synchronous rectification method, and can be changed to a diode rectification method (= method using a rectification diode instead of the synchronous rectification transistor). Further, the output feedback control method of the DC / DC converter 1 is not limited to the voltage mode control method described above, and may be a current mode control method.

<Fourth embodiment>
FIG. 7 is a circuit diagram showing a fourth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is a step-down switching power supply that employs a current mode control system, and includes a switch output stage 10, a feedback voltage generation unit 20, an error amplifier 30 (corresponding to a first amplifier), First phase compensation circuit 40, oscillator 50, PWM comparator 60, driver 70, differential amplifier 80 (corresponding to the second amplifier), second phase compensation circuit 90, current detection unit 100, and clamper 110 And having.

  Note that many of the above-described components are common to those of the first embodiment (FIG. 1). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 1, and redundant descriptions are omitted. In the following, the characteristic portions of the fourth embodiment are mainly described.

  The switch output stage 10, the feedback voltage generator 20, and the error amplifier 30 are exactly the same as those in the first embodiment (FIG. 1).

  The first phase compensation circuit 40 corresponds to the phase compensation circuit 40 of the first embodiment (FIG. 1), receives the first error current signal I30 from the error amplifier 30, and generates an error voltage COMP. However, in the DC / DC converter 1 of the present embodiment, since the function of shifting to the sleep mode is omitted, unlike the first embodiment (FIG. 1), the capacitor of the phase compensation capacitance unit 42 is divided into a plurality. The switches 43 to 45 are not provided.

  The oscillator 50 and the PWM comparator 60 are exactly the same as those in the first embodiment (FIG. 1).

  The driver 70 is changed to a configuration including inverters 75 and 76 instead of the NAND gate 71 and the AND gate 72 in accordance with the omission of the sleep mode. The inverters 75 and 76 output the logical inversion signals of the comparison signal CMP as the gate signals G1 and G2, respectively. Therefore, when the comparison signal CMP is at the high level, the gate signals G1 and G2 are both at the low level, so that the output transistor 11 is turned on and the synchronous rectification transistor 12 is turned off. Conversely, when the comparison signal CMP is at a low level, both the gate signals G1 and G2 are at a high level, so that the output transistor 11 is turned off and the synchronous rectification transistor 12 is turned on.

  The differential amplifier 80, like the error amplifier 30, is a current output type transconductance amplifier (so-called gm amplifier), and is applied to the error voltage COMP applied to the inverting input terminal (−) and the non-inverting input terminal (+). The second error current signal I80 corresponding to the difference from the current sense voltage CSNS to be generated is generated. The second error current signal I80 flows in the positive direction (= direction from the differential amplifier 80 toward the second phase compensation circuit 90) when the error voltage COMP is lower than the current sense voltage CSNS, and the error voltage COMP is the current sense voltage CSNS. When the value is higher, the current flows in the negative direction (= direction from the second phase compensation circuit 90 toward the differential amplifier 80).

  The second phase compensation circuit 90 is connected between the differential amplifier 80 and the PWM comparator 60, and receives the second error current signal I80 and generates the first voltage VC. The configuration and operation of the second phase compensation circuit 90 will be described later.

  The current detection unit 100 generates a current sense voltage CSNS corresponding to the coil current IL flowing through the switch output stage 10. For example, the current sense voltage CSNS increases as the average value IL (ave) of the coil current IL increases, and conversely decreases as the average value IL (ave) of the coil current IL decreases.

  The clamper 110 limits the error voltage COMP to a predetermined upper limit voltage value VLMT or less. As a result, in the differential amplifier 80, output feedback control is performed so that the current sense voltage CSNS corresponding to the coil current IL is limited to the upper limit voltage value VLMT or less, and therefore the coil current IL is set to the upper limit current value ILMT or less. Limited.

<Second phase compensation circuit>
Next, the configuration and operation of the second phase compensation circuit 90 will be described in detail with reference to FIG. The second phase compensation circuit 90 in this figure includes a phase compensation resistor 91 and a phase compensation capacitor 92, and compensates for the phase of the first voltage VC to prevent oscillation of the output feedback loop.

  The phase compensation capacitance unit 92 includes capacitors C4 and C5. A first terminal of the capacitor C4 is connected to the ground terminal. On the other hand, the first end of the capacitor C5 is connected to the application end of the output voltage Vo. When the capacitance value of the entire phase compensation capacitor 92 is C, the capacitance value of the capacitor C4 is C4, and the capacitance value of the capacitor C5 is C5, C = C4 + C5, C5 / C4 = k / (1-k) (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitor unit 92 of the present embodiment, the phase compensation capacitor is divided into two, and at least one ground side node (the first end of the capacitor C5 in this figure) has a DC. The output voltage Vo of the / DC converter 1 is applied as the monitoring target voltage, and the technical significance thereof will be described later.

  The phase compensation resistor 91 includes a resistor having a first end connected to the non-inverting input end (+) of the PWM comparator 60 and a second end connected to the second ends of the capacitors C4 and C5.

  FIG. 8 is a timing chart showing an example of the rush current suppression operation in the fourth embodiment. In order from the top, the output voltage Vo, the first voltage VC (solid line), the second voltage RAMP (broken line), and the comparison signal CMP are illustrated. , As well as the coil current IL.

  Before the time t43, since the short circuit of the switch output stage 10 has not occurred, the output voltage Vo is maintained at the target value Vo1. Further, since the first voltage VC is maintained at k × Vo1 by the function of the output feedback loop, the on-duty Don (= Ton / T) of the DC / DC converter 1 reduces the input voltage Vi to a desired value. This coincides with the theoretical duty value (= Vo1 / Vi) when the output voltage Vo (= Vo1) is generated.

  On the other hand, when the switch output stage 10 is short-circuited at time t43 and the output voltage Vo suddenly drops from the target value Vo1 to the abnormal value Vo2, the first voltage VC is output according to the charge distribution law between the capacitors C4 and C5. Without waiting for the response of the feedback loop, the voltage drops sharply with the same behavior as the output voltage Vo.

  In particular, in the DC / DC converter 1 of the present embodiment, C5 / C4 = k / (1−k) (where 0 <k <1) is satisfied, so when the output voltage Vo varies by ΔV, One voltage VC fluctuates by k × ΔV. Further, as described above, the amplitude of the second voltage RAMP is a variation value (= k × Vi) corresponding to the input voltage Vi.

  If such a setting is performed, the on-duty Don of the DC / DC converter 1 is the theoretical duty value (= Vo2 / Vi) corresponding to the abnormal value Vo2 of the output voltage Vo simultaneously with the occurrence of a short circuit of the switch output stage 10. Will be shifted to. As a result, the rush current (= excessive coil current IL) generated when the switch output stage 10 is short-circuited can be effectively suppressed, so that deterioration of the elements forming the switch output stage 10 can be prevented. .

  Note that the response speed of the differential amplifier 80 and the clamper 110 does not need to be increased if the duty tracking control according to the transient fluctuation of the output voltage Vo is realized using the second phase compensation circuit 90. Therefore, since the voltage loop characteristics do not change, the oscillation risk does not increase.

  In the case of the DC / DC converter 1 of the present embodiment, the amplitude of the second voltage RAMP varies depending on the input voltage Vi, so that the on-duty of the DC / DC converter 1 can be achieved even when the input voltage Vi changes suddenly. It is possible to adjust Don to an appropriate value and suppress the rush current.

<Fifth Embodiment>
FIG. 9 is a circuit diagram showing a fifth embodiment of the DC / DC converter. The DC / DC converter 1 according to this embodiment is based on the fourth embodiment (FIG. 7), but is included in the phase compensation resistor 91 instead of dividing the capacitor included in the phase compensation capacitor 92 into a plurality of parts. It is characterized in that the resistor is divided into a plurality of parts. Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the fifth embodiment are mainly described.

  The phase compensation resistor unit 91 includes resistors R1 and R2. The first end of the resistor R1 is connected to the ground end. The 1st end of resistance R2 is connected to the application end of output voltage Vo. R = R1 // R2, R1 / R2 = k / (1−R2 where R is the resistance value of the entire phase compensation resistor unit 91, R1 is the resistance value of the resistor R1, and R2 is the resistance value of the resistor R2. k) (where 0 <k <1) is satisfied. As described above, in the phase compensation resistor 91 of the present embodiment, the phase compensation resistor is divided into two, and at least one ground side node (the first end of the resistor R2 in this figure) has a DC. The output voltage Vo of the DC converter 1 is applied as the monitoring target voltage.

  The phase compensation capacitor 92 includes a capacitor having a first end connected to the non-inverting input end (+) of the PWM comparator 60 and a second end connected to the second ends of the resistors R1 and R2.

  In the DC / DC converter 1 of this embodiment, for example, when the output voltage Vo suddenly drops due to a short circuit of the switch output stage 10, the first voltage VC is applied to the output feedback loop by the voltage dividing action of the resistors R1 and R2. Without waiting for a response, the voltage drops sharply with the same behavior as the output voltage Vo. Therefore, the same effect as the previous fourth embodiment (FIG. 7) can be enjoyed.

  In particular, in the present embodiment, a divided voltage of the output voltage Vo is applied to the capacitor of the phase compensation capacitor 92. Accordingly, even when the output voltage Vo is relatively high, it is not necessary to unnecessarily increase the breakdown voltage of the capacitor, which can be said to be suitable for integration in a semiconductor device.

<Sixth Embodiment>
FIG. 10 is a circuit diagram showing a sixth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the fourth embodiment (FIG. 7), and is characterized in that it has a function of shifting to the sleep mode according to the first embodiment (FIG. 1). Have Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the fifth embodiment are mainly described.

  With the introduction of the sleep mode, changes are made to the error amplifier 30, the oscillator 50, the PWM comparator 60, the driver 70, the differential amplifier 80, and the second phase compensation circuit 90, respectively. Below, the change of each part is demonstrated.

  The error amplifier 30, the oscillator 50, the PWM comparator 60, and the differential amplifier 80 are in an operating state when the sleep control signal XSLP is at a high level (= logic level when the sleep mode is released), and the sleep control signal XSLP is low. When it is at the level (= the logic level at the time of the sleep mode), the stop state is entered.

  The driver 70 includes a NAND gate 71 and an AND gate 72 instead of the inverters 75 and 76, and generates gate signals G1 and G2 according to the comparison signal CMP and the sleep control signal XSLP. Since the circuit configuration and operation are the same as those in the first embodiment (FIG. 1), a duplicate description will be omitted.

  The second phase compensation circuit 90 includes switches 93 to 95 in addition to the phase compensation resistor unit 91 and the phase compensation capacitor unit 92.

  The switch 93 conducts / cuts off between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the differential amplifier 80 according to the sleep control signal XSLP. Specifically, the switch 93 is turned on when the sleep control signal XSLP is at a high level, and conducts between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the differential amplifier 80, When the sleep control signal XSLP is at a low level, it is turned off to block between the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the differential amplifier 80.

  The switch 94 conducts / cuts off between the second end of the capacitor C4 and the ground end in accordance with the sleep control signal XSLP. Specifically, the switch 94 is turned on when the sleep control signal XSLP is at a low level, and conducts between the second end of the capacitor C4 and the ground terminal, and when the sleep control signal XSLP is at a high level. To turn off the second terminal of the capacitor C4 and the ground terminal.

  The switch 95 switches whether the second terminal of the capacitor C5 is connected to the application terminal of the output voltage Vo (corresponding to the monitoring target voltage) or to the ground terminal according to the sleep control signal XSLP. Specifically, the switch 95 connects the second terminal of the capacitor C5 to the ground terminal when the sleep control signal XSLP is at a low level, and the second terminal of the capacitor C5 when the sleep control signal XSLP is at a high level. The end is connected to the application end of the output voltage Vo.

  In the second phase compensation circuit 90 configured as described above, when the sleep mode is canceled (XSLP = H), the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the differential amplifier 80 are electrically connected. The second end of the capacitor C4 is disconnected from the ground end, and the second end of the capacitor C5 is connected to the application end of the output voltage Vo.

  That is, the phase compensation capacitance unit 92 is in a state in which the capacitors C4 and C5 are connected in series between the application terminal of the output voltage Vo and the ground terminal when the sleep mode is canceled. As a result, the first voltage VC is quickly increased to VC = k × Vo (= {C4 / (C4 + C5)} × Vo) without waiting for the activation of the differential amplifier 80 due to the capacitance division of the capacitors C4 and C5. Be raised. Therefore, as in the first embodiment (FIG. 1), the duty initial value when the sleep mode is canceled is set using the second phase compensation circuit 90.

  Further, after the sleep mode is canceled, the connection state of the phase compensation capacitor 92 is completely equivalent to that in FIG. Therefore, similarly to the fourth embodiment (FIG. 7), the duty tracking control according to the transient fluctuation of the output voltage Vo can be realized using the second phase compensation circuit 90, so that the switch output stage 10 is short-circuited. It becomes possible to effectively suppress the rush current generated at the time of abnormality.

  Thus, if it is the DC / DC converter 1 of this embodiment, it will become possible to enjoy the effect of both 1st Embodiment (FIG. 1) and 4th Embodiment (FIG. 7).

<Seventh embodiment>
FIG. 11 is a circuit diagram showing a seventh embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the sixth embodiment (FIG. 10), but is included in the phase compensation resistor unit 91, instead of dividing the capacitor included in the phase compensation capacitor unit 92 into a plurality of parts. It is characterized in that the resistor is divided into a plurality of parts. In accordance with this change, the second phase compensation circuit 90 is provided with switches 96 to 98 instead of the switches 94 and 95. Therefore, the same components as those in the sixth embodiment are denoted by the same reference numerals as those in FIG. 10, and redundant descriptions are omitted. In the following, the characteristic portions of the seventh embodiment are mainly described.

  The phase compensation resistor unit 91 includes resistors R1 and R2. The first end of the resistor R1 is connected to the ground end. The first end of the resistor R2 is connected to the application terminal for the output voltage Vo via the switch 97. When the resistance value of the entire phase compensation resistor unit 91 is R, the resistance value of the resistor R1 is R1, and the resistance value of the resistor R2 is R2, R = R1 // R2, R1 / R2 = k / ( 1-k) (where 0 <k <1) is satisfied. This is the same as in the fifth embodiment (FIG. 9).

  The phase compensation capacitor 92 includes a capacitor having a first end connected to the non-inverting input end (+) of the PWM comparator 60 and a second end connected to the second ends of the resistors R1 and R2.

  The switch 96 conducts / cuts off between the second end of the resistor R1 and the ground end in accordance with the sleep control signal XSLP. More specifically, the switch 96 is turned on when the sleep control signal XSLP is at a low level to conduct between the second end of the resistor R1 and the ground terminal, and the sleep control signal XSLP is at a high level. Sometimes it is turned off to block between the second end of the resistor R1 and the ground end.

  The switch 97 conducts / cuts off between the second end of the resistor R2 and the application end of the output voltage Vo (= corresponding to the monitoring target voltage) according to the sleep control signal XSLP. More specifically, the switch 97 is turned off when the sleep control signal XSLP is at a low level to cut off between the second end of the resistor R2 and the application end of the output voltage Vo, and the sleep control signal XSLP is When it is at the high level, it is turned on and conducts between the second end of the resistor R2 and the application end of the output voltage Vo.

  The switch 98 conducts / cuts off between the first end of the phase compensation capacitor 92 and the ground end in accordance with the sleep control signal XSLP. More specifically, the switch 98 is turned on when the sleep control signal XSLP is at a low level to conduct between the first end of the phase compensation capacitor 92 and the ground end, and the sleep control signal XSLP is high. When it is at the level, it is turned off to block between the first end of the phase compensation capacitor 92 and the ground end.

  In the second phase compensation circuit 90 configured as described above, when the sleep mode is canceled (XSLP = H), the non-inverting input terminal (+) of the PWM comparator 60 and the output terminal of the differential amplifier 80 are electrically connected. The second end of the resistor R1 and the ground end, and the first end of the phase compensation capacitor 92 and the ground end are both blocked, and the second end of the resistor R2 is the application end of the output voltage Vo. It will be connected to.

  That is, the phase compensation resistor unit 91 is in a state in which the resistors R1 and R2 are connected in series between the application terminal of the output voltage Vo and the ground terminal when the sleep mode is released. As a result, the first voltage VC is quickly increased to VC = k × Vo (= {R1 / (R1 + R2)} × Vo) without waiting for the activation of the differential amplifier 80 by the resistance voltage division of the resistors R1 and R2. Be raised. Therefore, as in the first embodiment (FIG. 1), the duty initial value when the sleep mode is canceled is set using the second phase compensation circuit 90.

  In addition, after the sleep mode is canceled, the connection state of the phase compensation resistor unit 91 is completely equivalent to FIG. Accordingly, as in the previous fifth embodiment (FIG. 9), the duty tracking control according to the transient fluctuation of the output voltage Vo can be realized using the second phase compensation circuit 90, so that the switch output stage 10 is short-circuited. It becomes possible to effectively suppress the rush current generated at the time of abnormality.

  In particular, in the present embodiment, a divided voltage of the output voltage Vo is applied to the capacitor of the phase compensation capacitor 92. Accordingly, even when the output voltage Vo is relatively high, it is not necessary to unnecessarily increase the breakdown voltage of the capacitor, which can be said to be suitable for integration in a semiconductor device.

  Thus, if it is the DC / DC converter 1 of this embodiment, it will become possible to enjoy the effect of both 1st Embodiment (FIG. 1) and 5th Embodiment (FIG. 9).

<Eighth Embodiment>
FIG. 12 is a circuit diagram showing an eighth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is characterized in that the current sense voltage CSNS is fed back to the arithmetic unit 120 instead of the differential amplifier 80 while being based on the fourth embodiment (FIG. 7). With this change, the second phase compensation circuit 90 is omitted, and the function is transferred to the phase compensation circuit 40. Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the eighth embodiment are mainly described.

  The phase compensation circuit 40 includes a phase compensation resistor unit 41 and a phase compensation capacitor unit 42, and compensates the phase of the error voltage COMP to prevent oscillation of the output feedback loop.

  The phase compensation capacitance unit 42 includes capacitors C6 and C7. A first terminal of the capacitor C6 is connected to the ground terminal. On the other hand, the first end of the capacitor C7 is connected to the application end of the output voltage Vo. Note that C = C6 + C7, C7 / C6 = k / (1-k) where C is the capacitance value of the entire phase compensation capacitor 42, C6 is the capacitance value of the capacitor C6, and C7 is the capacitance value of the capacitor C7. (However, 0 <k <1) is satisfied. As described above, in the phase compensation capacitor unit 42 of the present embodiment, the phase compensation capacitor is divided into two, and at least one ground side node (the first end of the capacitor C7 in this figure) has a DC. The output voltage Vo of the DC converter 1 is applied as the monitoring target voltage.

  The phase compensation resistor unit 41 includes a resistor having a first end connected to the output end of the error amplifier 30 and a second end connected to the second ends of the capacitors C6 and C7.

  The arithmetic unit 120 generates the first voltage VC (= COMP-CSNS) by performing arithmetic processing (for example, subtraction processing for subtracting the current sense voltage CSNS from the error voltage COMP) between the error voltage COMP and the current sense voltage CSNS. To do.

  As described above, even when the current mode control method is realized by using the arithmetic unit 120, the phase compensation circuit 40 has a circuit configuration equivalent to that of FIG. 7, so that it is the same as that of the fourth embodiment (FIG. 7). It is possible to enjoy the effects. Further, the phase compensation circuit 40 may have a circuit configuration equivalent to that shown in FIG.

<Ninth Embodiment>
FIG. 13 is a circuit diagram showing a ninth embodiment of the DC / DC converter. The DC / DC converter 1 according to the present embodiment is characterized in that a computing unit 130 is used instead of the computing unit 120 while being based on the eighth embodiment (FIG. 12). Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the eighth embodiment are mainly described.

  The computing unit 130 performs a computation process (for example, an addition process for adding the second voltage RAMP and the current sense voltage CSNS) between the second voltage RAMP and the current sense voltage CSNS, thereby obtaining the third voltage RAMP ′ (= RAMP + CSNS). ) Is generated.

  In accordance with the above change, the PWM comparator 60 compares the first voltage VC input to the non-inverting input terminal (+) with the third voltage RAMP ′ input to the inverting input terminal (−) to compare signals. Generate CMP.

  As described above, even when the current mode control method is realized by using the arithmetic unit 130, the phase compensation circuit 40 has a circuit configuration equivalent to that shown in FIG. 7, so that it is the same as that in the fourth embodiment (FIG. 7). It is possible to enjoy the effects. Further, the phase compensation circuit 40 may have a circuit configuration equivalent to that shown in FIG.

<Tenth Embodiment>
FIG. 14 is a circuit diagram showing a tenth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is characterized in that the switch output stage 10 is changed from a step-down type to a step-up type while being based on the fourth embodiment (FIG. 7). Therefore, the same components as those in the fourth embodiment are denoted by the same reference numerals as those in FIG. 7, and redundant descriptions are omitted. In the following, the characteristic portions of the tenth embodiment are mainly described.

  The switch output stage 10 is a boost type that boosts the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 15 (NMOSFET in this figure), a synchronous rectification transistor 16 (PMOSFET in this figure), a coil 17 and the capacitor 18 are included. Since the circuit configuration and operation are the same as those of the third embodiment (FIG. 5), a duplicate description is omitted.

  Further, as the switch output stage 10 is changed from the step-down type to the step-up type, the oscillator 50, the PWM comparator 60, the driver 70, and the second phase compensation circuit 90 are also changed. Below, the change of each part is demonstrated.

  In the oscillator 50, the amplitude of the second voltage RAMP is changed from a fluctuation value (= k × Vi) corresponding to the input voltage Vi to a fluctuation value (= k × Vo) corresponding to the output voltage Vo.

  The input polarity of the PWM comparator 60 is inverted from that of the fourth to ninth embodiments. That is, the first voltage VC is input to the inverting input terminal (−) of the PWM comparator 60, and the second voltage RAMP is input to the non-inverting input terminal (+) of the PWM comparator 60. Accordingly, the logical level of the comparison signal CMP is low when the first voltage VC is higher than the second voltage RAMP, contrary to that of the fourth to ninth embodiments, and the first voltage VC becomes the second voltage RAMP. High level when lower than

  Driver 70 includes buffers 77 and 78 instead of inverters 75 and 76. The buffers 77 and 78 generate gate signals G3 and G4 having the same logic level as the comparison signal CMP, respectively. Therefore, when the comparison signal CMP is at a high level, the gate signals G3 and G4 are both at a high level, so that the output transistor 15 is turned on and the synchronous rectification transistor 16 is turned off. Conversely, when the comparison signal CMP is at a low level, the gate signals G3 and G4 are both at a low level, so that the output transistor 15 is turned off and the synchronous rectification transistor 16 is turned on.

  In the second phase compensation circuit 90, the monitoring target voltage applied to the second end of the capacitor C5 is changed from the output voltage Vo to the input voltage Vi.

  According to the DC / DC converter 1 of the present embodiment, it is possible to realize duty tracking control according to the transient fluctuation of the input voltage Vi using the second phase compensation circuit 90. Therefore, even if the switch output stage 10 is a boost type, it is possible to enjoy the effect of suppressing the rush current.

  In the case of the DC / DC converter 1 of the present embodiment, the amplitude of the second voltage RAMP varies depending on the output voltage Vo. Therefore, even when the output voltage Vo changes suddenly, the on-duty of the DC / DC converter 1 is increased. It is possible to adjust Don to an appropriate value and suppress the rush current.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The DC / DC converter disclosed in this specification can be used as a power supply means for various applications.

DESCRIPTION OF SYMBOLS 1 DC / DC converter 10 Switch output stage 11, 15 Output transistor 12, 16 Synchronous rectification transistor 13, 17 Coil 14, 18 Capacitor 20 Feedback voltage generation part 21, 22 Resistor 30 Error amplifier 40 Phase compensation circuit (1st phase compensation circuit) )
41 Phase Compensation Resistor 42 Phase Compensation Capacitor 43, 44, 45, 46 Switch 50 Oscillator 60 PWM Comparator 70 Driver 71 NAND Gate 72, 73 AND Gate 74 OR Gate 75, 76 Inverter 77, 78 Buffer 80 Differential Amplifier 90 1st Two-phase compensation circuit 91 Phase compensation resistor unit 92 Phase compensation capacitor unit 93, 94, 95, 96, 97, 98 Switch 100 Current detection unit 110 Clamper 120, 130 Calculator C1, C2, C3, C4, C5, C6, C7 Capacitor R1, R2 resistance

Claims (11)

A phase compensation circuit for compensating a phase of a first voltage inputted to a PWM comparator of a DC / DC converter having a sleep mode,
A phase compensation resistor including a resistor;
A phase compensation capacitor including a plurality of capacitors;
In the sleep mode, each capacitor is switched to the first connection state and at least one capacitor is charged with the first bias voltage. On the other hand, when the sleep mode is released, each capacitor is switched to the second connection state and the first connection state is set. A group of switches for setting the voltage to a desired initial value;
A phase compensation circuit comprising:   The phase compensation circuit according to claim 1, wherein the switch group switches at least one connection destination of the plurality of capacitors according to a sleep control signal.   The phase compensation capacitance unit includes a first capacitor and a second capacitor, each having a first end connected to a ground end, and the switch group is provided between the second end of the first capacitor and the ground end. A first switch that conducts / cuts off; and a second switch that switches between connecting a second end of the second capacitor to an application end of the first bias voltage or connecting to a second end of the first capacitor. The phase compensation circuit according to claim 2, further comprising:   When the capacitance value of the first capacitor is C1 and the capacitance value of the second capacitor is C2, C2 / C1 = k / (1-k) (where 0 <k <1) is satisfied, The phase compensation circuit according to claim 3, wherein the amplitude of the second voltage compared with the first voltage by the PWM comparator is set to k times the input voltage or the output voltage. The phase compensation capacitance unit further includes a third capacitor having a first end connected to the ground end,
The switch group includes a third switch for switching whether the second end of the third capacitor is connected to an application end of a second bias voltage different from the first bias voltage or to the second end of the first capacitor. The phase compensation circuit according to claim 3, further comprising:   When the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and the capacitance value of the third capacitor is C3, C1: C2: C3 = {1- (k + k ′)}: k: k ′ (where 0 <k <1 and 0 <k ′ <1) is satisfied, and the amplitude of the second voltage compared with the first voltage by the PWM comparator is the input voltage or The phase compensation circuit according to claim 5, wherein the phase compensation circuit is set to k times the output voltage.   7. The resistor according to claim 3, wherein a first end of the resistor is connected to an input end of the PWM comparator, and a second end is connected to a second end of the first capacitor. The phase compensation circuit according to any one of the above.   8. The phase compensation circuit according to claim 7, further comprising a switch for conducting / interrupting between the input terminal of the PWM comparator and the preceding circuit in accordance with the sleep control signal. A switch output stage that generates an output voltage from the input voltage; and
An amplifier that generates an error signal according to a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage;
A phase compensation circuit for receiving the error signal and generating a first voltage;
An oscillator for generating a second voltage having a ramp waveform;
A PWM comparator that compares the first voltage with the second voltage to generate a comparison signal;
A driver that generates a drive signal of the switch output stage in response to the comparison signal;
Have
A DC / DC converter, wherein the phase compensation circuit according to any one of claims 1 to 8 is used as the phase compensation circuit.   The switch output stage is a step-down type, the first bias voltage is the output voltage, and the amplitude of the second voltage is a fluctuation value according to the input voltage. DC / DC converter.   The switch output stage is a step-up type, the first bias voltage is the input voltage, and the amplitude of the second voltage is a fluctuation value corresponding to the output voltage. DC / DC converter.

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