JP4929856B2 - Switching element control device - Google Patents

Description

  The present invention relates to a switching element control device capable of preventing a through current from flowing greatly while reducing recovery loss.

  Conventionally, a series circuit of a high-side MOSFET as a main switching element and a low-side MOSFET as a synchronous rectifier is connected in parallel to a DC power source, and a smoothing reactor and a smoothing capacitor are connected between the drain and source of the low-side MOSFET. Are connected in series, and the high-side MOSFET and the low-side MOSFET are alternately turned on / off to step down the voltage of the DC power supply and supply a constant voltage to the load connected to both ends of the smoothing capacitor. In a synchronous rectification step-down DC-DC converter, a control circuit that outputs a gate signal to a high-side MOSFET and a low-side MOSFET has an inverted logic of a pulse width control signal for controlling the voltage across the smoothing capacitor to be constant. Signal and low side MOSF Means for outputting a logical product signal of the inverted logic signal of the voltage across T as a gate signal of the low-side MOSFET, and a logical product signal of the inverted logic signal of the gate voltage of the low-side MOSFET and the pulse width control signal as the high side There is known a step-down DC-DC converter including a means for outputting as a gate signal of a side MOFET (see, for example, Patent Document 1).

Similarly, as a technique for automatically controlling the dead time, in the step-down DC-DC converter, the main transistor and the synchronous rectification transistor are simultaneously turned on, and the main transistor is turned on so that a large through current is not generated. A technique for generating a dead time is known (see, for example, Patent Document 2).
JP 2004-312913 A Specification of US 6,369,250 (B1)

  By the way, in order to reduce recovery loss, it is known that it is effective to cross the switching timing of two switching elements. However, if the switching timing is excessively crossed, a through current flows greatly. In this regard, the above-mentioned conventional technology cannot detect crossing when the dead time is shortened, so the dead time is set somewhat longer so that a large through current does not flow, and recovery loss is effective. It has not yet been reduced.

  Accordingly, an object of the present invention is to provide a switching element control device capable of preventing a through current from flowing greatly while reducing recovery loss.

In order to achieve the above object, a switching element control device according to a first invention includes a first switching element and a second switching element connected in series,
Gate-source voltage detection means for detecting a voltage between the gate and source of the first switching element ;
A second gate-source voltage detecting means for detecting a voltage between the gate and the source of the second switching element ;
Based on the output result of the gate-source voltage detection means, when the first switching element is turned on, the gate-source voltage of the first switching element rises to become substantially constant and then rises again. Detect the timing,
Based on the output result of the second gate-source voltage detection means, the timing at which the gate-source voltage of the second switching element at the time of turn-off of the second switching element falls below a predetermined value is detected,
When the first switching element is turned on, the gate-source voltage of the first switching element rises to become substantially constant and then rises again, and the second restarting timing when the second switching element is turned off. The turn-off timing of the second switching element is adjusted so that the timing at which the gate-source voltage of the switching element falls below a predetermined value is substantially the same. Thereby , based on the gate-source voltage of the first switching element, it is possible to appropriately detect the timing when the charging of the gate-mirror capacitance of the first switching element is completed, and to the on-timing of the first switching element. The switching timing can be optimally crossed by substantially matching the OFF timing of the second switching element.

The switching element control device according to the second invention includes a first switching element and a second switching element connected in series,
Gate-source voltage detecting means for detecting a voltage between the gate and source of the first switching element;
Based on the output result of the gate-source voltage detecting means, the voltage-to-voltage period starts when the gate-source voltage of the first switching element at the time of turn-on of the first switching element temporarily becomes substantially constant during its rise. Detect the timing,
The gate signal for the second switching element is switched from High to Lo after a predetermined delay time has elapsed from the start timing of the detected voltage constant period. Thus, the switching timing can be optimally crossed with a simple configuration without detecting the gate-source voltage of the second switching element.

According to a third aspect of the present invention, in the switching element control device according to the second aspect of the present invention,
When the charging of the gate mirror capacitor of the first switching element is completed before the predetermined delay time elapses , that is, the gate-source voltage of the first switching element that becomes temporarily substantially constant during the rise. When the voltage rises again , the gate signal for the second switching element is switched from High to Lo.

4th invention is the switching element control apparatus which concerns on 2nd or 3rd invention,
Load current detection means for detecting the current flowing through the load,
The predetermined delay time is changed according to the magnitude of the load current. Thereby, an appropriate delay time according to the magnitude of the load current can be set.

A switching element control device according to a fifth aspect of the invention includes a first switching element and a second switching element connected in series,
Gate-source voltage detection means for detecting a voltage between the gate and source of the first switching element ;
A second gate-source voltage detecting means for detecting a voltage between the gate and the source of the second switching element ;
Based on the output result of the gate-source voltage detection means, the fixed-voltage period starts when the gate-source voltage of the first switching element at the time of turn-off of the first switching element temporarily becomes substantially constant during the fall. Detect the timing,
Based on the output result of the second gate-source voltage detection means, the timing at which the gate-source voltage of the second switching element rises when the second switching element is turned on and a timing exceeding a predetermined value is detected,
When the first switching element is turned off, the gate-source voltage of the first switching element temporarily becomes substantially constant in the middle of the decrease, and the voltage constant period start timing is second, and the second switching element is turned on. The turn-on timing of the second switching element is adjusted so that the timing exceeding a predetermined value after the gate-source voltage of the switching element rises substantially matches . Thereby, the switching timing at the time of turn-off of the first switching element can be optimally crossed.

6th invention is the switching element control apparatus which concerns on 5th invention,
If the gate signal for the second switching element is Lo even when the start timing of the voltage constant period occurs , the gate signal for the second switching element is switched from Lo to High.

The switching element control device according to the seventh invention is
A first switching element and a second switching element connected in series;
Gate-source voltage detecting means for detecting a voltage between the gate and source of the second switching element;
Based on the output result of the gate-source voltage detecting means, the second switching element is turned on after a predetermined delay time from the time when the gate-source voltage of the second switching element becomes larger than a predetermined value when the first switching element is turned on . The gate signal for the switching element is switched from High to Lo . Accordingly, the switching timing at the turn-on time of the first switching element can be optimally crossed with a simple configuration without detecting the gate-source voltage of the first switching element .

The switching element control device according to the eighth invention is
A first switching element and a second switching element connected in series;
Gate-source voltage detecting means for detecting a voltage between the gate and source of the second switching element;
Based on the output result of the gate-source voltage detection means, when the gate-source voltage of the second switching element becomes smaller than a predetermined value when the first switching element is turned off, the gate for the second switching element is The signal is switched from Lo to High . Thereby, even if it does not detect the gate-source voltage of a 1st switching element, the switching timing at the time of the turn-off of a 1st switching element can be crossed optimally with a simple structure .

A ninth invention is a switching element control device according to any one of the first to eighth inventions used for voltage control in a synchronous rectification type DC-DC converter,
The first switching element is a main switching element, and the second switching element is a synchronous rectification switching element. Thereby, the dead time can be adjusted without changing the duty of the main switching element that determines the output voltage.

According to a tenth aspect of the present invention, in the switching element control device according to any one of the first to ninth aspects, the first switching element and the second switching element are MOSFETs.

An eleventh invention is the switching element control device according to any one of the first to ninth inventions, wherein the first switching element and the second switching element are IGBTs, and the gate-source voltage is a gate -It is characterized by being replaced by the voltage between emitters.

  According to the present invention, it is possible to obtain a switching element control device that can prevent a through current from flowing greatly while reducing recovery loss.

  Hereinafter, the best mode for carrying out the present invention will be described in several embodiments with reference to the drawings.

  As a definition of the term, the term “turn on” means an operation for changing the switching element to a conducting state, and the term “on” means that the switching element is actually conducting. Similarly, the term “turn-off” means an operation for changing the switching element to a non-conducting state, and the term “off” means that the switching element is actually non-conducting.

  FIG. 1 is a main circuit diagram showing an embodiment of a power supply apparatus 10A related to a switching element control apparatus according to the present invention.

  As shown in FIG. 1, the power supply device 10A of the present embodiment is a synchronous rectification step-down DC-DC converter. Specifically, the main switching element 11 and the synchronous rectification switching element 12 connected in series are connected in parallel to a DC power supply (not shown). A smoothing reactor and a smoothing capacitor are connected in series between the drain and source of the switching element 12 for synchronous rectification, and an output voltage VOUT is taken out between the smoothing reactor and the smoothing capacitor. The main switching element 11 and the synchronous rectification switching element 12 are alternately turned on / off in a manner described in detail below, step down the voltage VIN of the DC power supply, and a load (not shown) connected in parallel to the smoothing capacitor. ) Is supplied with a desired output voltage VOUT. In this example, the main switching element 11 and the synchronous rectification switching element 12 are formed of a MOSFET (metal oxide semiconductor field-effect transistor).

  The power supply device 10A includes a PWM signal generation circuit 123, a dead time control circuit 124A, drivers 141 and 142 for driving the main switching element 11 and the synchronous rectification switching element 12, and a dead time control circuit 124A. The time detector 150 includes a first detector 130A that detects a gate-source voltage Vgs1 of the main switching element 11, and a gate-source voltage Vgs2 of the synchronous rectification switching element 12 (the gate of the synchronous rectification switching element 12). And a second detector 132A for detecting a voltage Vgs2) between the ground and the ground.

  The dead time control circuit 124A generates a gate signal Vg1 to be applied to the gate of the main switching element 11 based on the PWM signal from the PWM signal generation circuit 123, the PWM signal from the PWM signal generation circuit 123, and Based on the dead time detection result from the dead time detector 150, the gate signal Vg2 applied to the gate of the synchronous rectification switching element 12 is generated. As will be described in detail later, high / low switching (switching timing) of the gate signal Vg1 for turning on / off the main switching element 11 is controlled by the duty of the PWM signal, and turns on / off the synchronous rectification switching element 12. High / Low switching (switching timing) of the gate signal Vg2 for this is governed by the duty of the PWM signal and the dead time detection result.

  FIG. 2 is a circuit diagram showing an example of a PWM signal generation circuit that may be used in the power supply device 10A shown in FIG. In FIG. 2, 201 and 202 are voltage controlled constant current sources, 203 to 206 are diodes, 207 is a capacitor, 208 and 209 are resistors, and 210 is a comparator.

  The PWM signal generation circuit 123 shown in FIG. 2 generates a pulse wave and a ramp wave that are synchronized with each other at the carrier frequency. That is, the PWM signal generation circuit 123 generates a pulse wave and a ramp wave such that the ramp wave rise time is on-duty and the ramp wave fall time is off-duty.

  In general, when the point A changes from Low (for example, 0 V) to High (for example, 5 V), a rising edge of a pulse wave is formed, and in synchronization with this, the current flow from the voltage controlled constant current source 201 to the capacitor 207 As a result, the potential at point B (ramp wave) gradually increases. When the potential at the point B reaches a predetermined potential, the comparator switches the point A to low, a falling edge of the pulse wave is formed, the capacitor 207 is discharged, and the potential at the point B is lowered (the ramp wave is reset). ) When the potential at point B drops to a predetermined value, point A changes from low to high again, and the same operation is repeated thereafter, and a pulse wave and a ramp wave synchronized with each other are periodically generated. The duty is made variable by controlling the voltages of the voltage controlled constant current sources 201 and 202.

  Next, the basic operation of the dead time control circuit 124A will be described with reference to FIGS.

  FIG. 3 is a circuit diagram showing an example of a dead time control circuit 124A that may be used in power supply device 10A shown in FIG. The dead time control circuit 124A mainly includes a dead time detector 150, an adjustment circuit 101, and a gate signal generation circuit. A first detector 130A and a second detector 132A are connected to the dead time detector 150 of the dead time control circuit 124A.

  4 and 5 are explanatory diagrams of the dead time control realized by the dead time control circuit 124A, and show output waveforms at points a to n in FIG.

  The pulse time c and the ramp wave i are input from the PWM signal generation circuit 123 to the dead time control circuit 124A.

  The ramp wave i is input to the inverting input of the comparator 122 and also input to the level shift circuits 102 and 103. The ramp wave “a” level-shifted by the level shift circuit 102 is input to the inverting input of the comparator 105 and the non-inverting input of the comparator 106. The ramp wave b level-shifted by the level shift circuit 103 is input to the non-inverting input of the comparator 107 and the inverting input of the comparator 108. Note that the comparators 105, 106, 107, and 108 preferably have characteristics having a hysteresis and a small offset.

  The pulse wave c is input to the non-inverting input of the comparator 122 and also input to the inverting input of the comparator 106 and the inverting input of the comparator 107. The pulse wave c is also input to the inverting circuit 104. In the inverting circuit 104, the pulse wave c is inverted with reference to 2.5V. The inverted pulse wave d is input to the non-inverting input of the comparator 105 and the non-inverting input of the comparator 108.

  The comparator 122 outputs a gate signal Vg1 for driving the main switching element 11 in accordance with the comparison result between the pulse wave c and the ramp wave i from the PWM signal generation circuit 123 (see FIG. 5B).

  The comparator 105 outputs a turn-on delay signal e in accordance with the comparison result between the ramp wave a level-shifted by the level shift circuit 102 and the inverted pulse wave d (see FIG. 4A).

  The comparator 106 outputs a turn-on advance signal f in accordance with a comparison result between the ramp wave a and the pulse wave c level-shifted by the level shift circuit 102 (see FIG. 4B).

  The comparator 107 outputs a turn-off advance signal g in accordance with the comparison result between the ramp wave b level-shifted by the level shift circuit 103 and the pulse wave c (see FIG. 4C).

  The comparator 108 outputs a turn-off delay signal h in accordance with the comparison result between the ramp wave b level-shifted by the level shift circuit 103 and the inverted pulse wave d (see FIG. 4D).

  In FIG. 4, for each signal, a waveform in which the delay or advance of the turn-on / off timing of the synchronous rectification switching element 12 does not occur with respect to the turn-off / on timing of the main switching element 11 (rightmost in the figure). On the other hand, waveforms for generating two types of turn delay or advance with different delay amounts or advance amounts are shown. Thus, by changing the level shift amount in the level shift circuits 102 and 103, the delay amount or the advance amount realized by the various signals e, f, g, and h can be freely changed.

  The adjustment circuit 101 adjusts the level shift amount in the level shift circuits 102 and 103 based on the dead time detection result from the dead time detector 150, and outputs an ON switching signal / OFF switching signal to synchronize. The switch timing of the rectifying switching element 12 is optimized.

  Specifically, in FIG. 3, the AND circuits 109 and 110, the OR circuit 113, and the NOT circuit 115 constitute a selector, and when the turn-on of the synchronous rectification switching element 12 is delayed, the ON switching signal m (FIG. 5). (See (A)) is set to Low, and the turn-on delay signal e is output from the OR circuit 113. On the other hand, when the turn-on of the synchronous rectification switching element 12 is advanced, the ON switching signal m (see FIG. 5A) is set to High, and the turn-on advance signal f is output from the OR circuit 113.

  Similarly, in FIG. 3, the AND circuits 111 and 112, the OR circuit 114, and the NOT circuit 116 constitute a selector, and the OFF switching signal n (FIG. 5 ( A) is set to Low, and the turn-off advance signal g is output from the OR circuit 114. On the other hand, when the turn-off of the synchronous rectification switching element 12 is delayed, the OFF switching signal n (see FIG. 5A) is set to High, and the turn-off delay signal h is output from the OR circuit 114.

  The NOT circuit 117 and the AND circuit 119 detect the rising edge of the turn-on delay signal e or the turn-on advance signal f selectively input as described above, and output the signal k (see FIG. 5A). Similarly, the NOT circuit 118 and the NOR circuit 120 detect the falling edge of the turn-off advance signal g or the turn-off delay signal h selectively input as described above, and output the signal l (see FIG. 5A). To do. The output of the AND circuit 119 is connected to the S terminal of the SR flip-flop 121, and the output of the NOR circuit 120 is connected to the R terminal of the SR flip-flop 121.

  The Q output of the SR flip-flop 121 becomes High (set) when the signal k input to the S terminal changes from Low to High, and becomes Low (reset) when the signal l input to the R terminal changes from Low to High. ) As a result, as shown in FIG. 5A, the gate signal Vg2 for driving the synchronous rectification switching element 12 is output from the Q output of the SR flip-flop 121 (see FIG. 5A).

  As described above, the dead time control circuit 124A shown in FIG. 3 can freely select whether to advance or delay the turn-on and turn-off timing of the synchronous rectification switching element 12 by the ON switching signal / OFF switching signal. By changing the level shift amount in the level shift circuits 102 and 103, the turn-on delay amount or advance amount and the turn-off delay amount or advance amount at that time can be freely changed.

  Next, operations of the dead time detector 150 and the adjustment circuit 101 will be described with reference to FIG. 6 shows, from above, the waveform of the gate-source voltage Vgs1 of the main switching element 11, the waveform of the gate-source voltage Vgs2 of the synchronous rectification switching element 12, the output waveform of the gate signal Vg1, and the output waveform of the gate signal Vg2. And the output waveform in each point o-r in FIG.

  As shown in FIGS. 6A and 6C, when the gate signal Vg1 changes from low to high, the driver 141 (see FIG. 1) gradually increases the gate-source voltage Vgs1 of the main switching element 11. Thereafter, since the mirror capacitance of the gate of the main switching element 11 is charged, a period in which the gate-source voltage Vgs1 does not change (mirror capacitance charging period) is entered. That is, as shown in FIG. 6A, the gate-source voltage Vgs1 once rises when the gate signal Vg1 goes from low to high, but until the mirror capacitance of the gate of the main switching element 11 is completely charged. It becomes almost constant. As shown in FIG. 6A, the gate-source voltage Vgs1 rises again when the charging of the mirror capacitance is completed. When the first detector 130A detects the end point of the mirror capacity charging, the first detector 130A outputs a signal to that effect to the dead time detector 150.

  As shown in FIGS. 6B and 6D, when the gate signal Vg2 goes low, the driver 142 (see FIG. 1) gradually decreases the gate-source voltage Vgs2 of the synchronous rectification switching element 12. When the second detector 132A detects a time point when the gate-source voltage Vgs2 falls below a predetermined threshold value, the second detector 132A determines that the synchronous rectification switching element 12 is turned off and outputs a signal to that effect to the dead time detector 150. . In this example, in consideration of the fact that the discharge phenomenon does not clearly appear in the waveform of the gate-source voltage Vgs2 as when the main switching element 11 is turned off when the synchronous rectification switching element 12 is turned off, as described above. Although the time point when the gate-source voltage Vgs2 falls below a predetermined threshold is detected, the OFF timing of the synchronous rectification switching element 12 is the end point of the discharge of the gate of the synchronous rectification switching element 12 to the mirror capacitance (see FIG. 6). It may be detected by detecting an arrow X1).

  The dead time detector 150 determines the mirror capacitance charging end timing tce of the gate of the main switching element 11 and the off timing of the synchronous rectification switching element 12 based on the detection results from the first detector 130A and the second detector 132A. The dead time Dt is detected by comparing with toff. That is, the dead time detector 150 detects the period from the off timing toff to the mirror capacity charging end timing tce as the dead time Td when the main switching element 11 is turned on.

  FIG. 6E shows a waveform representing the detection result of the dead time Td when the main switching element 11 is turned on. At the leftmost turn-on, the off timing toff is earlier than the mirror capacity charging end timing tce, and the positive dead time Td1 is detected. At the second turn-on from the left, the off timing toff is later than the mirror capacitance charging end timing tce, and a negative dead time Td3 (excessive cross) is detected. At the time of turn-on on the rightmost side, an optimum switching timing is detected in which the off timing toff coincides with the mirror capacity charging end timing tce and the dead time Td is zero.

  FIG. 6F shows an output waveform of the adjustment circuit 101 when the main switching element 11 is turned on. The output of the adjustment circuit 101 serves to adjust the level shift amount by the level shift circuit 103 as described above. At the time of the leftmost turn-on of the main switching element 11, the adjustment circuit 101 performs level shift as shown in FIG. 6 (F) to delay the turn-off of the synchronous rectification switching element 12 corresponding to the positive dead time Td1. The level shift amount of the ramp wave b in the circuit 103 is decreased according to the positive dead time Td1. As a result, as shown in FIG. 4D, the turn-off delay amount of the turn-off delay signal h is increased, and when the main switching element 11 is turned on next time (second turn-on from the left), FIG. As shown in B), the turn-off timing of the synchronous rectification switching element 12 is delayed as compared to the current turn-on time. When the main switching element 11 is turned on for the second time from the left, the adjusting circuit 101 corresponds to the negative dead time Td3 so as to advance the turn-off of the synchronous rectification switching element 12 as shown in FIG. The level shift amount of the ramp wave b in the level shift circuit 103 is increased according to the negative dead time Td3. As a result, as shown in FIG. 4D, the turn-off delay amount of the turn-off delay signal h is reduced, and when the main switching element 11 is turned on next time (at the rightmost turn-on), FIG. ), The turn-off timing of the synchronous rectification switching element 12 is advanced as compared with the current turn-on. When the rightmost turn of the main switching element 11 is turned on, the off timing toff of the synchronous rectification switching element 12 coincides with the mirror capacitance charging end timing tce of the main switching element 11, so that the adjustment circuit 101 is shown in FIG. As shown, the level shift amount of the ramp wave b in the level shift circuit 103 is maintained without being changed.

  On the other hand, as shown in FIGS. 6A and 6C, when the gate signal Vg1 changes from high to low, the driver 141 (see FIG. 1) gradually decreases the gate-source voltage Vgs1 of the main switching element 11. Let Thereafter, since the mirror capacitance of the gate of the main switching element 11 is discharged, a period in which the gate-source voltage Vgs1 does not change (mirror capacitance discharge period) is entered. That is, as shown in FIG. 6A, the gate-source voltage Vgs1 once decreases when the gate signal Vg1 changes from high to low, but until the mirror capacitance of the gate of the main switching element 11 is completely discharged. It becomes almost constant. As shown in FIG. 6A, the gate-source voltage Vgs1 drops again when the discharge from the mirror capacitance is completed. When the first detector 130A detects this mirror capacitance discharge start time, it outputs a signal to that effect to the dead time detector 150.

  As shown in FIGS. 6B and 6D, when the gate signal Vg2 becomes high, the driver 142 (see FIG. 1) gradually increases the gate-source voltage Vgs2 of the synchronous rectification switching element 12. When the second detector 132A detects a time point when the gate-source voltage Vgs2 exceeds a predetermined threshold value, the second detector 132A determines that the synchronous rectification switching element 12 is turned on and outputs a signal to that effect to the dead time detector 150. . The on-timing of the synchronous rectification switching element 12 may be detected by detecting a charging start time (see an arrow X2 in FIG. 6) of the mirror capacitance of the gate of the synchronous rectification switching element 12.

  The dead time detector 150 determines the mirror capacitance discharge start timing tds of the gate of the main switching element 11 and the on timing of the synchronous rectification switching element 12 based on the detection results from the first detector 130A and the second detector 132A. The dead time is detected by comparing with ton. That is, the dead time detector 150 detects the period from the mirror capacitance discharge start timing tds of the main switching element 11 to the on timing ton of the synchronous rectification switching element 12 as the dead time Td when the main switching element 11 is turned off. .

  FIG. 6G shows a waveform representing the detection result of the dead time Td when the main switching element 11 is turned off. At the leftmost turn-off time, the mirror capacitance discharge start timing tds is earlier than the on-timing ton, and a positive dead time Td2 is detected. At the second turn-on from the left, the on timing ton is earlier than the mirror capacitance discharge start timing tds, and a negative dead time Td4 (excessive cross) is detected. At the time of turn-on on the rightmost side, an optimum switching timing is detected in which the on timing ton coincides with the mirror capacitance discharge start timing tds and the dead time Td is zero.

  FIG. 6H shows an output waveform of the adjustment circuit 101 when the main switching element 11 is turned off. The output of the adjustment circuit 101 serves to adjust the level shift amount by the level shift circuit 103 as described above. At the time of the leftmost turn-off of the main switching element 11, the adjustment circuit 101 corresponds to the positive dead time Td2 so as to advance the turn-on of the synchronous rectification switching element 12, as shown in FIG. The level shift amount of the ramp wave a in the shift circuit 103 is reduced according to the positive dead time Td2. As a result, as shown in FIG. 4A, the turn-on delay amount of the turn-on delay signal e is reduced, and when the main switching element 11 is turned off next time (second turn-off from the left), FIG. As shown in B), the turn-on timing of the synchronous rectification switching element 12 is advanced compared to the current turn-off time. When the main switching element 11 is turned off for the second time from the left, the adjustment circuit 101 corresponds to the negative dead time Td4 (excessive cross) in order to delay the turn-on of the synchronous rectification switching element 12 as shown in FIG. As shown, the level shift amount of the ramp wave a in the level shift circuit 103 is increased according to the negative dead time Td4. As a result, as shown in FIG. 4A, the turn-on delay amount of the turn-on delay signal e is increased, and when the main switching element 11 is turned off next time (rightmost turn-off time), FIG. ), The turn-on timing of the synchronous rectification switching element 12 is delayed as compared to the current turn-off time. At the time of the rightmost turn-off of the main switching element 11, the on-timing ton of the synchronous rectification switching element 12 coincides with the mirror capacitance discharge start timing tds of the main switching element 11, so that the adjustment circuit 101 is shown in FIG. As shown, the level shift amount of the ramp wave a in the level shift circuit 103 is maintained without being changed.

  FIG. 7 is an operation waveform diagram showing a reduction effect of the through current and the recovery current realized by the operations of the dead time detector 150 and the adjustment circuit 101 shown in FIG. 7 shows, from above, the waveform of the gate-source voltage Vgs1 of the main switching element 11, the waveform of the gate-source voltage Vgs2 of the synchronous rectification switching element 12, and the current I1 flowing through the main switching element 11 (see FIG. 1). And the waveform of the current I2 (see FIG. 1) flowing through the synchronous rectification switching element 12. The waveforms in FIGS. 7A and 7B are the same as those in FIGS. 6A and 6B. That is, FIGS. 7C and 7D show waveforms of currents I1 and I2 realized by the dead time adjustment shown in FIG. 6, respectively.

  As shown in FIG. 7, when the main switching element 11 is turned on for the first time (the leftmost side in the figure), the off timing toff of the synchronous rectification switching element 12 is as described above from the mirror capacitance charging end timing tce of the main switching element 11. As a result, a recovery current is generated. When the main switching element 11 is turned on for the second time (the leftmost in the figure), the off timing toff of the synchronous rectification switching element 12 is too late to the mirror capacitance charging end timing tce of the main switching element 11 as described above. A large current flows. Similarly, when the main switching element 11 is turned off for the second time, since the on timing ton of the synchronous rectification switching element 12 is too earlier than the mirror capacitance discharge start timing tds of the main switching element 11 as described above, the through current is large. Flowing. On the other hand, when the main switching element 11 is turned on for the third time (the rightmost side in the figure), the off timing toff of the synchronous rectification switching element 12 coincides with the mirror capacitance charging end timing tce of the main switching element 11 as described above. While the through current is prevented from flowing largely, the recovery current is reduced by an appropriate cross. Similarly, when the main switching element 11 is turned off for the third time, since the on timing ton of the synchronous rectification switching element 12 coincides with the mirror capacitance discharge start timing tds of the main switching element 11 as described above, a large through current flows. Is prevented.

  As described above, according to the present embodiment, the off timing toff and the on timing ton of the synchronous rectification switching element 12 are respectively matched with the mirror capacity charging end timing tce and the mirror capacity discharge start timing tds of the main switching element 11. It is possible to reduce the recovery loss by optimally crossing the switching timing while preventing a large through current from flowing. In addition, since the surge voltage at the time of switching is reduced, it is possible to reduce the durability of the main switching element 11 and the like.

  FIG. 8 is a flowchart illustrating an example of a switching control method that can be executed by the power supply apparatus 10A of the present embodiment. The process shown in FIG. 8 relates to a switching control method when the main switching element 11 is turned on.

  When switching control is started in step 1, initial setting is performed in step 2. In the initial setting, the switching interval Ts (1) is set to the initial value x, and the flag f = −1 for shortening the switching interval Ts is set. The switching interval Ts is the time from when the synchronous rectification switching element 12 is turned off to when the main switching element 11 is turned on, that is, when the gate signal Vg2 is switched from High to Low, and the gate signal Vg1 is switched from Low to High. Time until switching. The switching interval Ts may be a negative value because it is necessary to cross the switching timing by changing the gate signal Vg1 from Low to High and then changing the gate signal Vg2 from High to Low. The initial value x may be a positive value on the safe side (a value that is not crossed). Note that “k” (= 0, 1, 2,...) Of the switching interval Ts (k) represents the k-th switching cycle, and the switching interval Ts (1) is the first switching cycle. Represents.

  In step 3, a dead time Td when switching control is executed based on the current switching interval Ts (k) is detected. That is, a dead time Td (= tce−toff), which is a difference time from the mirror capacitor charging end timing tce of the gate of the main switching element 11 to the off timing toff of the synchronous rectification switching element 12, is detected, and its absolute value Is held as the current value Tdhold (NEW).

  In step 4, the current value Tdhold (NEW) is held as the previous value Tdhold (OLD).

  In step 5, the switching interval Ts changing process is executed. At this time, when the value of the flag is “−1”, the current switching interval Ts (k) is set to a value obtained by subtracting the predetermined value α from the previous switching interval Ts (k−1). That is, Ts (k) = Ts (k−1) −α. On the other hand, when the value of the flag is “1”, the current switching interval Ts (k) is set to a value obtained by adding the predetermined value α to the previous switching interval Ts (k−1). That is, Ts (k) = Ts (k−1) + α. If this time is the first routine, the flag f = −1 is set in step 2, so that Ts (2) = x−α.

  In step 6, the dead time Td (k) when the switching interval Ts (k) set in step 5 is used is detected, and the absolute value thereof is held as the current value Tdhold (NEW).

  In step 7, the current value Tdhold (NEW) of the dead time Td detected in step 6 is compared with the previous value Tdhold (OLD) of the dead time Td held in step 4. As a result of the comparison, if the current value Tdhold (NEW) is smaller than the previous value Tdhold (OLD), the process proceeds to step 8; otherwise, the process proceeds to step 9.

In step 8, a flag f = −1 for shortening the switching interval Ts is set, and the process returns to step 4. Therefore, in the subsequent processing in step 5, that is, in the next switching period (k + 1), the switching interval Ts (k + 1) is decreased by the predetermined value α.
That is, Ts (k + 1) = Ts (k) −α.

In step 9, a flag f = 1 for increasing the switching interval Ts is set, and the process returns to step 4. Therefore, in the subsequent processing in step 5, that is, in the next switching period (k + 1), the switching interval Ts (k + 1) is increased by the predetermined value α.
That is, Ts (k + 1) = Ts (k) + α.

  As described above, in this embodiment, when the dead time detected when the main switching element 11 is turned on decreases, the switching interval Ts at the next turn-on is decreased by the predetermined time width α, and the dead time increases. In this case, the switching interval Ts at the next turn-on is increased by a predetermined time width α. Thereby, since the switching interval is optimized so that the dead time becomes zero, switching control with little switching loss can be realized.

  In the example shown in FIG. 8, each time the main switching element 11 is turned off, the detected dead time is compared with the previous value, and the switching interval at the next main switching element turn-off in the direction in which the dead time decreases. Although Ts is determined, every time the main switching element 11 is turned off, the detected dead time is compared with zero, and the switching interval Ts when the main switching element is turned off next time so that the dead time becomes zero. May be determined.

  The example shown in FIG. 8 relates to the switching control method when the main switching element 11 is turned on, but the same may be applied to the switching control method when the main switching element 11 is turned off. That is, the difference time from the on timing ton of the synchronous rectification switching element 12 to the mirror capacitance discharge start timing tds of the gate of the main switching element 11 is detected as the dead time Td (= ton−tds), and the dead time Td. May be adjusted so that the synchronous rectification switching element 12 is turned off (the timing at which the gate signal Vg2 is switched from High to Low) so that becomes smaller than the previous value (or becomes zero). For example, in the first switching, when the gate signal Vg2 is still Low at the mirror capacitance discharge start timing tds of the gate of the main switching element 11, the gate signal Vg2 may be immediately switched from Low to High. In this case, the switching interval Ts after the next cycle may be determined with the switching interval Ts at that time as the initial value x.

  FIG. 9 is a main circuit diagram illustrating a power supply device 10B according to the second embodiment. The second embodiment is mainly different from the first embodiment described above in that a load current detector 134B that detects a current flowing through a load is provided instead of the second detector 132A. Hereinafter, the same configurations as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  As shown in FIG. 9, a first detector 130B and a load current detector 134B are connected to the dead time control circuit 124B. The load current detector 134B shown in FIG. 9 detects the voltage after the smoothing reactor (the output voltage of the DC-DC converter) as a load current. The first detector 130B detects the start timing tcs of the mirror capacitance charging period of the main switching element 11 when the main switching element 11 is turned on. The first detector 130 </ b> B detects the start timing tds of the mirror capacitance discharge period of the main switching element 11 based on the gate-source voltage Vgs <b> 1 of the main switching element 11 when the main switching element 11 is turned off.

  FIG. 10 is a circuit diagram schematically showing an example of a dead time control circuit 124B that may be used in the power supply device 10B shown in FIG. The dead time control circuit 124B mainly includes an adjustment circuit 301 and a gate signal generation circuit including a Vg1 circuit 301 and a Vg2 circuit 303. Based on the PWM signal from the PWM signal generation circuit 123, the Vg1 circuit 301 generates a gate signal Vg1 that is applied to the gate of the main switching element 11. Based on the PWM signal from the PWM signal generation circuit 123 and the instruction signal (delay time) from the adjustment circuit 301, the Vg2 circuit 303 generates a gate signal Vg2 to be applied to the gate of the synchronous rectification switching element 12. .

  FIG. 11 is a diagram illustrating main operation waveforms of the power supply device 10B according to the second embodiment. FIG. 11 shows operation waveforms when an optimum switching timing with zero dead time Td is realized. From the top, the waveform of the gate-source voltage Vgs1 of the main switching element 11, the synchronous rectification switching element 12 is shown. The waveform of the gate-source voltage Vgs2, the output waveform of the gate signal Vg1, the output waveform of the gate signal Vg2, and the waveform of the pulse wave for setting the delay time are shown.

  When the main switching element 11 is turned on, the dead time control circuit 124B performs synchronous rectification after a predetermined delay time Tdel from the mirror capacitance charging end timing tce of the main switching element 11 based on the detection result from the first detector 130B. In order to turn off the switching element 12, the gate signal Vg2 is switched from High to Low. As shown in FIG. 11, the delay time Tdel is set at the mirror capacitor charging end timing tce of the main switching element 11 at the off timing of the synchronous rectification switching element 12 (the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is predetermined). Are set so as to coincide with each other. The delay time Tdel is a relationship between the mirror capacitance charging period and the time from when the gate signal Vg2 becomes low until the gate-source voltage Vgs2 of the synchronous rectification switching element 12 falls below a predetermined threshold, through a test or the like in advance. It may be a fixed value that is derived and set based on the derived relationship. However, preferably, as in the present embodiment, the delay time Tdel is varied according to the load current detected by the load current detector 134B. This is because the mirror capacity charging period of the synchronous rectification switching element 12 changes depending on the magnitude of the current flowing through the main switching element 11 (that is, the magnitude of the load current). Similarly, in this case, the relationship between the mirror capacitance charging period and the time from when the gate signal Vg2 goes low until the gate-source voltage Vgs2 of the synchronous rectification switching element 12 falls below a predetermined threshold is tested in advance. For example, the delay time Tdel may be varied based on the derived relationship (for example, held by a map).

  As shown in FIG. 11, when the main switching element 11 is turned off, the dead time control circuit 124B sets the mirror capacitance discharge start timing tds of the gate of the main switching element 11 based on the detection result from the first detector 130B. Upon detection, the gate signal Vg2 is immediately switched from Low to High.

  FIG. 12 is an operation waveform diagram illustrating a reduction effect of the through current and the recovery current realized by the power supply device 10B according to the second embodiment. FIG. 12 shows an operation waveform when the optimum switching timing with zero dead time Td is realized. From the top, the waveform of the gate-source voltage Vgs1 of the main switching element 11 and the delay time setting pulse are shown. Waveform, waveform of gate-source voltage Vgs2 of synchronous rectification switching element 12, waveform of current I1 flowing through main switching element 11 (see FIG. 9), and current I2 flowing through synchronous rectification switching element 12 (FIG. 9).

  As shown in FIG. 12, when the main switching element 11 is turned on, the OFF timing toff of the synchronous rectification switching element 12 is set to the mirror capacitance charging end timing tce of the main switching element 11 by appropriately setting the delay time Tdel as described above. Therefore, a large amount of through current is prevented and a recovery current is reduced by appropriate crossing. Similarly, when the main switching element 11 is turned off, the mirror capacitance discharge start timing tds of the gate of the main switching element 11 is detected as described above, and the turn-on timing of the synchronous rectification switching element 12 is determined. Good switching can be realized.

  According to the present embodiment, since there is no means for detecting the gate-source voltage Vgs2 of the synchronous rectification switching element 12 as described above, the mirror of the nominal main switching element 11 as in the first embodiment described above. Although the off timing of the synchronous rectification switching element 12 cannot be feedback-adapted to the capacity charging end timing tce, it is simple and low that it is not necessary to detect the gate-source voltage Vgs2 of the synchronous rectification switching element 12. The cost structure can reduce recovery loss by optimally crossing the switching timing while preventing large through current from flowing.

  In this embodiment, when the delay time Tdel is set excessively, and when the gate signal Vg2 is still High at the mirror capacitance charge end timing tce of the gate of the main switching element 11, Since the cross is excessive, the gate signal Vg2 may be immediately switched from High to Low.

  FIG. 13 is a main circuit diagram illustrating a power supply device 10C according to the third embodiment. The third embodiment is mainly different from the first embodiment described above in that the first detector 130A is eliminated. Hereinafter, the same configurations as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified. A second detector 132C is connected to the dead time control circuit 124C.

  Similarly to the dead time control circuit 124B shown in FIG. 10, the dead time control circuit 124C includes an adjustment circuit 301 and a gate signal generation circuit including a Vg1 circuit 301 and a Vg2 circuit 303. Based on the PWM signal from the PWM signal generation circuit 123, the Vg1 circuit 301 generates a gate signal Vg1 that is applied to the gate of the main switching element 11. Based on the PWM signal from the PWM signal generation circuit 123 and the instruction signal (delay time) from the adjustment circuit 301, the Vg2 circuit 303 generates a gate signal Vg2 to be applied to the gate of the synchronous rectification switching element 12. .

  FIG. 14 shows a parasitic component equivalent circuit of the synchronous rectification switching element 12. In FIG. 14, reference numeral 101a represents a gate-drain capacitance, reference numeral 101b represents a gate-source capacitance, reference numeral 101c represents a drain-source capacitance, 101d represents a parasitic diode, Reference symbols G, D, and S represent a gate terminal, a drain terminal, and a source terminal, respectively. The rise or fall of the gate-source voltage Vgs2, which will be described later, is caused by charging or discharging of these parasitic capacitances 101a, 101b, and 101c that occur when the potential between the drain and source rises or falls.

  FIG. 15 is a diagram illustrating main operation waveforms of the power supply device 10C according to the third embodiment. FIG. 15 shows operation waveforms when the optimum switching timing with zero dead time Td is realized. From the top, the waveform of the gate-source voltage Vgs1 of the main switching element 11, the switching element 12 for synchronous rectification, and the like. , The waveform of the gate-source voltage Vgs2 of the current, the waveform of the current I1 flowing through the main switching element 11 (see FIG. 9), the waveform of the midpoint voltage (intersection voltage) V1 between the main switching element 11 and the synchronous rectification switching element 12, The output waveform of the gate signal Vg1, the output waveform of the gate signal Vg2, and the waveform of the pulse wave for setting the delay time are shown.

  As shown in FIGS. 15A and 15E, when the gate signal Vg1 changes from low to high, the driver 141 (see FIG. 13) gradually increases the gate-source voltage Vgs1 of the main switching element 11. When the gate-source voltage Vgs1 rises, the current I1 starts to rise from about 0A as shown in FIG. Along with this, as shown in FIG. 15C, the midpoint voltage V1 increases. When the midpoint voltage V1 rises, the gate-source voltage Vgs2 of the synchronous rectification switching element 12 increases according to the parasitic capacitance of the synchronous rectification switching element 12, as shown in FIG. The second detector 132C monitors the gate-source voltage Vgs2 of the synchronous rectification switching element 12 when the main switching element 11 is turned on, and the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is a predetermined threshold value. If it exceeds, it is determined that the gate-source voltage Vgs2 has risen, and a signal to that effect is output to the dead time control circuit 124C. The predetermined threshold value is larger than the high output gate voltage of the synchronous rectification switching element 12, and is set to an appropriate value according to the magnitude of the voltage that can increase when the lifting is performed.

  When the rise of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected, the dead time control circuit 124C switches the gate signal Vg2 from High to Low in order to turn off the synchronous rectification switching element 12. More preferably, as shown in FIG. 15 (F), the dead time control circuit 124C performs the synchronous rectification switching after a predetermined delay time Tdel from the time when the rise of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected. In order to turn off the element 12, the gate signal Vg2 is switched from High to Low.

  When the gate signal Vg2 is switched from High to Low, the driver 142 (see FIG. 13) gradually lowers the gate-source voltage Vgs2 of the synchronous rectification switching element 12. As shown in FIG. 15B and FIG. 15D, the gate-source voltage Vgs2 is (preferably) before the current I1 starts to increase from about 0A and before it becomes substantially the same as the coil current IL. Is reduced to a voltage that turns off the synchronous rectification switching element 12 at a timing when the current becomes substantially the same as the coil current IL. That is, the delay time Tdel is preferably switched for synchronous rectification at the mirror capacitance charge end timing tce (the timing at which the current becomes substantially the same as the coil current IL) of the main switching element 11 based on the same concept as in the second embodiment. The off-timing of the element 12 (when the gate-source voltage Vgs2 of the synchronous rectification switching element 12 falls below a predetermined threshold) is set to coincide. The delay time Tdel is the time from when the rise of the gate-source voltage Vgs2 is detected to the time when the current I1 becomes the coil current IL, and between the gate and source of the synchronous rectification switching element 12 after the gate signal Vg2 becomes low. The relationship with the time until the voltage Vgs2 falls below the predetermined threshold may be derived in advance by a test or the like, and may be a fixed value set based on the derived relationship. Since the time until the current I1 becomes the coil current IL varies depending on the load current, the delay time Tdel is set to a value corresponding to the load current and the circuit delay.

  Similarly, as shown in FIGS. 15A and 15E, when the gate signal Vg1 changes from high to low, the driver 142 (see FIG. 13) gradually increases the gate-source voltage Vgs1 of the main switching element 11. Lower. Thereafter, as shown in FIG. 15C, the midpoint voltage V1 decreases. When the midpoint voltage V1 decreases, the gate-source voltage Vgs2 of the synchronous rectification switching element 12 increases according to the parasitic capacitance of the synchronous rectification switching element 12, as shown in FIG. The second detector 132C monitors the gate-source voltage Vgs2 of the synchronous rectification switching element 12 when the main switching element 11 is turned off, and the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is a predetermined threshold value. If it falls below, it is determined that the gate-source voltage Vgs2 has dropped, and a signal to that effect is output to the dead time control circuit 124C. The predetermined threshold value is smaller than the low output gate voltage of the synchronous rectification switching element 12, and is set to an appropriate value according to the magnitude of the voltage that can be reduced when the switch is lowered.

  When the fall of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected, the dead time control circuit 124C turns on the synchronous rectification switching element 12 as shown in FIG. The gate signal Vg2 is switched from Low to High.

  According to the present embodiment, when the main switching element 11 is turned on, the rising of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected as described above, and the off timing toff of the synchronous rectification switching element 12 is set. Since the adjustment is made so as to coincide with the mirror capacitance charging end timing tce of the main switching element 11, a large amount of through current is prevented, and the recovery current is reduced by appropriate crossing. Similarly, when the main switching element 11 is turned off, the fall of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected as described above, and the turn-on timing of the synchronous rectification switching element 12 is determined. Efficient switching can be realized.

  In this embodiment, when the load current is small, it is difficult to detect the lifting and lowering, and the above lifting and lowering are performed only when the load current is larger than a predetermined value. Switching control based on the detection result may be performed. In addition, in the same way, it may be combined with other on / off switching conditions. In this case, only when the lifting and the lowering are detected, the High / Lo switching of the gate signal Vg2 is realized based on the detection result. When the load current is small and no lifting or lowering is detected, the High / Lo switching of the gate signal Vg2 may be realized based on other on / off switching conditions.

  FIG. 16 is a main circuit diagram illustrating a power supply device 10D according to the fourth embodiment. The fourth embodiment is mainly different from the third embodiment described above in that a load current detector 134D is added. Hereinafter, the same configurations as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  As shown in FIG. 16, a second detector 132D and a load current detector 134D are connected to the dead time control circuit 124D. The load current detector 134D shown in FIG. 16 detects the voltage after the smoothing reactor (the output voltage of the DC-DC converter) as a load current. The second detector 132D detects the start timing tcs of the mirror capacitance charging period of the main switching element 11 when the main switching element 11 is turned on. The second detector 132D detects a rise in the gate-source voltage Vgs2 of the synchronous rectification switching element 12 when the main switching element 11 is turned on, and synchronous rectification when the main switching element 11 is turned off. The falling of the gate-source voltage Vgs2 of the switching element 12 is detected.

  When the rise of the gate-source voltage Vgs2 of the synchronous rectification switching element 12 is detected, the dead time control circuit 124D is configured to turn off the synchronous rectification switching element 12 after a predetermined delay time Tdel from the detection time. The gate signal Vg2 is switched from High to Low. In the present embodiment, the dead time control circuit 124D varies the predetermined delay time Tdel according to the load current detected by the load current detector 134D. This is because the mirror capacitance charging period of the synchronous rectification switching element 12 (the time from when the current I1 starts to rise from about 0A until it becomes substantially the same as the coil current IL) is the magnitude of the current flowing through the main switching element 11. This is because it varies depending on (that is, the magnitude of the load current). In this case, the time from when the current I1 starts to rise from about 0A until it becomes substantially the same as the coil current IL, and the gate-source voltage Vgs2 of the synchronous rectification switching element 12 after the gate signal Vg2 becomes low is The relationship with the time until the value falls below the predetermined threshold value may be derived in advance by changing the magnitude of the load current by a test or the like, and may be varied based on the derived relationship (for example, held by a map).

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, in the above-described embodiment, the main switching element 11 and the synchronous rectification switching element 12 are made of MOSFETs, but the main switching element 11 ′ and the synchronous rectification switching element 12 ′ are, as shown in FIG. It may consist of IGBT (Insulated Gate Bipolar Transistor). In this case, in the above description, the “gate-source voltage Vgs1” of the main switching element 11 and the “gate-source voltage Vgs2” of the synchronous rectification switching element 12 are the same as the “gate-emitter voltage” of the main switching element 11 ′. The voltage Vge1 ”and the“ gate-emitter voltage Vge2 ”of the switching element 12 ′ for synchronous rectification are respectively replaced (read). Even with such a configuration using an IGBT, it is possible to reduce the recovery loss by optimally crossing the switching timing while preventing a large amount of through current from flowing as in the above-described embodiment.

  In the above-described embodiment, the switching timing of the main switching element 11 that determines the output voltage VOUT is governed only by the duty of the PWM signal, and the adjustment of the dead time Td is exclusively performed by the switching of the synchronous rectification switching element 12. It is realized by changing only the timing. Thereby, the dead time Td can be adjusted without changing the duty of the PWM signal. In contrast, in the configuration in which the switching time of the main switching element 11 is varied to adjust the dead time Td, it is necessary to readjust the duty adjusted by the PWM signal, and the feedforward control and the feedback control are performed. Characteristics are degraded. However, the present invention does not exclude such a configuration. Even in such a configuration, it is possible to optimally cross the switching timing and reduce the recovery loss while preventing a large amount of through current from flowing.

It is a main circuit diagram showing one embodiment of a power supply device 10A related to a switching element control device according to the present invention. 3 is a circuit diagram illustrating an example of a PWM signal generation circuit 123. FIG. FIG. 2 is a circuit diagram showing an example of a dead time control circuit 124A that may be used in the power supply device 10A shown in FIG. It is a figure which shows the output waveform in each point at the time of the dead time control implement | achieved by the dead time control circuit 124A (the 1). It is a figure which shows the output waveform in each point at the time of the dead time control implement | achieved by the dead time control circuit 124A (the 2). It is a figure which shows the operation | movement waveform of the dead time detector 150 and the adjustment circuit 101. FIG. FIG. 7 is an operation waveform diagram showing a through current and recovery current reduction effect realized by the operations of the dead time detector 150 and the adjustment circuit 101 shown in FIG. 6. It is a flowchart which shows an example of the switching control method which can be performed by 10 A of power supply devices of a present Example. FIG. 6 is a main circuit diagram showing a power supply device 10B according to a second embodiment. FIG. 10 is a circuit diagram schematically showing an example of a dead time control circuit 124B that may be used in the power supply device 10B shown in FIG. 9. It is a figure which shows the main operation | movement waveforms of the power supply device 10B in connection with Example 2. FIG. It is an operation | movement waveform diagram which shows the reduction | restoration effect | action of the penetration current and recovery current implement | achieved by the power supply device 10B in connection with Example 2. FIG. FIG. 10 is a main circuit diagram showing a power supply device 10C according to a third embodiment. 3 is a diagram illustrating a parasitic component equivalent circuit of the synchronous rectification switching element 12. FIG. It is a figure which shows the main operation | movement waveforms of the power supply device 10C in connection with Example 3. FIG. FIG. 10 is a main circuit diagram showing a power supply device 10D according to a fourth embodiment. It is a main circuit diagram which shows one Example of the power supply device which uses IGBT as a switching element.

Explanation of symbols

10A to 10D Power supply device 11 Main switching element 12 Synchronous rectification switching element 123 PWM signal generation circuit 124A to 124D Dead time control circuit 130A, 130B First detector 132A, 132C, 132D Second detector 134B, 134D Load current detector

Claims (11)

A first switching element and a second switching element connected in series;
Gate-source voltage detection means for detecting a voltage between the gate and source of the first switching element ;
A second gate-source voltage detecting means for detecting a voltage between the gate and the source of the second switching element ;
Based on the output result of the gate-source voltage detection means, when the first switching element is turned on, the gate-source voltage of the first switching element rises to become substantially constant and then rises again. Detect the timing,
Based on the output result of the second gate-source voltage detection means, the timing at which the gate-source voltage of the second switching element at the time of turn-off of the second switching element falls below a predetermined value is detected,
When the first switching element is turned on, the gate-source voltage of the first switching element rises to become substantially constant and then rises again, and the second restarting timing when the second switching element is turned off. A switching element control device that adjusts the turn-off timing of the second switching element so that the timing at which the gate-source voltage of the switching element falls below a predetermined value substantially matches . A first switching element and a second switching element connected in series;
Gate-source voltage detecting means for detecting a voltage between the gate and source of the first switching element;
Based on the output result of the gate-source voltage detecting means, the voltage-to-voltage period starts when the gate-source voltage of the first switching element at the time of turn-on of the first switching element temporarily becomes substantially constant during its rise. Detect the timing,
After a predetermined delay time from the constant voltage period start timing the detected has passed, and switches the gate signals for the second switching element from High to Lo, the switching element control device. If the gate-source voltage of the first switching element, which has become temporarily substantially constant during the rise, rises again before the predetermined delay time elapses, the gate signal for the second switching element is changed from High. The switching element control device according to claim 2 , wherein the switching element control device is switched to Lo. Load current detection means for detecting the current flowing through the load,
The switching element control device according to claim 2 or 3 , wherein the predetermined delay time is changed according to a magnitude of a load current. A first switching element and a second switching element connected in series;
Gate-source voltage detection means for detecting a voltage between the gate and source of the first switching element ;
A second gate-source voltage detecting means for detecting a voltage between the gate and the source of the second switching element ;
Based on the output result of the gate-source voltage detection means, the fixed-voltage period starts when the gate-source voltage of the first switching element at the time of turn-off of the first switching element temporarily becomes substantially constant during the fall. Detect the timing,
Based on the output result of the second gate-source voltage detection means, the timing at which the gate-source voltage of the second switching element rises when the second switching element is turned on and a timing exceeding a predetermined value is detected,
When the first switching element is turned off, the gate-source voltage of the first switching element temporarily becomes substantially constant in the middle of the decrease, and the voltage constant period start timing is second, and the second switching element is turned on. A switching element control device, characterized by adjusting a turn-on timing of the second switching element so that a timing exceeding a predetermined value after the gate-source voltage of the switching element rises substantially matches . 6. The switching element control device according to claim 5 , wherein if the gate signal for the second switching element is Lo even when the voltage constant period start timing occurs , the gate signal for the second switching element is switched from Lo to High. A first switching element and a second switching element connected in series;
Gate-source voltage detecting means for detecting a voltage between the gate and source of the second switching element;
Based on the output result of the gate-source voltage detecting means, the second switching element is turned on after a predetermined delay time from the time when the gate-source voltage of the second switching element becomes larger than a predetermined value when the first switching element is turned on . A switching element control device, wherein the gate signal for the switching element is switched from High to Lo . A first switching element and a second switching element connected in series;
Gate-source voltage detecting means for detecting a voltage between the gate and source of the second switching element;
Based on the output result of the gate-source voltage detection means, when the gate-source voltage of the second switching element becomes smaller than a predetermined value when the first switching element is turned off, the gate for the second switching element is A switching element control device, wherein the signal is switched from Lo to High . The switching element control device according to any one of claims 1 to 8 , which is used for voltage control in a synchronous rectification type DC-DC converter.
The switching element control device, wherein the first switching element is a main switching element, and the second switching element is a synchronous rectification switching element. It said first and second switching elements is a MOSFET, the switching element control device according to any one of claims 1-9. Said first and second switching elements are IGBT (Insulated Gate Bipolar Transistor), the gate-source voltage is replaced with the gate-emitter voltage, according to any one of claims 1-9 Switching element control device.

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