JP5537683B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  As a power supply circuit, an output voltage lower than the input voltage can be obtained by alternately turning on and off a high-side switching element connected between the input terminal and the inductor and a low-side switching element connected between the inductor and the ground. There is a DC-DC converter that outputs to the subsequent stage of the LC filter (for example, Patent Document 1).

  An inductor is often used as an external component for a power supply IC in which a switching element, a driver, and the like are formed as an integrated circuit. In this case, the drain terminal of the low-side switching element becomes an external terminal of the power supply IC, and ESD (Electro The power supply IC is required not to be destroyed even if an ESD surge jumps into an external terminal.

JP 2002-281744 A

  A semiconductor device with excellent reliability is provided.

According to the embodiment, the semiconductor device includes a first switching element connected between the input voltage line and the inductive load, and a second connection connected in parallel between the inductive load and the reference voltage line. And a switching element.
When 0 <(threshold voltage of the second switching element) <(on-voltage of a built-in diode of the second switching element) and the gate voltage of the second switching element is a reference potential, the first When the potential at the connection point between the switching element and the second switching element is greater than − (threshold voltage of the second switching element), the second switching element is turned off, and the potential at the connection point is When it becomes smaller than-(threshold voltage of the second switching element), the second switching element is turned on regardless of the level of the gate voltage of the second switching element .

The schematic diagram which shows the structural example of the DC-DC converter using the semiconductor device which concerns on embodiment of this invention. FIG. 3 is a schematic view illustrating the cross-sectional structure of a main part of a second switching element M2 in FIG. The schematic diagram which illustrates the principal part cross-section of the 3rd switching element M3 in FIG. FIG. 4 is a characteristic diagram showing a relationship between a first main electrode-second main electrode voltage Vds and a drain current Ids in the third switching element M3 shown in FIG. 3; FIG. 6 is a schematic cross-sectional view showing another specific example of the third switching element M3 in FIG. 1. FIG. 7 is a schematic cross-sectional view showing still another specific example of the third switching element M3 in FIG. FIG. 2 is a waveform diagram of switching elements M1 to M3 and inductor current IL during normal operation and light load in the DC-DC converter shown in FIG. FIG. 7B is a waveform diagram showing a specific example in which the operation timings of the second switching element M2 and the third switching element M3 at a light load are different. The schematic diagram which shows the structural example of the DC-DC converter using the semiconductor device which concerns on other embodiment of this invention. The figure which shows the operation timing of the switching elements M1, M2, and M4 in the DC-DC converter shown in FIG. 9, and the waveform of the inductor current IL. The schematic diagram which shows the structural example of the DC-DC converter using the semiconductor device which concerns on further another embodiment of this invention. FIG. 12 is a waveform diagram of M1, M2, g2, Vx, and IL in the DC-DC converter shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The semiconductor device according to the embodiment of the present invention has a plurality of switching elements and can be used for, for example, a DC-DC converter.
FIG. 1 is a schematic diagram illustrating a configuration example of the DC-DC converter.

  This DC-DC converter includes a first switching element M1 that is a high-side switching element, second and third switching elements M2 and M3 that are low-side switching elements, and gates of the first switching element M1. A driver 5 for driving, a driver 6 for driving the gate of the second switching element M2, a driver 7 for driving the gate of the third switching element M3, a control circuit 9 for controlling these drivers 5 to 7, and an induction Inductor L, which is a capacitive load, capacitor C, and detection circuit 8 are provided.

  The DC-DC converter is a step-down DC-DC converter (buck) that outputs an output voltage Vo (average) lower than the input voltage Vin to the load 10 by alternately turning on and off the high-side switching element and the low-side switching element. converter).

  In the elements shown in FIG. 1, the first switching element M1, the second switching element M2, the third switching element M3, the drivers 5 to 7, the control circuit 9, and the detection circuit 8 are integrated into one chip (or one package). The power supply IC is configured.

  The switching elements M1, M2, and M3 are MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), which are respectively supplied by gate drive signals g1, g2, and g3 supplied from the control circuit 9 via drivers 5, 6, and 7, respectively. On / off.

  The first switching element M1 and the inductor L are connected in series between the input voltage line 11 to which the input voltage Vin is applied and the output terminal 12. The first switching element M1 is, for example, a P-type MOSFET, and has a source terminal connected to the reference voltage line 11 and a drain terminal connected to the inductor L.

  A second switching element M2 and a third switching element M3 are connected in parallel between a connection point between the first switching element M1 and the inductor L and a reference voltage line (for example, a ground line).

  The second switching element M2 and the third switching element M3 are, for example, N-type MOSFETs, each drain terminal is connected to the drain terminal of the first switching element M1 and the inductor L, and each source terminal is a ground line. It is connected to the.

  A connection point between the inductor L and the output terminal 12 is grounded via a smoothing capacitor C for preventing the output voltage from fluctuating greatly in a short time.

  In addition, a detection circuit 8 that detects a potential at a connection point between the low-side switching elements (second switching element M2 and third switching element M3) and the inductor L is provided. Specifically, the detection circuit 8 is a comparator that compares the potential at the connection point between the low-side switching element and the inductor L with the reference potential Vref.

  FIG. 7A is a waveform diagram of the gate drive signals g1 to g3 and the inductor current IL during normal operation that is not under light load in the DC-DC converter shown in FIG. IL flows from the inductor L toward the load 10 when positive, and flows from the inductor L to the ground via the low-side switching element when negative.

  Gate drive signals g1 and g2 having substantially inverted phases are supplied to the gate terminal of the first switching element M1 and the gate terminal of the second switching element M2. The third switching element M3 is turned on / off at the same timing as the second switching element M2. Alternatively, the third switching element M3 may be always off during normal operation.

  When the first switching element M1 is on and the second switching element M2 and the third switching element M3 are off, the input voltage line 11 is connected to the load 10 via the first switching element M1 and the inductor L. Current is supplied. At this time, the inductor current IL increases and energy is accumulated in the inductor L.

  When the first switching element M1 is turned off and the second switching element M2 is turned on, the inductor L releases the accumulated energy, and the load 10 passes from the ground via the second switching element M2 and the inductor L. Is supplied with current. At this time, the third switching element M3 may be off. As will be described later, since the current drive capability when the third switching element M3 operates as a MOSFET is sufficiently smaller than that of the second switching element M2, it is almost the electrical characteristics of the second switching element M2. This is because the characteristics of the converter are determined.

  The output voltage Vo is monitored, and the on / off duty of the first switching element M1 and the second switching element M2 is controlled by the control circuit 9 so that the output voltage Vo becomes a predetermined target voltage.

  Further, when the first switching element M1 and the second switching element M2 are simultaneously turned on, a very large current (through current) flows from the input voltage line 11 to the ground via the switching elements M1 and M2. become. In order to avoid this, when setting the on / off duty of the switching elements M1, M2, a dead time is set, which is a period during which both the switching elements M1, M2 are off. For the same reason, the dead time is set so that the first switching element M1 and the third switching element M3 are not simultaneously turned on.

  Next, specific structures of the second switching element M2 and the third switching element M3 will be described. In the following specific example, an example in which silicon is used as a semiconductor material will be described. However, not only silicon but also other semiconductor materials can be used. Although the first conductivity type is described as P type and the second conductivity type is described as N type, the first conductivity type may be N type and the second conductivity type may be P type.

  FIG. 2 is a schematic diagram illustrating a cross-sectional structure of a main part of the second switching element M2.

In the second switching element M2, a P ⁺ -type contact layer 25, an N ⁺ -type source layer 22, an N-type drift layer 24, and an N ⁺ -type drain layer 23 are formed on the surface layer portion of the P ⁻ -type layer 21. Furthermore, it has an LDMOS (Lateral Diffusion Metal-Oxide-Semiconductor) structure in which a first main electrode 28, a second main electrode 27, and a gate electrode 29 are provided on the surface.

  The source layer 22 and the drain layer 23 are provided apart from each other, and a drift layer 24 is provided in contact with the drain layer 23 therebetween. The drift layer 24 has a lower impurity concentration than the source layer 22 and the drain layer 23.

A gate electrode 29 is provided on the surface of the P ⁻ -type layer 21 between the source layer 22 and the drift layer 24 via a gate insulating film 26. A P ⁺ -type contact layer 25 having an impurity concentration higher than that of the P ⁻ -type layer 21 is provided in contact with the source layer 22 at the end of the source layer 22 opposite to the gate electrode 29 side.

A second main electrode 27 functioning as a source electrode is provided on the surfaces of the source layer 22 and the contact layer 25. As a result, the source layer 22 is electrically connected to the second main electrode 27, and the P ⁻ -type layer 21 is set to the source potential via the contact layer 25. A first main electrode 28 that functions as a drain electrode is provided on the surface of the drain layer 23, and the drain layer 23 is electrically connected to the first main electrode 28.

When a predetermined gate voltage is applied to the gate electrode 29, an N-type inversion layer (channel) is formed in the surface layer portion of the P ⁻ -type layer 21 below the gate electrode 29, and the drain layer 23, drift layer 24, channel and source layer are formed. A drain current flows between the first main electrode 28 and the second main electrode 27 via 22.

  A switching element used in a DC-DC converter is required to have low on-resistance and high speed. In particular, to achieve high speed, it is important to reduce the gate-drain capacitance.

In the structure shown in FIG. 2, the gate-drain capacitance is made as small as possible by self-aligning the drift layer 24 using the gate electrode 29 as a mask. That is, the drift layer 24 is formed by implanting N-type impurities into the surface layer portion of the P ⁻ -type layer 21 by ion implantation after forming the gate electrode 29. Usually, after the gate electrode is formed, there is almost no heat treatment process because it affects the CMOS or the like constituting a driver or the like mixed with the high-side switching element and the low-side switching element. Therefore, the junction depth (N-type impurity diffusion depth) of drift layer 24 into P ⁻ -type layer 21 is shallow.

  Referring to FIG. 1 again, the drain terminals of the low-side switching elements (second switching element M2 and third switching element M3) are connected to an inductor L which is an external component for an IC formed as an integrated circuit. For external terminals. For this reason, the IC can be exposed to ESD (Electro Static Discharge), and it is not destroyed even if a surge (electrical stress such as instantaneously generated excessive voltage or current pulse) is applied to the external terminal. Desired.

  In the structure shown in FIG. 2, when an ESD surge is applied to the drain terminal, the electric field between the gate and the drain becomes strong, and a large avalanche current flows. As described above, since the junction depth of the drift layer 24 is shallow, there is a concern that current concentrates on the drift layer 24 and reliability is lowered.

Therefore, in the present embodiment, the third switching element M3 having a function as an ESD protection element is provided in parallel to the second switching element M2.
FIG. 3 is a schematic diagram showing a cross-sectional structure of a main part of the third switching element M3.

The third switching device M3 is also similar to the second switching element M2, P ^- the surface portion of the mold layer 21, ^{P +} -type contact layer 37, ^{N +} -type source layer 32, N-type drift layer 34, N ^{A +} -type drain layer 33 is formed, and an LDMOS structure is provided in which a first main electrode 28, a second main electrode 27, and a gate electrode 29 are provided on the surface thereof.

  The source layer 32 and the drain layer 33 are provided apart from each other, and a drift layer 34 is provided in contact with the drain layer 33 therebetween. The drift layer 34 has a lower impurity concentration than the source layer 32 and the drain layer 33.

A gate electrode 29 is provided on the surface of the P ⁻ -type layer 21 between the source layer 32 and the drift layer 34 via a gate insulating film 26. A P ⁺ -type contact layer 37 having an impurity concentration higher than that of the P ⁻ -type layer 21 is provided in contact with the source layer 32 at the end of the source layer 32 opposite to the gate electrode 29 side.

Further, in the third switching element M3, a P ⁺ -type anode layer 36 is provided in the drain layer 33, and an N-type layer 31 is provided below and in contact with the drain layer 33 and the anode layer 36. Yes.

A second main electrode 27 is provided on the surfaces of the source layer 32 and the contact layer 37. As a result, the source layer 32 is electrically connected to the second main electrode 27, and the P ⁻ -type layer 21 is set to the source potential via the contact layer 37. A first main electrode 28 is provided on the surfaces of the drain layer 33 and the anode layer 36, and the drain layer 33 and the anode layer 36 are electrically connected to the first main electrode 28.

In the third switching element M3, the anode layer 36, the N type layer 31, and the P ⁻ type layer 21 constitute a PNP type bipolar transistor, and the contact layer 37, the P ⁻ type layer 21 and the N type layer 31 are NPN type. A bipolar transistor is constituted, and a thyristor is constituted by these PNP type transistor and NPN type transistor. When the thyristor operation is performed, the first main electrode 28 functions as an anode electrode, and the second main electrode 27 functions as a cathode electrode.

  Therefore, the third switching element M3 has a configuration in which the MOS structure portion and the thyristor structure portion are connected in parallel between the first main electrode 28 and the second main electrode 27.

When the ESD surge does not jump into the drain terminal and the voltage applied between the first main electrode 28 and the second main electrode 27 is within the rated voltage, the thyristor does not operate and the gate voltage applied to the gate electrode 29 is reduced. In response, the MOS structure is turned on and off. That is, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 29, a channel is formed in the surface layer portion of the P ⁻ -type layer 21 below the gate electrode 29, and the drain layer 33, the drift layer 34, the channel and the source layer 32 are interposed. Thus, a current flows between the first main electrode 28 and the second main electrode 27 (this current path is referred to as a main current path). When the gate voltage is lower than the threshold voltage, no channel is formed under the gate electrode 29, the first main electrode 28 and the second main electrode 27 are not conducted, and the third switching element M3 is Turns off.

  In contrast to the main current path in the MOS structure, the thyristor functions as a surge current path through which a surge current flows when a surge is applied.

  The thyristor of the third switching element M3 is activated with avalanche breakdown as a trigger. Therefore, the third switching element M3 is configured so that the avalanche breakdown occurs in the third switching element M3 when a surge jumps into the external terminal (the drain terminal of the low-side switching element) described above. It is designed to have a breakdown voltage lower than M2. Specifically, the length L2 of the drift layer 34 in the third switching element M3 is shorter than the length L1 of the drift layer 24 in the second switching element M2 (L1> L2). Here, the length of the drift layer means the length in the direction connecting the gate and the drain.

  When a positive surge voltage (surge voltage at which the first main electrode 28 becomes higher than the second main electrode 27) is applied to the external terminal, the gate electrode 29 (via a pull-down resistor not shown) 2 and the first main electrode 28, and the drift layer is depleted. Here, since the breakdown voltage of the third switching element M3 is lower than that of the second switching element M2 (the length of the drift layer is short), the gate layer 29 side of the drain layer 33 of the third switching element M3 The electric field strength at the edge becomes higher, causing avalanche breakdown at that point.

Electrons and holes are generated by this avalanche breakdown, the holes flow through the P ⁻ type layer 21 and the contact layer 37 to the second main electrode 27, and the electrons are at the end of the drain layer 33 on the gate electrode 29 side. Then, it flows around the N-type layer 31 below the anode layer 36 and flows to the first main electrode 28.

  Here, when electrons move through the N-type layer 31, a voltage drop occurs due to parasitic resistance existing in the N-type layer 31. That is, the potential of the anode layer 36 that is in ohmic contact with the first main electrode 28 and the same potential as the first main electrode 28 is Vd, the resistance of the N-type layer 31 is R, and the current flowing through the N-type layer 31 is I. Then, the potential of the N-type layer 31 becomes lower than the potential Vd of the anode layer 36 (Vd−RI).

Therefore, a forward bias is applied to the PN junction between the anode layer 36 and the N-type layer 31, and holes are injected from the anode layer 36 into the P ⁻ -type layer 21. This is the base current of the NPN transistor, the collector current of the NPN transistor that flows in response to this becomes the base current of the PNP transistor, and the cycle in which the collector current of the PNP transistor corresponding to this base current becomes the base current of the NPN transistor is repeated. As a result, the thyristor is activated.

  When the thyristor is activated, the path between the first main electrode 28 and the second main electrode 27 through the thyristor becomes a low resistance state in which a large current can flow. Thereby, a surge current can be quickly discharged to the ground through a thyristor with a smaller element area. That is, when the surge voltage is applied, the third switching element M3 operates as a thyristor with high responsiveness and promptly draws the surge current and flows it to the ground, thereby preventing the second switching element M2 from being damaged by the surge. .

  Although it is conceivable that the third switching element M3 having an ESD protection function is not provided and the second switching element M2 itself has an element structure with excellent ESD tolerance, the first resistance is usually required to have the ESD tolerance. The distance between the main electrode and the second main electrode is increased, and the on-resistance when functioning as a switching element of the converter is increased.

  In the present embodiment, the third switching element M3 plays a function as an ESD protection element, and the second switching element M2 plays almost the role as a low-side switching element in the DC-DC converter. Can be designed with the highest priority on the characteristics required by the converter. That is, by forming the low-side switching element from the second switching element M2 and the third switching element M3 that share the respective roles, the original characteristics of the DC-DC converter are not impaired, and protection from ESD is also realized. it can.

  FIG. 4 is a characteristic diagram showing a relationship between the drain-source voltage (voltage between the first main electrode 28 and the second main electrode 27) Vds and the drain current Ids in the third switching element M3. Iesd on the vertical axis is the maximum current value of the ESD surge current. FIG. 4 shows the case where the gate voltage Vgs is zero volts (Vgs = 0) and the case where it is greater than zero volts (Vgs> 0).

  When the drain-source voltage Vds is within the rated voltage, the third switching element M3 does not operate as a thyristor, but operates when a high ESD voltage higher than the rated voltage is applied. That is, the third switching element M3 functions as a switching MOSFET within the rated voltage, and functions as an ESD protection element when ESD is applied.

  Next, FIG. 5 is a schematic cross-sectional view showing another specific example of the third switching element M3.

The third switching element M3 shown in FIG. 5 has the following structure. A high impurity concentration N ⁺ type buried layer 42 is provided on a P type substrate 41, and an N ⁻ type layer 43 and a P ⁻ type layer 44 are selectively provided on the N ⁺ type buried layer 42. Yes. A P-type base layer 47 is provided on the N ⁻ -type layer 43 adjacent to the P ⁻ -type layer 44.

An N ⁺ -type source layer 46 and a P ⁺ -type contact layer 45 are selectively provided on the surface layer portion of the P-type base layer 47. The source layer 46 and the contact layer 45 are adjacent to each other, and the second main electrode 27 is provided on the surface thereof. The source layer 46 and the contact layer 45 are electrically connected to the second main electrode 27, and the potential of the second main electrode 27 is applied to the P base layer 47 through the contact layer 45.

On the surface layer portion of the P ⁻ type layer 44, an N ⁺ type drain layer 49 and an N type drift layer 48 are selectively provided. The drift layer 48 is located between the source layer 46 and the drain layer 49 and is adjacent to the drain layer 49. The drift layer 48 has a lower impurity concentration than the drain layer 49. For example, the impurity concentration of the drift layer 48 is 2 × 10 ¹² to 4 × 10 ¹² / cm ² .

A gate electrode 29 is provided on the surface of the P-type base layer 47 and the P ⁻ -type layer 44 between the source layer 46 and the drift layer 48 with the gate insulating film 26 interposed therebetween.

On the N ⁺ type buried layer 42 on the drain layer 49 side, an N ⁺ type layer 51 is provided up to the element surface. The drain layer 49 and the N ⁺ type layer 51 are connected via a resistor, and the drain layer 49 and the N ⁺ type layer 51 are electrically connected to the first main electrode 28.

In the third switching element M3 shown in FIG. 5, the drain layer 49, the drift layer 48, the gate electrode 29, the P-type base layer 47, the channel formation region under the gate electrode 29 in the P ⁻ type layer 44, and the source layer 46 are An LDMOS is formed. The source layer 46, the P-type base layer 47, the N ⁻ -type layer 43, the N ⁺ -type buried layer 42, and the N ⁺ -type layer 51 constitute an NPN-type bipolar transistor Tr1. The LDMOS and the bipolar transistor Tr1 are connected in parallel between the first main electrode 28 and the second main electrode 27. The bipolar transistor Tr1 functions as a surge current path through which a surge current flows when a surge is applied.

  The bipolar transistor Tr1 is activated with avalanche breakdown as a trigger. Therefore, the third switching element M3 is configured so that the avalanche breakdown occurs in the third switching element M3 when a surge jumps into the external terminal (the drain terminal of the low-side switching element) described above. It is designed to have a breakdown voltage lower than M2. That is, also in the third switching element M3 shown in FIG. 5, the length L2 of the drift layer 48 is shorter than the length L1 of the drift layer 24 of the second switching element M2 shown in FIG. 2 (L1> L2 ).

  When a positive surge voltage is applied to the external terminal, between the first main electrode 28 and the gate electrode 29 having the same potential as the second main electrode 27 via a pull-down resistor (not shown). A high voltage is applied to the drift layer, and the drift layer is depleted. Here, since the breakdown voltage of the third switching element M3 is lower than that of the second switching element M2 (the length of the drift layer is short), the gate layer 29 side of the drain layer 49 of the third switching element M3 The electric field strength at the edge becomes higher, causing avalanche breakdown at that point.

Electrons and holes are generated by this avalanche breakdown, the electrons flow to the first main electrode 28, and the holes pass through the P ⁻ type layer 44, the P type base layer 47, and the contact layer 45 to form the second main electrode. 27 flows.

  Here, when holes move in the P-type base layer 47, a voltage drop is caused by the parasitic resistance existing in the P-type base layer 47. That is, the potential of the source layer 46 that is in ohmic contact with the second main electrode 27 and the same potential as the second main electrode 27 is Vs, the resistance of the P-type base layer 47 is R, and the current flowing through the P-type base layer 47 Assuming I, the potential under the source layer 46 in the P-type base layer 47 is lower than Vs (Vs−RI).

Therefore, a forward bias is applied to the PN junction between the source layer 46 and the P-type base layer 47, and electrons are injected from the source layer 46 into the N ⁻ -type layer 43 and the N ⁺ -type buried layer 42. As a result, the NPN bipolar transistor Tr is activated.

  When the bipolar transistor Tr1 is activated, the path between the first main electrode 28 and the second main electrode 27 through the bipolar transistor Tr1 becomes a low resistance state in which a large current can flow. As a result, the surge current can be quickly discharged to the ground through the bipolar transistor Tr1 with a smaller element area. That is, when the surge voltage is applied, the third switching element M3 operates as a thyristor with high responsiveness and promptly draws the surge current and flows it to the ground, thereby preventing the second switching element M2 from being damaged by the surge. .

When a negative surge voltage (surge voltage at which the first main electrode 28 has a lower potential than the second main electrode 27) is applied to the external terminal, the contact layer 45, the P-type base layer 47, P ⁻ A forward bias is applied to the PN diode composed of the mold layer 44, the N ⁺ -type buried layer 42, the N ⁺ -type layer 51, and the drain layer 49, and the surge current quickly flows to the ground through the diode.

  When the ESD surge does not jump in and the voltage applied between the first main electrode 28 and the second main electrode 27 is within the rated voltage, the bipolar transistor Tr1 does not operate and depends on the gate voltage applied to the gate electrode 29. LDMOS is turned on and off.

That is, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 29, a channel is formed in the surface layer portion of the P-type base layer 47 and the P ⁻ -type layer 44 below the gate electrode 29, and the drain layer 49, drift layer 48, channel A current flows between the first main electrode 28 and the second main electrode 27 through the source layer 46. When the gate voltage is lower than the threshold voltage, no channel is formed under the gate electrode 29, the first main electrode 28 and the second main electrode 27 are not conducted, and the third switching element M3 is Turns off.

  Next, FIG. 6 is a schematic cross-sectional view showing still another specific example of the third switching element M3.

The third switching element M3 shown in FIG. 6 has the following structure. A high impurity concentration N ⁺ type buried layer 42 is provided on the P type substrate 41, and a P type layer 52 and a P ⁻ type layer 57 are provided adjacent to each other on the N ⁺ type buried layer 42. Yes.

An N ⁺ -type source layer 54 is selectively provided on the surface layers of the P-type layer 52 and the P ⁻ -type layer 57. A P ⁺ -type contact layer 53 is provided adjacent to the source layer 54 on the surface layer portion of the P-type layer 52.

  A second main electrode 27 is provided on the surfaces of the source layer 54 and the contact layer 53, and the source layer 54 and the contact layer 53 are electrically connected to the second main electrode 27. Further, the potential of the second main electrode 27 is applied to the P-type layer 52 through the contact layer 53.

On the surface layer portion of the P ⁻ type layer 57, an N ⁺ type drain layer 56 and an N type drift layer 55 are selectively provided. The drift layer 55 is located between the source layer 54 and the drain layer 56 and is adjacent to the drain layer 56. The drift layer 55 has an impurity concentration lower than that of the drain layer 56. For example, the impurity concentration of the drift layer 55 is 2 × 10 ¹² to 4 × 10 ¹² / cm ² .

On the surface of the P ⁻ -type layer 57 between the source layer 54 and the drift layer 55, a gate electrode 29 is provided via the gate insulating film 26.

On the N ⁺ type buried layer 42 below the drain layer 56, an N ⁺ type layer 51 is provided in contact with the drain layer 56. The drain layer 56 and the N ⁺ type layer 51 are electrically connected to the first main electrode 28.

In the third switching element M3 shown in FIG. 6, the drain layer 56, the drift layer 55, the gate electrode 29, the channel forming region under the gate electrode 29 in the P ⁻ type layer 57, and the source layer 54 constitute an LDMOS. Further, the contact layer 53, the P-type layer 52, the N ⁺ -type buried layer 42, and the N ⁺ -type layer 51 constitute a PN diode D1. The LDMOS and the diode D1 are connected in parallel between the first main electrode 28 and the second main electrode 27. The diode D1 functions as a surge current path through which a surge current flows when a surge is applied.

  The third switching element M3 is connected to the second switching element so that the avalanche breakdown occurs in the diode D1 of the third switching element M3 when a surge enters the external terminal (the drain terminal of the low-side switching element). The breakdown voltage is designed to be lower than that of the element M2.

  In the third switching element M3, the breakdown voltage between the first main electrode 28 and the gate electrode 29 in the LDMOS is set larger than the breakdown voltage of the diode D1. Such a withstand voltage relationship can be controlled by increasing the length L2 of the drift layer 55, increasing the diffusion depth of the P-type layer 52, increasing the impurity concentration of the P-type layer 52, and the like.

When a positive surge voltage (reverse bias for the diode D1) is applied to the external terminal described above, the diode D1 avalanche breaks down. The avalanche breakdown location is the junction surface between the P-type layer 52 and the N ⁺ -type buried layer 42, and an electric field concentration location is formed over a relatively wide surface, so that current concentration hardly occurs, and the diode D 1 is resistant to breakdown. Has electrical characteristics. Due to the avalanche breakdown, the path between the first main electrode 28 and the second main electrode 27 through the diode D1 is in a low resistance state in which a large current can flow, and a surge current is quickly supplied to the ground. be able to.

  When a negative surge voltage is applied to the external terminal, since the diode D1 is forward biased, the surge current quickly flows to the ground through the diode D1.

  When the ESD surge does not jump in and the voltage applied between the first main electrode 28 and the second main electrode 27 is within the rated voltage, the diode D1 does not operate and depends on the gate voltage applied to the gate electrode 29. LDMOS is turned on and off.

That is, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 29, a channel is formed in the surface layer portion of the P ⁻ type layer 57 below the gate electrode 29, via the drain layer 56, the drift layer 55, the channel and source layer 54. Thus, a current flows between the first main electrode 28 and the second main electrode 27. When the gate voltage is lower than the threshold voltage, no channel is formed under the gate electrode 29, the first main electrode 28 and the second main electrode 27 are not conducted, and the third switching element M3 is Turns off.

  Next, the on / off timing of the second switching element M2 and the third switching element M3 will be described.

  During normal operation, as shown in FIG. 7A, the third switching element M3 is turned on at the same timing as the second switching element M2. When these low-side switching elements are on, the second switching element M2 and the third switching element M3 supply current to the load 10 via the inductor L. However, the third switching element M3 does not significantly affect the characteristics of the converter even if it is always off. As will be described later, since the current driving capability of the third switching element M3 is sufficiently smaller than that of the second switching element M2, the characteristics of the converter are almost determined by the electrical characteristics of the second switching element M2. Because it is.

  In a period in which the high-side switching element (first switching element M1) is on and the low-side switching elements (second switching element M2 and third switching element M3) are off (positive) Inductor current IL increases and energy is stored in inductor L.

  However, if the current value flowing through the inductor L is small when the current flowing through the load 10 is small, the energy stored in the inductor L is small when the high-side switching element (first switching element M1) is turned on. Therefore, during the period when the low-side switching element is on, the energy accumulated in the inductor L at a certain timing becomes zero. Thereafter, the current flowing through the inductor L flows from the load 10 to the ground via the low-side switching element. Since this current is not supplied to the load 10, it becomes a reactive current and greatly reduces the power conversion efficiency (output power / input power × 100%).

  In particular, battery-driven devices such as portable devices are required to have excellent conversion efficiency of the DC-DC converter even at light loads.

  Therefore, in the present embodiment, the second switching element M2 has a current driving capability necessary to obtain desired converter characteristics, while the third switching element M3 has the second switching element. The current driving capability is sufficiently lower than M2. Note that the current driving capability here is not the time of ESD surge application but the current driving capability when operating as a MOSFET within the rated voltage. The fact that the third switching element M3 has a lower current drive capability than the second switching element M2 means that the third switching element M3 has a higher on-resistance than the second switching element M2.

  For example, the cell area of the third switching element M3 is made smaller than the cell area of the second switching element M2, or the threshold voltage of the third switching element M3 is set higher than that of the second switching element M2. By doing so, the current driving capability of the third switching element M3 can be made lower than that of the second switching element M2.

  Further, as described above with reference to FIG. 1, the DC-DC converter of the present embodiment has a connection point between the low-side switching element (the second switching element M2 and the third switching element M3) and the inductor L. It has a detection circuit 8 for monitoring the potential. The detection circuit 8 detects the potential at the connection point and compares it with the reference potential Vref.

  During normal operation that is not under light load, when the high-side switching element is off and the low-side switching element is on, current flows from the ground to the connection point via the low-side switching element, so the potential at the connection point is a negative potential. Become.

  During a light load, the energy stored in the inductor becomes zero during the period when the high-side switching element is off and the low-side switching element is on, and current flows from the load 10 to the ground via the inductor L and the low-side switching element. Then, the potential at the connection point becomes a positive potential.

  Therefore, the sign of the inductor current IL can be determined from the comparison result between the potential at the connection point and the reference potential Vref. In the present embodiment, as shown in FIG. 7B showing a timing chart at light load, the second switching element M2 is off during the period in which the inductor current IL is negative, and the third switching element. A period during which M3 is on is provided.

  As described above, since the third switching element M3 has low current drive capability (high on-resistance), only the third switching element M3 is turned on when the inductor current IL is negative. The current flowing from the inductor L to the ground via the low-side switching element can be reduced. That is, the reactive current that flows to the ground without being supplied to the load 10 is reduced, and a reduction in efficiency can be suppressed.

  In the timing example shown in FIG. 7B, there is a period in which the second switching element M2 and the third switching element M3 are simultaneously turned on. However, as shown in FIG. 8, when the second switching element M2 is turned on. When the third switching element M3 is off, the second switching element M2 is off when the third switching element M3 is on, and so on. There may be no period during which the signals are simultaneously turned on. This is because the current driving capability of the third switching element M3 is sufficiently smaller than that of the second switching element M2, so that even if the second switching element M2 and the third switching element M3 are turned on at the same time, This is because the converter characteristics are determined by the electrical characteristics of the second switching element M2.

  In the example shown in FIGS. 7B and 8, the start timing of the period in which the second switching element M2 is off and the third switching element M3 is on is immediately before the inductor current IL changes from positive to zero. However, it may be the moment when it becomes zero or immediately after it becomes zero. Note that if the third switching element M3 is also turned on simultaneously with the first switching element M1, a through current flows from the input voltage line 11 to the ground. The switching element M1 needs to be turned off before the switching element M1 is turned on.

  Note that, when the load is further light, the efficiency can be improved by reducing the switching frequency of the high-side switching element and the low-side switching element.

Next, FIG. 9 is a schematic diagram showing a configuration example of a DC-DC converter using a semiconductor device according to another embodiment of the present invention.
FIG. 10 shows the operation timing of the switching elements M1, M2, and M4 and the waveform of the inductor current IL in the DC-DC converter shown in FIG.

  The first switching element M1, the second switching element M2, and the third switching element M4 are MOSFETs. As in the embodiment described above with reference to FIG. 1, the first switching element M1 and the second switching element M2 are driven by gate drive signals g1 and g2 supplied from the control circuit 9 via drivers 5 and 6, respectively. On / off. However, this embodiment is different from the embodiment shown in FIG. 1 in that the gate of the third switching element M4 is always connected to the ground. Therefore, the gate electrode and the source electrode of the third switching element M4 are electrically short-circuited.

  The third switching element M4 functions as a low-side switching element in the DC-DC converter together with the second switching element M2. However, unlike the third switching element M3 in the above-described embodiment, the third switching element M4 does not necessarily have an ESD protection function. May be.

  FIG. 9 shows the internal diodes (parasitic diodes) d1 and d2 in the second switching element M2 and the third switching element M4. The built-in diodes d1 and d2 exist in parallel to the main current path between the drains and the sources of the second switching element M2 and the third switching element M4, and the direction from the source to the drain is the forward direction. .

The size of the second switching element M2 is larger than the size of the third switching element M4.
The threshold voltage of the third switching element M4 is set as follows.
0 <(threshold voltage of the third switching element M4) <(ON voltage of the built-in diode d1 of the second switching element M2) (1).

  As a result, when the potential at the connection point between the first switching element M1 and the second switching element M2 becomes higher than − (threshold voltage of the third switching element M4), the third switching element M4 is turned off. When the potential at the connection point becomes smaller than − (threshold voltage of the third switching element M4), the third switching element M3 is turned on.

  In the normal operation shown in FIG. 10A, the potential at the connection point between the first switching element M1 and the second switching element M2 is negative during the period in which the first switching element M1 is off. During the period when both the first switching element M1 and the second switching element M2 are off, if there is no third switching element M4, the connection between the first switching element M1 and the second switching element M2 The potential at the point becomes − (on voltage of the built-in diode d1 of the second switching element M2). However, due to the presence of the third switching element M4, the gate-source voltage of the third switching element M4 becomes equal to or higher than the threshold voltage according to the relationship of the above expression (1), and the third switching element M4 is in the on state. Become.

  When the second switching element M2 is turned on, the size of the second switching element M2 is larger than the size of the third switching element M4, and the applied gate-source voltage is higher than that of the second switching element M2. Since this is larger than the third switching element M4, the on-resistance is lower in the third switching element M4. Accordingly, the potential at the connection point between the first switching element M1 and the second switching element M2 approaches the ground potential, and the third switching element M4 is turned off.

In the case of the light load 1 shown in FIG. 10B, the inductor current IL flows to the load 10 when the second switching element M2 is turned on for a certain period during the return and then the second switching element M2 is turned off. The potential at the connection point between the first switching element M1 and the second switching element M2 becomes negative, and the third switching element M4 is turned on.
Thereafter, when the inductor current IL tries to flow from the load 10 to the ground, the potential at the connection point between the first switching element M1 and the second switching element M2 becomes positive, and the third switching element M4 is in the OFF state. It becomes. Therefore, the reactive current flowing from the load 10 to the ground can be eliminated. Further, since a control circuit for turning on and off the third switching element M4 is not necessary, the circuit configuration can be simplified.

  In the light load 2 shown in FIG. 10C in which the load is further lighter than that at the light load 1, the second switching element M2 is not turned on for a certain period during the return time. By doing so, the potential at the connection point between the first switching element M1 and the second switching element M2 becomes negative, and the third switching element M4 is turned on. Thereafter, when the inductor current IL tries to flow from the load 10 to the ground, the potential at the connection point between the first switching element M1 and the second switching element M2 becomes positive, and the third switching element M4 is in the OFF state. It becomes. Therefore, the reactive current that tends to flow from the load 10 toward the ground can be eliminated.

  At light load 1 where the current is relatively large even at light load, the conduction loss of the third switching element M4 is large. Therefore, the second switching element M2 is turned on in a region where the load current is large, and the load current is further increased. At the time of small light load 2, since the loss for driving the second switching element M2 is larger than the conduction loss of the third switching element M4, the second switching element M2 is operated without being turned on. By doing so, the conversion efficiency in the low current region can be improved.

Next, FIG. 11 is a schematic diagram showing a configuration example of a DC-DC converter using a semiconductor device according to still another embodiment of the present invention.
12 shows the operation timing of the switching elements M1 and M2, the gate voltage g2 of the switching element M2, the high-side switching element (first switching element M1) and the low-side switching element (the second switching element) in the DC-DC converter shown in FIG. The waveforms of the potential Vx at the connection point with the switching element M2) and the inductor current IL are shown.

  The first switching element M1 and the second switching element M2 are MOSFETs. Similar to the above-described embodiment, the first switching element M1 and the second switching element M2 are turned on and off by a gate drive signal supplied from the control circuit 9 via the drivers 5 and 6, respectively. However, this embodiment is different from the embodiment shown in FIG. 9 in that the third switching element does not exist.

In the present embodiment, the threshold voltage of the second switching element M2 is set as follows.
0 <(threshold voltage of the second switching element M2) <(ON voltage of the built-in diode d1 of the second switching element M2) (2).

  Thus, when the gate voltage of the second switching element M2 is the reference potential (low level “L”), the potential Vx of the connection point between the first switching element M1 and the second switching element M2 is The second switching element M2 is turned off when it exceeds-(threshold voltage of the second switching element M2), and the second voltage when the potential Vx at the connection point becomes lower than-(threshold voltage of the second switching element M2). The switching element M2 is turned on.

  In the normal operation shown in FIG. 12A, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 is negative during the period in which the first switching element M1 is off. During the period in which the first switching element M1 is off and the gate voltage g2 of the second switching element M2 is at the low level “L”, the second switching element M2 is in the on state, as in FIG. However, since the gate bias is shallow at this time, the on-resistance is high, and the on-resistance can be lowered by setting the gate voltage g2 of the second switching element M2 to the high level “H”. By doing so, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 becomes the reference potential because the gate voltage g2 of the second switching element M2 becomes the high level “H”. Approaches (0 volts).

  The second switching element M2 in the present embodiment also serves as the third switching element M4 in the embodiment shown in FIG. The second switching element M2 of the present embodiment has a larger element size than the third switching element M4.

  Therefore, in this embodiment, by setting the second switching element M2 as in the above formula (2), the loss during the period in which both the high-side switching element and the low-side switching element are turned off is shown in FIG. It can reduce compared with a form.

  In the light load 1 shown in FIG. 12B, the second switching element M2 is turned on for a certain period at the time of recirculation, and then the gate voltage g2 of the second switching element M2 is set to the reference potential (low level “L”). Then, when the inductor current IL flows to the load 10, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 becomes negative, and the second switching element M2 has the gate voltage g2 Regardless of being at the low level “L”, it is turned on.

  Thereafter, when the inductor current IL tries to flow from the load 10 to the ground, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 becomes positive, and the second switching element M2 Since the voltage g2 is at a low level, it is turned off. Therefore, the reactive current flowing from the load 10 to the ground can be eliminated.

  In the light load 2 shown in FIG. 12C, which is lighter than the light load 1, the gate voltage g2 of the second switching element M2 is set to the low level “L” for a certain period during the return. By doing so, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 becomes negative, and the second switching element M2 is turned on.

  Thereafter, when the inductor current IL tries to flow from the load 10 to the ground, the potential Vx at the connection point between the first switching element M1 and the second switching element M2 becomes positive, and the second switching element M2 is turned off. It becomes a state. Therefore, the reactive current that tends to flow from the load 10 toward the ground can be eliminated.

  At light load 1 where the current is relatively large even at light load, the conduction loss of the second switching element M2 is large, so the second switching element M2 is turned on in a region where the load current is large, and the load current is further increased. At a small light load 2, since the loss for driving the second switching element M2 is larger than the conduction loss of the second switching element M2, the second switching element M2 is not turned on (the gate voltage g2 is set to the threshold voltage). Do not do this). By doing so, the conversion efficiency in the low current region can be improved. As described above, according to the present embodiment, it is possible to avoid the loss during the period in which the third switching element M4 in the embodiment shown in FIG. 9 is turned on, and the third switching element M4 is not prepared. The chip occupation area can be reduced.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to them, and various modifications can be made based on the technical idea of the present invention.

  The present invention includes the following aspects.

(Appendix 1)
A high-side switching element having a first switching element connected between the input voltage line and the inductive load;
A low-side switching element having a second switching element and a third switching element connected in parallel between the inductive load and a reference voltage line;
With
When a surge is applied to a terminal connected to the inductive load in the low-side switching element, a surge current is discharged to the reference voltage line through the third switching element. .
(Appendix 2)
The low-side switching element includes a first conductivity type semiconductor layer, a second conductivity type source layer provided in a surface layer portion of the semiconductor layer, and a surface layer portion of the semiconductor layer spaced from the source layer. A drain layer of a second conductivity type provided; a drift layer of a second conductivity type provided in contact with the drain layer between the source layer and the drain layer and having a lower impurity concentration than the drain layer; and the drain A first main electrode connected to the layer; a second main electrode connected to the source layer; and an insulating film provided on the surface of the semiconductor layer between the source layer and the drift layer A gate electrode, and
2. The semiconductor device according to claim 1, wherein L1> L2, where L1 is a length of the drift layer in the second switching element and L2 is a length of the drift layer in the third switching element. .
(Appendix 3)
The third switching element is
A main current path connecting the first main electrode and the second main electrode via the drain layer, the drift layer, a channel formed under the gate electrode, and the source layer;
A surge current path provided between the first main electrode and the second main electrode in parallel with the main current path, and activated by the surge and through which a surge current flows;
The semiconductor device according to appendix 2, characterized by comprising:
(Appendix 4)
A high-side switching element having a first switching element connected between the input voltage line and the inductive load;
A low-side switching element having a second switching element and a third switching element connected in parallel between the inductive load and a reference voltage line;
With
The size of the second switching element is larger than the size of the third switching element,
0 <(threshold voltage of the third switching element) <(on-voltage of the built-in diode of the second switching element),
When the potential at the connection point between the first switching element and the second switching element becomes higher than − (threshold voltage of the third switching element), the third switching element is turned off, and the connection point The semiconductor device, wherein the third switching element is turned on when a potential becomes smaller than − (threshold voltage of the third switching element).
(Appendix 5)
The semiconductor device according to appendix 4, wherein the gate electrode and the source electrode of the third switching element are electrically short-circuited.
(Appendix 6)
Supplementary note 4 wherein when a surge is applied to a terminal connected to the inductive load in the low-side switching element, the surge current is discharged to the reference voltage line through the third switching element. Or the semiconductor device according to 5;
(Appendix 7)
A first switching element connected between the input voltage line and the inductive load;
A second switching element connected in parallel between the inductive load and a reference voltage line;
With
0 <(threshold voltage of the second switching element) <(ON voltage of the built-in diode of the second switching element),
When the gate voltage of the second switching element is a reference potential, the potential at the connection point between the first switching element and the second switching element is − (threshold voltage of the second switching element). The second switching element is turned off when it becomes larger, and the second switching element is turned on when the potential at the connection point becomes smaller than − (threshold voltage of the second switching element). .

  8: detection circuit, 11: input voltage line, 22, 32, 46, 54 ... source layer, 23, 33, 49, 56 ... drain layer, 24, 34, 48, 55 ... drift layer, 27 ... second main Electrode 28 ... first main electrode 29 ... gate electrode M1 ... first switching element M2 ... second switching element M3, M4 ... third switching element

Claims (2)

A first switching element connected between the input voltage line and the inductive load;
A second switching element connected in parallel between the inductive load and a reference voltage line;
With
0 <(threshold voltage of the second switching element) <(ON voltage of the built-in diode of the second switching element),
When the gate voltage of the second switching element is a reference potential, the potential at the connection point between the first switching element and the second switching element is − (threshold voltage of the second switching element). When the voltage becomes larger, the second switching element is turned off, and when the potential at the connection point becomes smaller than − (threshold voltage of the second switching element), the second switching element becomes the gate of the second switching element. A semiconductor device which is turned on regardless of a voltage level . The second switching element is
A first conductivity type semiconductor layer;
A source layer of a second conductivity type provided in a surface layer portion of the semiconductor layer;
A drain layer of a second conductivity type provided in a surface layer portion of the semiconductor layer so as to be separated from the source layer;
A drift layer of a second conductivity type provided in contact with the drain layer between the source layer and the drain layer and having a lower impurity concentration than the drain layer;
A first main electrode connected to the drain layer;
A second main electrode connected to the source layer;
A gate electrode provided on the surface of the semiconductor layer between the source layer and the drift layer via an insulating film;
The semiconductor device according to claim 1, comprising:

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