JPH08288811A - Push-pull drive circuit - Google Patents

Abstract

PURPOSE: To provide a push-pull drive circuit where a proper delay time is set even for both transistors which have fast and slow operations respectively. CONSTITUTION: When the control signal sent from an input terminal 11 is changed to 'H' from 'L', the output G1 of an OR circuit 12 rises. Then a p-MOS 14 is turned off and at the same time the output of a comparator 16 is changed to 'H' from 'L' when the control signal exceeds the threshold voltage Vr1. Both 'H' of the output of the comparator 16 and the control signal are inputted to an AND circuit 13, and the output G2 of the cicuit 13 rises and exceeds the threshold voltage Vr2. Thus n-MOS 15 is turned on. The output of a comparator 17 is changed to 'H' from 'L' and inputted to the circuit 12. The p-MOS 14 is kept in an OFF state by the output of the circuit 12 right after the control signal is changed to 'L'. On the other hand, an n-MOS 15 is turned off and at the same time the output of the comparator 17 is changed to 'L' when the output G2 of the circuit 13 falls lower than the voltage Vr2. Both 'L' of the output of the comparator 17 and the control signal are inputted to the circuit 12. Thus the output of the circuit 12 is changed to 'L' and the p-MOS 14 is turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DC-DC for electronic equipment.
The present invention relates to a push-pull drive circuit used for a converter or the like.

[0002]

2. Description of the Related Art Conventionally, there is a push-pull drive circuit as shown in FIG. The push-pull drive circuit 1 shown in FIG. 9A operates as shown in the timing chart of FIG. To briefly explain this, first, FIG.
In the push-pull drive circuit 1 of FIG. 1, the pulse waveform signal 1a-1 input from the control circuit (not shown) to the input terminal 1a (see “input” in FIG. 2B) is
Output to the gate of the n-MOS transistor 3a via the other side, and on the other hand, via the inverter 2b to another n-MOS transistor 3a.
It is output to the gate of the transistor 3b.

The rising output corresponding to the falling of the input signal at the drain of the n-MOS transistor 3a is passed through the delay circuit including the resistor 4a and the capacitor 5a to the inverter 6a as the signal a-1 having the delay time t1. Is output. Therefore, the inverted signal G1 (driving signal of the p-MOS transistor M1) from the inverter 6a falls after a delay of time t1 from the fall of the input signal (see G1 in the same figure (b)). This drive signal (gate applied voltage) G1 cuts off the p-MOS transistor M1 at "H" and makes it conductive at "L". That is, the falling delay time t1 of the drive signal G1 is p-MO.
It is set to delay the conduction of the S transistor M1.

On the other hand, the rising output corresponding to the rising of the input signal at the drain of the other n-MOS transistor 3b also has a signal b- having a delay time t2 through the delay circuit composed of the resistor 4b and the capacitor 5b as described above.
1 is output to the buffer 6b. Therefore, the output signal G2 from the buffer 6b (n-MOS transistor M
Drive signal 2) is at time t after the rising edge of the input signal.
Start up with a delay of 2 (see G2 in Fig. 2 (b)). When the drive signal G2 is "H", the n-MOS transistor is made conductive, and when it is "L", it is cut off. That is, this drive signal G
The rising delay time t2 of 2 is set to delay the conduction of the n-MOS transistor M2.

Since the MOS transistor is driven by charging or discharging the gate, the conducting and blocking operations are generally slightly delayed with respect to changes in the voltage applied to the gate during the charging or discharging time. Therefore, if both transistors are driven in synchronism with the rising and falling edges of the input signal 1a-1, the other transistor is turned on while one transistor is still not cut off, and the power source Vcc is shifted to the ground side. Through current flows, a correct output cannot be taken out from the drain connection of the push-pull circuit, and useless power loss occurs. The delay time as described above is set in order to take out a correct output from the push-pull circuit in accordance with the drive characteristics of the MOS transistor.

[0006]

The delay time (t1 or t2) is set to a fixed time fixed by the resistor (4a or 4b) and the capacitor (5a or 5b). The drive characteristic of the MOS transistor has a slow operation speed. The delay time is set to be a little longer in order to cope with the difference in the characteristics. The time t1 included in each of the delay times t1 and t2 shown in FIG.
-1 and t2-1 are delay times which are originally useless for the MOS transistor having the drive characteristic shown in the timing chart of the figure.

As described above, since the delay time is set to be slightly longer and the set delay time is a fixed time, a fast operating MOS transistor is used and a high driving frequency is used. When I try to design
That is, if the cycle T shown in FIG. 6 (b) is shortened, the cycle (time)
The ratio of the delay times t1 and t2 to T increases, and the duty width of the drive signal is limited accordingly, so that the transistors used are limited. Therefore, there is a problem that the degree of freedom in design is greatly restricted.

On the other hand, when a slow-moving MOS transistor is used, if the rising and falling edges of the MOS transistor seem to be even later than the delay time set to the constant value, a break time is set. However, since the through current flows through the MOS transistor, the MOS transistor to be used is limited and the degree of freedom in design is limited.

The object of the present invention is to solve the above-mentioned conventional problems.
It is an object of the present invention to provide a push-pull drive circuit in which an appropriate delay time is set regardless of whether the transistor has a fast operation or the transistor has a slow operation.

[0010]

According to the push-pull driving circuit of the invention described in claim 1, after confirming that one of the push-side transistor and the pull-side transistor is off, the other transistor is turned on. It is configured to drive and control the push-pull circuit.

According to another aspect of the push-pull drive circuit of the present invention, there is provided a first monitoring means for monitoring the gate voltage of the push-side transistor based on the input signal, and a pull side based on the monitoring result of the first monitoring means. A first switching means for outputting a drive signal based on the input signal to the gate of the transistor; a second monitoring means for monitoring the gate voltage of the pull-side transistor; and a monitoring result of the second monitoring means. The gate of the push-side transistor includes a second switching unit that outputs a drive signal based on the input signal. And, for example, claim 3
As described above, the first monitoring means outputs a monitoring result signal when the gate voltage of the push-side transistor becomes equal to or higher than a predetermined voltage, and the first switching means outputs the monitoring result signal and the input signal. A logical product with a signal is output to the gate of the pull-side transistor, and the second monitoring means outputs a monitoring result signal when the gate voltage of the pull-side transistor becomes equal to or lower than a predetermined voltage, and the second monitoring means outputs the result. The switching means outputs a logical sum of the monitoring result signal and the input signal to the gate of the push-side transistor.

Further, for example, as described in claim 4, the first monitoring means outputs a monitoring result signal when the gate voltage of the push-side transistor becomes equal to or lower than a predetermined voltage, and the first switching means. Outputs a logical product of the monitoring result signal and the input signal to the gate of the pull-side transistor, and the second monitoring means outputs the monitoring result signal when the gate voltage of the pull-side transistor becomes equal to or lower than a predetermined voltage. And the second switching means outputs the logical sum of the monitoring result signal and the input signal to the gate of the push-side transistor.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a diagram showing a configuration of a push-pull drive circuit according to an embodiment, and FIG. 1B is an operation state diagram for explaining the operation of the push-pull drive circuit having the above configuration.

First, the structure will be described. As shown in FIG. 3A, in the push-pull drive circuit 10, the control signal input from the control circuit (not shown) via the input terminal 11 is one input side of the OR circuit 12 which is the second switching means. And one input side of the AND circuit 13 which is the first switching means. The output of the OR circuit 12 is
As the drive signal G1, the p-MOS transistor M1 (14) which is the push-side transistor of the push-pull circuit.
The output of the AND circuit 13 is given to the gate of the n-MOS transistor M2 (15), which is the pull-side transistor of the push-pull circuit, as the drive signal G2. As a result, the connection point D between the drain of the p-MOS transistor M1 (14) and the drain of the n-MOS transistor M2 (15) is smoothed to the predetermined voltage through the smoothing circuit including the coil L and the capacitor C. Is output to an external circuit (not shown).

The drive signal G1 output from the OR circuit 12 is branched and input to the non-inverting input side of the comparator Cmp1 (16) which is the first monitoring means. On the inverting input side of the comparator Cmp1 (16), p-M
The driving threshold voltage Vr1 of the OS transistor M1 (14) is input. The output of the comparator Cmp1 (16) is input to the other input side of the AND circuit 13.

The drive signal G2 output from the AND circuit 13 is also branched and input to the non-inverting input side of the comparator Cmp2 (17) which is the second monitoring means. On the inverting input side of the comparator Cmp2 (17), n−
Drive threshold voltage Vr2 of MOS transistor M2 (15)
Has been entered. This comparator Cmp2 (17)
The output of is input to the other input side of the OR circuit 12.

Next, FIGS. 2 (a) to 2 (f) are timing charts showing the operation of the push-pull drive circuit 10 having the above construction. The push-pull drive circuit 1 is described with reference to the timing chart of FIG. 2 and the operation state diagram shown in FIG.
The operation of 0 will be described.

First, when the input signal of the input terminal 11 is time t
From the state of "L" indicated by 0 to "H" indicated by time t3
When standing up to (“1”) (see FIGS. 2 (f) and (a)),
The output of the OR circuit 12 becomes "H"("1"), and p-M
The gate application voltage G1 of the OS transistor M1 (14) starts to rise and exceeds the cut-off threshold voltage Vr1 of the p-MOS transistor M1 (14) at time t4 (FIG. 2).
(f) and (d), and G1 in FIG. 1 (b)). As a result, the p-MOS transistor M1 (14) is completely turned off. The period from time t3 to time t4 is p-
This is a delay time until completion of rising based on the charge / discharge characteristics of the gate of the MOS transistor M1 (14).

At time t4, the applied voltage G1 exceeds the cut-off threshold voltage Vr1 of the p-MOS transistor M1 (14) input to the comparator Cmp1 (16), so that the output of the comparator Cmp1 (16). Becomes "H"("1") (see Cmp1 in FIGS. 1 (a) and 1 (b)), which causes the output of the AND circuit 13 to be "H".
("1"). The output of this AND circuit 13 is "H"
When it becomes (“1”), the gate applied voltage G2 of the n-MOS transistor M2 (15) starts to rise. The conduction threshold voltage Vr2 of the n-MOS transistor M2 (15) is near "L"("0") of the applied voltage G2 (see FIG. 2 (c)), and almost immediately when the applied voltage G2 rises. The power is turned on (turned on) at time t5. The applied voltage G2 is the n-MOS transistor M2 (15).
Since the current-carrying threshold voltage Vr2 is exceeded, the output of the comparator Cmp2 (17) input to the inverting input terminal of the current-carrying threshold voltage Vr2 becomes “H” (“1”), which results in OR. "H"("1") from circuit 12
Level output continues. That is, the applied voltage G1 is "H"("1"), and the p-MOS transistor M1 is
(14) off, n-MOS transistor M by this
2 (15) is on continuously. After this, the above-mentioned p-MO
The shut-off (OFF) completion state of the S transistor M1 (14) and the energization (ON) completion state of the n-MOS transistor M2 (15) are maintained while the input signal is "H"("1").
That is, it continues until time t6 (see FIGS. 2 (a), 2 (d) and 2 (e)).

Next, when the input signal falls at time t6 (see the state B in which the input in FIG. 1B is "L"("0")), the output of the AND circuit 13 is "L"(" 0 "). As a result, the n-MOS transistor M2 (15)
Discharge of the gate of the n-MOS transistor M2 (15) is started and the applied voltage G2 falls below the energization threshold voltage Vr2 at time t7, whereby the n-MOS transistor M2 (15) is completely turned off (FIG. 1 (b)).
State B of FIG. 2 (c), (e), (f)). As described above, since the applied voltage G2 is lower than the conduction threshold voltage Vr2 of the n-MOS transistor M2 (15), the comparator C
The output of mp2 (17) becomes "L"("0"). Thus, at time t7, both the input from the input terminal 11 to the OR circuit 12 and the input from the comparator Cmp2 (17) become “L” (“0”), and thus the OR circuit 1
The output of 2 changes from "H"("1") to "L"("0"). As a result, the p-MOS transistor M1 (1
The voltage G1 applied to 4) falls. The above-mentioned p-MO
The cut-off threshold voltage Vr1 of the S transistor M1 (14) is
The applied voltage G1 is near the “H” (“1”) level (see FIG. 2 (b)).
When it changes from (“1”) to “L” (“0”), it almost immediately falls below the cut-off threshold voltage Vr1 of the p-MOS transistor M1 (14) and the p-MOS transistor M1 (1)
4) starts energization rising. Since the applied voltage G1 is lower than the threshold voltage of the p-MOS transistor M1 (14), the comparator Cmp1
The output of (16) is "L"("0"), and therefore the output of the AND circuit 13 is also "L"("0"). This p-MOS transistor M1 (14) is on, and n-MO
The state in which the S transistor M2 (15) is off is the same as the state at the time t0 described above, and thereafter continues until the input signal rises.

As described above, the p-MOS transistor M1
(14) and the n-MOS transistor M2 (15) are alternately turned on / off repeatedly. Then, when one transistor is turned off, the other transistor immediately starts an on operation, so that the times t1-1 and t2 shown in FIG.
An unnecessary delay such as -1 is eliminated, and the duty width of the control signal can be effectively used.

Even when the operation of the transistor is slow, the applied voltages G1 and G2 are monitored by the comparator Cmp1 (16) and the comparator Cmp2 (17) as described above, and the OR circuit 12 and the OR circuit 12 and Due to the switching of the input signal by the AND circuit 13, the ON operation of one transistor does not overlap with the ON operation of the other transistor.

FIGS. 3A and 3C are timing charts when such a slow-moving transistor is used.
For comparison, FIG. 2B shows the timing charts of the applied voltages G1 and G2 shown in FIGS. 2B and 2C again.
In contrast to the slightly steep rises and falls of the applied voltages G1 and G2, the gentle slope of the rises and falls of the applied voltages G1 ′ and G2 ′ shown in FIG. 3 (c) is the timing chart of FIG. 2 described above. This is a slightly exaggerated illustration of the case of the slow-moving MOS transistor, as compared with the case of the fast-moving MOS transistor shown in FIG. 3 (that is, the reprinted diagram shown in FIG. 3B). Further, times (periods) T2 and T1 shown in FIG. 2B respectively indicate a period from time t3 to time t4 and a period from time t6 to time t7 shown in FIG. 2F.

In the push-pull drive circuit of the embodiment shown in FIG. 1A, the applied voltage G1 corresponding to the p-MOS transistor is used even when the slow-moving transistor shown in the flow chart of FIG. 3C is used. As shown in FIG. 3 (c), the period T2 ′ from the start of rising of ′ until the applied voltage G1 ′ exceeds the cut-off threshold voltage Vr1 for turning off the p-MOS transistor is long as shown in FIG. 3 (c). Even then, the applied voltage G2 'corresponding to the n-MOS transistor does not start rising until the p-MOS transistor is completely cut off after the period T2' has elapsed. That is, the n-MOS transistor does not start energizing. Therefore, no through current flows from the power supply side to the ground side.

In this way, after the n-MOS transistor is turned on in response to the appropriate rise of the applied voltage G2 ', the applied signal G2' starts to fall due to the next fall of the input signal. The energizing threshold voltage V
By falling below r2, the n-MOS transistor is completely cut off. Also in this case, the other applied voltage G1 'does not fall until the period T1' from the start of the fall of the applied voltage G2 'to the fall of the energization threshold voltage Vr2 has elapsed. One n-MO
Until the S-transistor shuts off completely, the other p-MO
The S transistor does not start energizing.

As described above, according to the embodiment shown in FIG. 1 (a), in the transistor in which the p-MOS transistor and the n-MOS transistor forming the push-pull circuit operate at high speed, unnecessary delay time is required. The transistor can be turned on / off at high speed without intervening, and even a transistor operating at low speed can be turned on / off with a delay according to the driving characteristics of the transistor so that a through current does not flow.

In the above embodiment, a p-MOS transistor is used on the push side of the push-pull circuit,
Although the case where the n-MOS transistor is used on the pull side has been described, the present invention is not limited to this, and a push-pull circuit using an n-MOS transistor can be driven on both the push side and the pull side.

FIG. 4 (a) shows another embodiment for driving a push-pull circuit composed of two n-MOS transistors, and FIG. 4 (b) shows a timing chart of its operation. In the configuration shown in FIG. 4 (a), the same components as in the configuration shown in FIG. 1 (a) are designated by the same reference numerals as in FIG. 1 (a). In FIG. 4A, first, the push-pull circuit is provided on the push side as well as the n-MOS transistor M2 (15) on the pull side.
1-2 (18) is used. The push-pull drive circuit 20 shown in FIG.
Circuit 12 and push-side n-MOS transistor M1-
An inverter 19 is arranged between the two (18). As a result, the output of the OR circuit 12 is inverted and the gate applied voltage G1 is applied to the gate of the n-MOS transistor M1-2 (18).
Enter as -2. In addition, the comparator Cmp1 (1
The gate applied voltage G1-2 is applied to the non-inverting input terminal of 6).
Is input, and the driving threshold voltage Vr1-2 of the n-MOS transistor M1-2 (18) is input to the inverting input terminal of the comparator Cmp1 (16).

This push-pull drive circuit 20 is shown in FIG.
As shown in the timing chart of (b), when the input signal rises from “L” to “H”, the n-MOS transistor M1− passes through the OR circuit 12 and the inverter 19.
The gate voltage G1-2 of 2 (18) starts to fall (see time t11 in FIG. 4B). When the gate voltage G1-2 falls below the drive threshold voltage Vr1-2 of the n-MOS transistor M1-2, the n-MOS transistor M1-2 (18) turns off and the comparator Cm.
The output of p1 (16) becomes "H".

Since the output of the comparator Cmp1 (16) and the input signal are "H", the output of the AND circuit 13, that is, the gate applied voltage G2 of the pull-side n-MOS transistor M2 (15) rises. (See time t12 in FIG. 7B), and when the gate applied voltage G2 exceeds the driving threshold voltage Vr2 of the n-MOS transistor M2 (15), the n-MOS transistor M2 (15) becomes conductive. .

Then, when the input signal falls, as shown in FIG.
As in the case of (a), the output of the AND circuit 13 changes from "H" to "L", and the pull-side n-MOS transistor M
The gate applied voltage G2 of 2 (15) starts to fall (see time t13 in the same figure (b)).
When 2 falls below the drive threshold voltage Vr2 of the n-MOS transistor M2 (15) (see time t14 in FIG. 7B), the output of the comparator Cmp2 (17) becomes "L". Since the output of the comparator Cmp2 (17) becomes "L" and the input signal is "L", the output of the OR circuit 12 is "L" and the inverter 1
The output of 9 is "H". That is, the gate voltage G1-2
Starts rising.

Thus, this push-pull drive circuit 2
Also in the case of 0, the conduction of the other n-MOS transistor of the push-pull circuit is not executed until the interruption of one of the two n-MOS transistors is completed. Therefore, in this case as well, there is no possibility that a through current flows even in a slow-moving transistor. Further, when the cutoff of one transistor is completed, the gate drive voltage of the other transistor immediately starts to rise, so even if a design using a fast-moving transistor is performed, that is, even if the frequency of the input control signal is increased, Since there is no unnecessary delay time, the duty of the applied voltage is improved.

FIG. 5 is an overall configuration diagram of a DC / DC converter in which the push-pull drive circuit described above is incorporated and used. In the figure, an oscillating circuit 21 is a circuit for outputting a triangular wave signal. Output. A reference voltage is supplied to the + input side (inverting input side) of the comparator 22 via a preamplifier (error amplifier) 27. This reference voltage is a voltage obtained by dividing the output voltage Vout of the DC-DC converter by the resistors R1 and R2, and is a voltage that changes according to the output of the DC-DC converter. Therefore, the oscillator 22
By comparing the triangular wave signal output from the reference voltage with the reference voltage, a signal having a pulse width according to the output change of the DC-DC converter is output to the control logic circuit 23.

The control logic circuit 23 includes a comparator 2
In addition to the pulse signal output by V.sub.2, Vfb, which is a feedback signal of the output voltage Vout, and the coil current value detected by the current detection circuit 24 are received, and the p-MOS transistor 28 and the n-MOS transistor 29 are operated in accordance with those signals. Outputs a signal for controlling.

The drive circuit 25 is the push-pull drive circuit 10 described above, and as described above, the control logic circuit 2 is used.
The p-MOS transistor 28 and the n-MOS transistor 29 are driven so as to be alternately turned on / off based on the control signal input from the circuit 3.

According to the present invention, the two drive signals output at this time drive the respective MOS transistors by the delay time control circuit provided in the drive circuit 25 so that the two MOS transistors are not simultaneously turned on. The delay is given according to the characteristics. The drive signals (gate voltages) VP and VN of the MOS transistors shown in the figure are the gate applied voltages G1 and G2 or G1 ′ and G2 ′ in the above-described embodiments, respectively.
Is. Of course, as shown in FIG. 4 (a), p-M of FIG.
The OS transistor 28 can be replaced with an n-MOS transistor.

P-M of the DC-DC converter shown in FIG.
OS transistor 28 and n-MOS transistor 2
9 is driven by the drive signal, and a coil current is generated according to its on / off state. This coil current has a ramp waveform, the ripple is suppressed by the capacitor C, and the stable voltage is output from the output terminal 12.

[0038]

As described above, according to the present invention,
Since the drive delay of the MOS transistor can be performed according to the drive characteristic of the MOS transistor without fixing the delay time, an unnecessary delay time may be set when a high-speed transistor is used in the push-pull circuit. Therefore, the duty control range is widened. Also,
Similarly, since the delay time can be set according to the drive characteristics of the MOS transistor without being fixed, even if a low speed transistor is used in the push-pull circuit, the push-side transistor and the pull-side transistor can be turned on at the same time. Without
As a result, even a low-speed transistor can be easily used without the risk of a shoot-through current, thus improving the degree of freedom in designing the push-pull circuit.

[Brief description of drawings]

FIG. 1A is a diagram showing a configuration of a push-pull drive circuit according to an embodiment, and FIG. 1B is an operation state diagram for explaining the operation thereof.

2A to 2F are timing charts for explaining the operation of the push-pull drive circuit according to the embodiment.

3 (a), (b), and (c) are timing charts for explaining the operation of the push-pull drive circuit when a slow-moving transistor is used.

FIG. 4 is a diagram showing another embodiment for driving a push-pull circuit composed of two n-MOS transistors in (a), (b).
Is a timing chart for explaining the operation.

FIG. 5 is an overall configuration diagram of a DC / DC converter in which a push-pull drive circuit is incorporated and used.

FIG. 6 (a) is a diagram showing a conventional push-pull drive circuit,
(b) is a timing chart showing the operation.

[Explanation of symbols]

10, 20 Push-pull drive circuit 11 Input terminal 12 OR circuit 13 AND circuit 14 p-MOS transistor M1 15 n-MOS transistor M2 16 Comparator Cmp1 17 Comparator Cmp2 18 n-MOS transistor M1-219 Inverter G1, G2, G1 ′ , G2 ', G1-2 drive signal (gate applied voltage) Vr1, Vr2, Vr12 drive threshold voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03K 19/0944 H03K 19/094 A

Claims (4)

[Claims] 1. A push-pull drive circuit for driving and controlling the push-pull drive circuit so as to turn on the other transistor after confirming that one of the push-side transistor and the pull-side transistor is off. 2. A first monitoring means for monitoring the gate voltage of the push-side transistor based on the input signal, and a drive signal based on the input signal to the gate of the pull-side transistor based on the monitoring result of the first monitoring means. A second switching means for monitoring the gate voltage of the pull-side transistor, and the input signal to the gate of the push-side transistor based on the monitoring result of the second monitoring means. A second switching means for outputting a driving signal based on the push-pull driving circuit. 3. The first monitoring means outputs a monitoring result signal when the gate voltage of the push-side transistor exceeds a predetermined voltage, and the first switching means outputs the monitoring result signal and the input signal. Is output to the gate of the pull-side transistor, the second monitoring means outputs a monitoring result signal when the gate voltage of the pull-side transistor becomes equal to or lower than a predetermined voltage, and the second switching 3. The push-pull driving circuit according to claim 2, wherein the means outputs a logical sum of the monitoring result signal and the input signal to the gate of the push-side transistor. 4. The first monitoring means outputs a monitoring result signal when the gate voltage of the push-side transistor becomes a predetermined voltage or less, and the first switching means outputs the monitoring result signal and the input signal. Is output to the gate of the pull-side transistor, the second monitoring means outputs a monitoring result signal when the gate voltage of the pull-side transistor becomes equal to or lower than a predetermined voltage, and the second switching 3. The push-pull driving circuit according to claim 2, wherein the means outputs a logical sum of the monitoring result signal and the input signal to the gate of the push-side transistor.