JP2001177380A - Comparator circuit and oscillation circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a comparator circuit, where a differential voltage range causing an analog output state is small and to realize an oscillation circuit that employs the comparator circuit and can reduce fluctuation in the oscillation frequency. SOLUTION: This comparator circuit is provided with a differential circuit to which a differential input signal is applied, a 1st current mirror circuit to which a 1st differential current of the differential circuit is applied, a 2nd current mirror circuit to which a 2nd differential current of the differential circuit is applied, a 3rd current mirror circuit to which an output current of the 1st current mirror circuit is given, an inverter circuit to which output current of the 2nd and 3rd current mirror circuit are given and that outputs the output signal, and a cross coupling switch circuit that supplies other differential current to itself, on the basis of one differential current of the differential circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit and an oscillation circuit using the same, and more particularly, to a comparison circuit having a small differential voltage range in an analog output state and reducing oscillation frequency fluctuation using the comparison circuit. Oscillation circuit that can

[0002]

2. Description of the Related Art A conventional RC oscillation circuit (hereinafter, simply referred to as an oscillation circuit) uses a resistor (R) and a capacitor (C) for setting a time constant, based on a time constant of charging and discharging of the capacitor. This is for determining the oscillation frequency.

FIG. 3 is a configuration block diagram showing an example of a conventional oscillation circuit. In FIG. 3, 1 is a resistor for setting a time constant, 2 is a capacitor for setting a time constant, 3 and 5 are switch circuits, 4 is a comparison circuit, 6 and 7 are constant voltage sources, 100 and 1
01 is a non-inverted input signal and an inverted input signal of the comparison circuit 4;
102 is a pulse output signal which is an output of the oscillation circuit.

One end of a resistor 1 is connected to one end of a capacitor 2, one end of a switch circuit 3, and a non-inverting input terminal of a comparison circuit 4. The output of the comparison circuit 4 is output as a pulse output signal 102 and as a control signal. Connected to control input terminals of switch circuits 3 and 5.

The output terminal of the switch circuit 5 is connected to the inverting input terminal of the comparison circuit 4, and the first and second input terminals of the switch circuit 5 are connected to one ends of constant voltage sources 6 and 7, respectively.

The other end of the resistor 1 and one power supply terminal of the comparison circuit 4 are connected to a positive voltage source "VDD", respectively.
The other end of the capacitor 2, the other end of the switch circuit 3, the other power supply terminal of the comparison circuit 4, and the other ends of the constant voltage sources 6 and 7 are grounded.

Now, the operation of the conventional example shown in FIG. 3 will be described with reference to FIG. FIG. 4 shows the non-inverted input signal 1 of the comparison circuit 4.
FIG. 6 is a timing chart showing an example of an operation waveform of 00 and a pulse output 102.

The switch circuit 3 is turned "ON" when the control signal is at "high level", and is turned "OFF" when the control signal is at "low level". On the other hand, the switch circuit 5
Selects the input terminal indicated by “B” in FIG. 3 when the control signal is “high level”, and selects the input terminal indicated by “A” in FIG. 3 when the control signal is “low level”.

The output voltage values of the constant voltage sources 6 and 7 are
When “V1” and “V2” are set, the relationship “V2> V1” is established.

In the area indicated by "AR01" in FIG. 4, since the output of the comparison circuit 4 which is a control signal is at "low level", the switch circuit 3 is turned "OFF" and the switch circuit 5 is set to "A" in FIG. "" Input terminal.

Therefore, the voltage value “V 2” is applied to the inverting input terminal of the comparison circuit 4, and the capacitor 2 is charged by the current flowing from the positive voltage source “VDD” via the resistor 1.

For example, as shown by "PR01" in FIG. 4, the capacitor 2 is charged with a time constant by the resistor 1 and the capacitor 2, so that the non-inverting input terminal of the comparison circuit 4 which is the voltage between the terminals of the capacitor 2. Voltage value increases.

When the voltage value of the non-inverting input terminal of the comparing circuit 4 exceeds the voltage value "V2" of the inverting input terminal, the output of the comparing circuit 4, which is the pulse output signal 102, becomes "high level".

A change in the output of the comparison circuit 4 causes "A" in FIG.
In the region indicated by “R02”, the output of the comparison circuit 4 which is a control signal is “high level”, and the switch circuit 3 is “ON”.
And the switch circuit 5 selects the input terminal "B" in FIG.

For this reason, the voltage value "V1" is applied to the inverting input terminal of the comparison circuit 4, and the electric charge charged through the switch circuit 3 flows to the ground level at both ends of the capacitor 2 and flows out. Discharged.

For example, as shown by "PR02" in FIG. 4, the charge of the capacitor 2 is discharged by the switch circuit 3, so that
The value of the voltage at the non-inverting input terminal of the comparison circuit 4, which is the voltage between the terminals of the capacitor 2, decreases in a short time.

When the voltage value of the non-inverting input terminal of the comparing circuit 4 becomes lower than "V1" which is the voltage value of the inverting input terminal, the output of the comparing circuit 4, which is the pulse output signal 102, becomes "low level". Then, the state returns to the area indicated by “AR03” in FIG. 4 (the same as “AR01” in FIG. 4).

As a result, the state shown by "AR01" and "AR02" in FIG. 4 is repeated by repeating the charging and discharging of the capacitor 2, so that the pulse output signal 102 having the cycle shown by "FQ01" in FIG. Can be obtained.

Also, by adjusting the values of the resistor 1 and the capacitor 2 to change the time constant, the width of the region indicated by “AR01” in FIG. 4 can be controlled. Becomes possible.

FIG. 5 is a circuit diagram showing a specific example of the comparison circuit 4. As shown in FIG. In FIG. 5, 100, 101 and 10
2 has the same reference numerals as in FIG. In FIG.
9, 11, 12, 13, 14, 15, 16, 17 and 1
8 is a MOSFET ((Metal Oxide Semiconductor Field
Effect Transistor: Hereinafter, simply referred to as FET. ), 1
0 is a constant current source.

Further, in FIG. 5, 8 to 10 denote a differential circuit 50, 11 and 13 denote a current mirror circuit 51, 12
And 14 constitute a current mirror circuit 52, 15 and 16 constitute a current mirror circuit 53, and 17 and 18 constitute an inversion circuit 54, respectively.

The non-inverted input signal 100 which is a differential input signal
The inverted input signal 101 is connected to the gates of the FETs 8 and 9, and the source of the FET 8 is connected to the source of the FET 9 and one end of the constant current source 10.

The drain of FET 8 is connected to FETs 11 and 13.
, And the drain of the FET 11, respectively.
The drain of FET 9 is connected to the gates of FETs 12 and 14 and F
Each is connected to the drain of ET12.

The drain of the FET 13 is connected to the FETs 15 and 1
6 and the drain of the FET 15, respectively. The drain of the FET 14 is the drain of the FET 16,
Connected to the gates of ET17 and ET18, respectively.

The drain of the FET 17 is connected to the drain of the FET 18 and outputs a pulse output signal 102.

The other end of the constant current source 10, the FET 15,
The sources of 16 and 17 are connected to a positive voltage source "VDD", respectively, and the other ends of the FETs 11, 12, 13, 14 and 18 are grounded (connected to a "0 V" voltage source).

Here, the operation of the comparison circuit shown in FIG.
This will be described with reference to FIG. FIG. 6 shows the characteristics of the drain currents of the FETs 8, 9, 11 and 12 and the output "Vcomp" before being inverted by the inverting circuit 54 (hereinafter simply referred to as "Vcomp") with respect to the change of the differential input signal. It is a characteristic curve figure which shows a relationship.

[0028] In FIGS. 6 (a) non-inverted input signal is a differential input signal 100 "V _100" and the inverted input signal 101 "V
₁₀₁ ", (b) shows drain current" I ₈ "of FETs 8 and 9;
And "I ₉ ", (c) are drain currents "I ₁₁ " and "I ₁₂ " of the FETs ₁₁ and _{12, respectively} . (D) shows each characteristic curve of the output "Vcomp". The horizontal axis difference voltage "V _{10 0}
−V ₁₀₁ ″.

[0029] changes as difference voltage "V ₁₀₀ -V _101" in FIG. 6, in other words, when the differential input signal is changed as shown in FIG. 6 (a), constitute a differential circuit 50 FET
A drain current flows through 8 and 9 as shown in FIG.

Then, "V" shown in "AR11" in FIG.
_In the region where ₁₀₁ > V ₁₀₀ ″, the drain current “I ₈ ” flowing through the FET 8 flows as it is as the drain current “I ₁₁ ” of the FET ₁₁ as shown in FIG.

Since the FETs 11 and 13 form a current mirror circuit 51, the same current flows through the FET 13 as a drain current. This drain current further flows through the FETs 15 and 16 constituting the current mirror circuit 53.

On the other hand, the drain current “I” flowing through the FET 9
₉ ”flows as it is as the drain current“ I ₁₂ ”of the FET 12. Further, since the FETs 12 and 14 constitute the current mirror circuit 52, the same current flows through the FET 14 as the drain current.

However, since the drain current flowing through the FET 14 is much smaller than the drain current flowing through the FET 16, the output "Vcomp" has substantially the same value as the positive voltage source "VDD" as shown in FIG. Become.

On the other hand, in a region where “V ₁₀₁ <V ₁₀₀ ” indicated by “AR 12” in FIG. 6, as shown in FIG. 6C, the drain current “I ₉ ” flowing through the FET ₉ is directly applied to the FET 12. Flows as the drain current “I ₁₂ ”.

Since the FETs 12 and 14 form a current mirror circuit 52, the same current flows through the FET 14 as a drain current.

On the other hand, the drain current “I” flowing through the FET 8
₈ ”flows as it is as the drain current“ I ₁₁ ”of the FET _11. Further, since the FETs ₁₁ and 13 constitute the current mirror circuit 51, the same value current also flows as the drain current to the FET 13. Further, the drain current is further increased. FETs 15 and 1 constituting current mirror circuit 53
6 will flow.

However, since the drain current flowing through the FET 16 is much smaller than the drain current flowing through the FET 14, the output "Vcomp" has substantially the same value as the ground level as shown in FIG.

Here, the output "V" is output from the inverting circuit 54.
If “comp” is the value of the positive voltage source, the FET 17
At "F", the FET 18 is turned "ON" and the pulse output signal 102 becomes "low level".

Similarly, if the output "Vcomp" is at the ground level, the FET 17 is "ON" and the FET 18 is "O".
FF ”and the pulse output signal 102 is“ high level ”
become.

[0040]

However, in FIG. 4, when the voltage of the non-inverting input signal 100 rises more slowly than the voltage drop, the rising speed decreases near the threshold voltage "V2". As a result, the voltage change with respect to the time change becomes small.

For this reason, noise and the like are caused by the non-inverted input signal 10.
In the case of superimposition on 0, the output level of the comparison circuit 4 may be switched before reaching the threshold voltage “V2”, and the oscillation frequency of the resulting pulse output signal 102 fluctuates (jitter). There was a problem that it would happen.

This problem is because the gain of the comparison circuit is finite, so that when the difference between the differential input signals becomes small, the logic level becomes a value that has no particular one, resulting in an unstable state. That is, in the area indicated by "AR13" in FIG. 6, the differential circuit 50 is an analog operation area, and in such an area, the output of the comparison circuit is easily affected by noise. Accordingly, an object of the present invention is to provide a comparison circuit having a small differential voltage range in an analog output state and an oscillation circuit using the same, which can reduce fluctuations in oscillation frequency. .

[0043]

In order to achieve the above object, according to a first aspect of the present invention, in a comparison circuit, a differential circuit to which a differential input signal is applied and a differential circuit to which the differential input signal is applied are provided. A first current mirror circuit to which a first differential current of a driving circuit is connected, a second current mirror circuit to which a second differential current of the differential circuit is connected, and the first current mirror A third current mirror circuit to which an output current of the circuit is connected, and output currents of the second and third current mirror circuits to be connected;
By providing an inverting circuit that outputs an output signal and a cross-coupling switch circuit that passes the other differential current to itself based on one differential current of the differential circuit, an analog output state is obtained. The comparison circuit has a small differential voltage range, and can effectively reduce the difference between the differential input signals that become unstable.

According to a second aspect of the present invention, in the comparison circuit according to the first aspect, the cross-coupling switch circuit includes a first and a second differential current of the differential circuit connected to a gate and a drain. Connected first MOSFET
And the first and second differential currents of the differential circuit are constituted by the second MOSFET connected to the drain and the gate, so that the differential voltage range in which the analog output state is obtained is small. It becomes a circuit, and the difference between the differential input signals that becomes unstable can be effectively reduced.

According to a third aspect of the present invention, in the comparison circuit according to the first aspect, the differential circuit includes a constant current source and an output current of the constant current source connected to respective sources. 1 outputs a differential current from each drain based on the differential input signal connected to the gate of
With the configuration including the pair of MOSFETs, the comparison circuit has a small differential voltage range in an analog output state, and can effectively reduce the difference between differential input signals in an unstable state.

According to a fourth aspect of the present invention, in the comparison circuit according to the first aspect, the first to third current mirror circuits have a source connected to a voltage source and an input current connected to a drain and a gate. A first MOSFET connected to a voltage source, a second MOSFET connected to an input current of the gate and outputting an output current from the drain.
By using the ET and the ET, a comparison circuit having a small differential voltage range in an analog output state can be obtained, and the difference between differential input signals in an unstable state can be effectively reduced.

According to a fifth aspect of the present invention, in the comparison circuit according to the first aspect, the inverting circuit has one source connected to a high voltage side and the other source connected to a low voltage side. The output currents of the second and third current mirror circuits are connected to the gates connected to each other, and the pair of MOSFETs output an output signal from the drains connected to each other. The comparison circuit has a small differential voltage range in an output state, and can effectively reduce a difference between differential input signals in an unstable state.

According to a sixth aspect of the present invention, the use of the comparison circuit according to the first aspect of the present invention in an oscillation circuit makes it possible to prevent fluctuations in the oscillation frequency.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration circuit diagram showing one embodiment of a comparison circuit according to the present invention. In FIG. 1, 8 to 18, 100,
Reference numerals 101, 50, 51, 52, 53 and 54 denote the same reference numerals as in FIG. 5, 19 and 20 denote FETs, and 103 denotes an output signal as a comparison result. 19 and 20 constitute a cross coupling switch circuit 55.

The non-inverted input signal 100 which is a differential input signal
The inverted input signal 101 is connected to the gates of the FETs 8 and 9, and the source of the FET 8 is connected to the source of the FET 9 and one end of the constant current source 10.

The drain of the FET 8 is connected to the gates of the FETs 11, 13 and 19 and the drains of the FETs 11 and 20, respectively.
20 and the drains of FETs 12 and 19, respectively.

The drain of the FET 13 is connected to the FETs 15 and 1
6 and the drain of the FET 15, respectively. The drain of the FET 14 is the drain of the FET 16,
Connected to the gates of ET17 and ET18, respectively.

The drain of the FET 17 is connected to the drain of the FET 18 and outputs an output signal 103.

The other end of the constant current source 10, the FET 15,
The sources of 16 and 17 are connected to a positive voltage source "VDD", respectively, and FETs 11, 12, 13, 14, 18, 19
And 20 are respectively grounded (connected to a voltage source of "0 V").

Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows that F
The drain currents of the ETs 8, 9, 11, 12, 19 and 20 and the output "Vcomp '" before the output is inverted by the inversion circuit 54.
FIG. 11 is a characteristic curve diagram showing a relationship between characteristics of the output (hereinafter, simply referred to as an output “Vcomp ′”).

FIG. 2A shows a non-inverted input signal 100 "V ₁₀₀ " and an inverted input signal 101 "V which are differential input signals.
₁₀₁ ", (b) shows drain current" I ₈ "of FETs 8 and 9;
And "I _9", (c) the drain current "I _11" of FET11 and 12 and "I _12", (d) the FET19 and 2
Drain currents “I ₁₉ ” and “I ₂₀ ” of 0 and (e) show respective characteristic curves of the output “Vcomp ′”. The horizontal axis indicates the difference voltage “V ₁₀₀ −V ₁₀₁ ”.

[0057] changes as difference voltage "V ₁₀₀ -V _101" in FIG. 2, in other words, when the differential input signal is changed as shown in FIG. 2 (a), constitute a differential circuit 50 FET
Drain currents 8 and 9 flow as shown in FIG.

Then, "V" shown in "AR21" in FIG.
_In the region where ₁₀₁ > V ₁₀₀ ″, the drain current “I ₈ ” flowing through the FET 8 flows as it is as the drain current “I ₁₁ ” of the FET ₁₁ as shown in FIG.

Further, since the FETs 11 and 13 constitute the current mirror circuit 51, the same current flows through the FET 13 as a drain current. This drain current further flows through the FETs 15 and 16 constituting the current mirror circuit 53.

However, since the gate of the FET 19 is also connected to the gate of the FET 11 and the like constituting the current mirror circuit 51, the drain current "I ₉ " of the FET 19 originally flowing from the FET 9 to the FET 12 is shown in FIG. As shown in (1), the drain current of the FET ₁₉ itself flows as "I ₁₉ ".

For this reason, “V” shown in “AR21” in FIG.
2C, the drain current “I ₁₂ ” of the FET ₁₂ stops flowing in the region where ₁₀₁ > V ₁₀₀ ”. Further, since the drain current“ I ₁₂ ”does not flow in the FET 12, the drain current also flows in the FET 14. Stops flowing.

Accordingly, no drain current flows through the FET 14, in other words, the drain current flowing through the FET 14 is much smaller than the drain current flowing through the FET 16, so that the output "Vcomp '" becomes as shown in FIG. At the same time as the positive voltage source "VDD".

On the other hand, in a region where “V ₁₀₁ <V ₁₀₀ ” indicated by “AR 22” in FIG. 2, as shown in FIG. 2C, the drain current “I ₉ ” flowing through the FET ₉ is directly applied to the FET 12. Flows as the drain current “I ₁₂ ”.

Since the FETs 12 and 14 form the current mirror circuit 52, the same current flows through the FET 14 as a drain current.

However, since the gate of the FET 20 is also connected to the gate of the FET 12 and the like constituting the current mirror circuit 52, the FET 20 uses the drain current “I ₈ ” that the FET 8 has conventionally flowed through the FET 11 in FIG. As shown in (1), the drain current of the FET ₂₀ itself flows as “I ₂₀ ”.

For this reason, "V" shown in "AR22" in FIG.
2C, the drain current “I ₁₁ ” of the FET ₁₁ does not flow in the region where ₁₀₁ <V ₁₀₀ ”, and the drain current“ I ₁₁ ”does not flow in the FET ₁₁ so that the drain current also flows in the FET 13. Does not flow.
The drain current does not flow through the FETs 15 and 16 of the current mirror circuit 53 through which the drain current has flowed.

Accordingly, no drain current flows through the FET 16, in other words, the drain current flowing through the FET 16 is much smaller than the drain current flowing through the FET 14, so that the output "Vcomp '" becomes as shown in FIG. The value is almost the same as the ground level.

Here, the output “V” is output from the inverting circuit 54.
If comp ′ ”is the value of the positive voltage source, the FET 17
F ”, the FET 18 is turned“ ON ”and the output signal 103
Becomes "low level".

Similarly, if the output "Vcomp '" is at the ground level, the FET 17 is "ON" and the FET 18 is "ON".
OFF ", and the output signal 103 becomes" high level ".

That is, as shown by "AR23" in FIG.
The difference between the differential input signals becomes smaller and
When the current values of the drain currents of FIG.
"V" shown in the middle "AR21"₁₀₁> V₁₀₀In the area that is "
The drain current “I” of the FET 19 ₁₉FET20
Drain current “I”₂₀Becomes larger, the operation becomes FET2
It switches sharply to the 0 side.

For this reason, the switching of the output “Vcomp ′” in the region where the difference between the differential input signals is small becomes sharp, and
The logic level does not have a value that neither has, and an unstable state can be avoided. In other words, the differential voltage range in which the output state is analog becomes smaller.

As a result, by adding the cross-coupling switch circuit 55 to the current mirror circuits 51 and 52, a comparison circuit having a very small differential voltage range to be in an analog output state can be obtained.

Further, by using such a comparison circuit in an oscillation circuit, fluctuations in the oscillation frequency can be reduced.

Although the MOSFET is exemplified as the transistor in the embodiment shown in FIG. 1, a normal bipolar transistor or the like may be used.

[0075]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first to fifth aspects of the present invention, an analog output state is provided by adding, to the current mirror circuit, a cross coupling switch circuit that allows the other differential current to flow through itself based on one differential current. The comparison circuit has a small differential voltage range, and the difference between the differential input signals that becomes unstable can be effectively reduced.

Further, according to the invention of claim 6, by using such a comparison circuit for an oscillation circuit, it is possible to reduce the fluctuation of the oscillation frequency.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram showing an embodiment of a comparison circuit according to the present invention.

FIG. 2 is a characteristic curve diagram showing a relationship between a drain current and a characteristic of an output “Vcomp ′” with respect to a change in a differential input signal.

FIG. 3 is a configuration block diagram illustrating an example of a conventional oscillation circuit.

FIG. 4 is a timing chart showing an example of an operation waveform and a pulse output of a non-inverting input signal.

FIG. 5 is a configuration circuit diagram showing a specific example of a comparison circuit.

FIG. 6 is a characteristic curve diagram showing a relationship between a drain current and a characteristic of an output “Vcomp” with respect to a change in a differential input signal.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 resistance 2 capacitance 3,5 switch circuit 4 comparison circuit 6,7 constant voltage source 8,9,11,12,13,14,15,16,17,
18, 19, 20 MOSFET 10 Constant current source 50 Differential circuit 51, 52, 53 Current mirror circuit 54 Inverting circuit 55 Cross-coupling switch circuit 100 Non-inverting input signal 101 Inverting input signal 102 Pulse output signal 103 Output signal

Claims (6)

[Claims] A differential circuit to which a differential input signal is applied; a first current mirror circuit to which a first differential current of the differential circuit is connected; A second current mirror circuit to which a second differential current is connected; and a third current terminal to which an output current of the first current mirror circuit is connected.
A current mirror circuit, an output circuit of the second and third current mirror circuits is connected, and an inverting circuit that outputs an output signal; and a differential current of the differential circuit based on one differential current. A comparison circuit comprising a cross-coupling switch circuit flowing to itself. 2. The cross-coupling switch circuit includes: a first MOSFET having first and second differential currents of the differential circuit connected to a gate and a drain; and a first and a second MOSFET of the differential circuit. 2. The comparison circuit according to claim 1, wherein the two differential currents comprise a second MOSFET connected to a drain and a gate. 3. A differential circuit comprising: a constant current source; an output current of the constant current source connected to a respective source; and a differential current source connected to a respective gate. 2. The comparison circuit according to claim 1, comprising a pair of MOSFETs for outputting a dynamic current. 4. The first to third current mirror circuits include: a first MOSFET having a source connected to a voltage source and an input current connected to a drain and a gate; and a source connected to a voltage source and having an input current. A second MOS connected to the gate and outputting an output current from the drain
2. The comparison circuit according to claim 1, wherein the comparison circuit comprises an FET. 5. The inverting circuit, wherein one source is connected to a high voltage side voltage source and the other source is connected to a low voltage side voltage source, respectively, and gates of the second and third current mirror circuits are connected to gates connected to each other. 2. The comparison circuit according to claim 1, further comprising a pair of MOSFETs connected to an output current and outputting an output signal from drains connected to each other. 6. An oscillation circuit using the comparison circuit according to claim 1.