CN208386513U - Music control switching circuit and device - Google Patents
Music control switching circuit and device Download PDFInfo
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- CN208386513U CN208386513U CN201820993077.7U CN201820993077U CN208386513U CN 208386513 U CN208386513 U CN 208386513U CN 201820993077 U CN201820993077 U CN 201820993077U CN 208386513 U CN208386513 U CN 208386513U
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Abstract
The utility model is suitable for audio play-back technology field, provide a kind of music control switching circuit, control module respectively with frequency of oscillation module, beat module, address module, memory array setup module, programmable logic array setup module is connected with output module, frequency of oscillation module respectively with audio-frequency module, acceleration module is connected with beat module, beat module respectively with acceleration module, memory array setup module, programmable logic array setup module, address module, audio-frequency module is connected with output module, address module is connect with memory array setup module, memory array setup module is connect with programmable logic array setup module and acceleration module respectively, programmable logic array setup module is connect with audio-frequency module, audio-frequency module is connect with output module, output module is connect with external audible device.Music control switching circuit provided by the utility model, may be implemented being switched fast for music, handoff procedure is steadily smooth.
Description
Technical field
The utility model belongs to audio play-back technology field more particularly to a kind of music control switching circuit and device.
Background technique
With the fast development of science and technology, various electronic products have been come into people's lives, and people can be with
It the various recreations such as conversed by different electronic products, see TV and listen to music, wherein the sound of music can be played
Happy electronic product is even more to be liked by numerous music-lovers.More songs are all stored in existing music electronic product to supply
User's selection, but music electronic product switch speed in music handoff procedure in part is slow, is easy to happen Caton.
Utility model content
In view of this, the utility model embodiment provides a kind of music control switching circuit and device, it is existing to solve
The problem of happy electronic product of partial switch speed in music handoff procedure is slow in the middle part of technology, is easy to happen Caton.
The utility model embodiment provides a kind of music control switching circuit, including control module, frequency of oscillation module,
Beat module, address module, memory array setup module, programmable logic array setup module, acceleration module, audio-frequency module
And output module；
The control module receives externally input push button signalling, the control module respectively with the frequency of oscillation mould
Mould is arranged in block, the beat module, the address module, the memory array setup module, the programmable logic array
Block is connected with the output module, the frequency of oscillation module respectively with the audio-frequency module, the acceleration module and the section
Module connection is clapped, the beat module is patrolled with the acceleration module, the memory array setup module, described may be programmed respectively
Volume array setup module, the address module, the audio-frequency module are connected with the output module, the address module with it is described
Memory array setup module connection, the memory array setup module respectively with the programmable logic array setup module
It is connected with the acceleration module, the programmable logic array setup module is connect with the audio-frequency module, the audio-frequency module
It is connect with the output module, the output module is connect with external audible device.
Further, the control module includes power on reset unit and control unit；
Described control unit receives externally input push button signalling, and the power on reset unit and described control unit connect
Connect, described control unit respectively with the frequency of oscillation module, the beat module, the memory array setup module, institute
It states programmable logic array setup module to connect with the output module, the power on reset unit and the address module connect
It connects.
Further, the power on reset unit includes phase inverter inv1, phase inverter inv2, phase inverter inv3, PMOS tube
M1 and polar capacitor C1；
The source level of PMOS tube M1 is connect with power vd D, and the grid of PMOS tube M1 is connect with ground GND, the drain electrode of PMOS tube M1
It is connect respectively with the input terminal of the anode of polar capacitor C1 and phase inverter inv1, the cathode of polar capacitor C1 is connect with ground GND, instead
Phase device inv1, phase inverter inv2 and phase inverter inv3 are sequentially connected in series, the output end of phase inverter inv3 respectively with described control unit
It is connected with the address module.
Further, described control unit include phase inverter inv4, phase inverter inv5, phase inverter inv6, phase inverter inv7,
Phase inverter inv8, phase inverter inv9, phase inverter inv10, phase inverter inv11, phase inverter inv12, phase inverter inv13, phase inverter
Inv14, phase inverter inv15, phase inverter inv16, nor gate N1, nor gate N2, nor gate N3, nor gate N4, nor gate N5 or
NOT gate N6, nor gate N7, polar capacitor C2, polar capacitor C3 and ZDR module I 1；
The input terminal of phase inverter inv4 is connect with the frequency of oscillation module, and phase inverter inv4 successively goes here and there with phase inverter inv5
Connection, the output end of phase inverter inv5 are connect with the input terminal CK of ZDR module I 1, the input terminal CKB and phase inverter of ZDR module I 1
The input terminal of inv5 connects, and the input terminal D of ZDR module I 1 is connect with the output end of phase inverter inv12, the output of ZDR module I 1
End Q is connect with the input terminal of phase inverter inv6, and phase inverter inv6 is sequentially connected in series with phase inverter inv7, the output end of phase inverter inv7
The cathode of the anode connection of the input terminal B and polar capacitor C2 of AND OR NOT gate N1 respectively, polar capacitor C2 is connect with ground GND, or
The input terminal A of NOT gate N1 is connect with the input terminal of phase inverter inv7, and the input terminal A of the output end AND OR NOT gate N2 of nor gate N1 connects
It connects, the output end connection of the input terminal B AND OR NOT gate N4 of nor gate N2, the input terminal of the output end AND OR NOT gate N4 of nor gate N2
A connection；
The input terminal of phase inverter inv8 is connect with the beat module, and phase inverter inv8 is sequentially connected in series with phase inverter inv9,
The anode connection of the input terminal B and polar capacitor C3 of the output end difference AND OR NOT gate N3 of phase inverter inv9, polar capacitor C3's
Cathode with ground GND connect, the input terminal A of nor gate N3 is connect with the input terminal of phase inverter inv9, the output end of nor gate N3 and
The input terminal B connection of nor gate N4, the input terminal C of nor gate N4 are connect with the power on reset unit, the output of nor gate N4
End is connect with the input terminal of phase inverter inv10, and phase inverter inv10 and phase inverter inv11 are sequentially connected in series, and phase inverter inv11's is defeated
Outlet is connect with the beat module；
The input terminal of phase inverter inv12 inputs the push button signalling, and the output end AND OR NOT gate N5's of phase inverter inv12 is defeated
Enter B is held to connect, the output end connection of the input terminal A AND OR NOT gate N7 of nor gate N5, the input terminal C and phase inverter of nor gate N5
The output end of inv11 connects, the output end of nor gate N5 pass sequentially through concatenated phase inverter inv13 and phase inverter inv14 with or
The input terminal B connection of NOT gate N6, the input terminal A of nor gate N6 are connect with the control module, the output end of nor gate N6 and anti-
The input terminal of phase device inv15 connects, the output end of phase inverter inv15 respectively with the frequency of oscillation module and the beat module
Connection, the output end of phase inverter inv13 respectively with the frequency of oscillation module, the memory array setup module, it is described can
Programmed logic array (PLA) setup module is connected with the output module；
The input terminal of phase inverter inv16 is connect with the beat module, the output end AND OR NOT gate N7's of phase inverter inv16
Input terminal B connection, the input terminal A of nor gate N7 are connect with the control module, the input terminal C AND OR NOT gate N5's of nor gate N7
Output end connection, the input terminal A connection of the output end AND OR NOT gate N5 of nor gate N7.
Further, the frequency of oscillation module includes oscillating unit and frequency unit；
The oscillating unit is connect with the frequency unit, the oscillating unit respectively with the control module and the sound
Frequency module connection, the frequency unit are connect with the control module, the beat module and the acceleration module respectively.
Further, the beat module includes that the first register setting unit, the first output unit and the second output are single
Member；
The first register setting unit is connect with first output unit, first output unit and described the
The connection of two output units, the first register setting unit are connect with the acceleration module, the first output unit difference
It is connect with the control module, the frequency of oscillation module, the memory array setup module and the address module, it is described
Second output unit is connect with the programmable logic array setup module, the audio-frequency module and the output module respectively.
Further, the acceleration module includes the second register setting unit；
The second register setting unit respectively with the frequency of oscillation module, the memory array setup module and
The beat module connection.
Further, the audio-frequency module includes third register setting unit and third output unit；
The third register setting unit is connect with the third output unit, the third register setting unit point
Do not connect with the frequency of oscillation module and the programmable logic array setup module, the third output unit respectively with institute
Beat module is stated to connect with the output module.
Further, the output module includes phase inverter inv38, phase inverter inv39, phase inverter inv40, phase inverter
Inv41, phase inverter inv42, phase inverter inv43, phase inverter inv44, phase inverter inv45, NAND gate N19, NAND gate N20 and with
NOT gate N21；
The input terminal of phase inverter inv38 is connect with the beat module, the output end and NAND gate N19 of phase inverter inv38
Input terminal A connection, the input terminal B of NAND gate N19 connect with the audio-frequency module 18, the output end of NAND gate N19 respectively with
The input terminal B of NAND gate N20 is connected with the input terminal of phase inverter inv39, the input terminal A of NAND gate N20 and the control module
Connection, the output end of NAND gate N20 are connect with the input terminal of phase inverter inv40, phase inverter inv40, phase inverter inv41 and reverse phase
Device inv42 is sequentially connected in series, and the output end of phase inverter inv42 is connect with the external audible device, the output end of phase inverter inv39
It is connect with the input terminal A of NAND gate N21, the output end B of NAND gate N21 is connect with the control module, the output of NAND gate N21
End is connect with the input terminal of phase inverter inv43, and phase inverter inv43, phase inverter inv44 and phase inverter inv45 are sequentially connected in series, reverse phase
The output end of device inv45 is connect with the external audible device.
The utility model embodiment additionally provides a kind of music including music control switching circuit in above-mentioned technical proposal
Switching device.
The beneficial effect of music control switching circuit and device provided by the utility model is: compared with prior art,
Music control switching circuit provided by the utility model receives externally input push button signalling, control module root by control module
Music switching signal is sent according to push button signalling and gives beat module, and frequency of oscillation module sends the first predeterminated frequency signal to section
Module is clapped, acceleration module sends broadcasting speed signal and gives beat module, and when carrying out music switching, beat module is exported to address
The carry driving signal of module high frequency, can play to be switched music within a very short time, and realization is switched fast music
Function, after the completion of music switching, beat module is using broadcasting speed signal as input signal, then passes through address module, storage
Device array setup module, programmable logic array setup module, audio-frequency module and output module switch according to normal speed forward
Music afterwards, music handoff procedure is quick and smooth, greatly improves user experience.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only that this is practical new
Some embodiments of type for those of ordinary skill in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of music control switching circuit provided by the embodiment of the utility model；
Fig. 2 is the circuit structure diagram of power on reset unit provided by the embodiment of the utility model；
Fig. 3 is the circuit structure diagram of control unit provided by the embodiment of the utility model；
Fig. 4 is the circuit structure diagram of key-press input unit provided by the embodiment of the utility model；
Fig. 5 is the circuit structure diagram of the first register setting unit provided by the embodiment of the utility model；
Fig. 6 is the circuit structure diagram of the first output unit provided by the embodiment of the utility model；
Fig. 7 is the circuit structure diagram of the second output unit provided by the embodiment of the utility model；
Fig. 8 is the circuit structure diagram of the second register setting unit provided by the embodiment of the utility model；
Fig. 9 is the circuit structure diagram of output module provided by the embodiment of the utility model.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the utility model embodiment.However, it will be clear to one skilled in the art that there is no these
The utility model also may be implemented in the other embodiments of detail.In other situations, omit to well-known system,
The detailed description of apparatus, circuit and method, in case unnecessary details interferes the description of the utility model.
In order to illustrate technical solution described in the utility model, the following is a description of specific embodiments.
Refering to fig. 1, music control switching circuit provided by the embodiment of the utility model, including control module 11, oscillation frequency
Rate module 12, beat module 13, address module 14, memory array setup module 15, programmable logic array setup module 16,
Acceleration module 17, audio-frequency module 18 and output module 19；
The control module 11 respectively with the frequency of oscillation module 12, the beat module 13, the address module 14,
The memory array setup module 15, the programmable logic array setup module 16 and the output module 19 connect, institute
Frequency of oscillation module 12 is stated to connect with the audio-frequency module 18, the acceleration module 17 and the beat module 13 respectively, it is described
Beat module 13 is set with the acceleration module 17, the memory array setup module 15, the programmable logic array respectively
It sets module 16, the address module 14, the audio-frequency module 18 and the output module 19 to connect, the address module 14 and institute
The connection of memory array setup module 15 is stated, the memory array setup module 15 is set with the programmable logic array respectively
It sets module 16 and the acceleration module 17 connects, the programmable logic array setup module 16 connects with the audio-frequency module 18
It connects, the audio-frequency module 18 is connect with the output module 19, and the output module 19 is connect with external audible device 20；
The control module 11 receives externally input push button signalling, sends music switching signal according to the push button signalling
To the beat module 13, first predeterminated frequency signal of the transmission of frequency of oscillation module 12 is described to the beat module 13
Beat module 13 sends carry driving according to the music switching signal, the first predeterminated frequency signal and broadcasting speed signal
Signal gives the address module 14, and the address module 14 sends address signal to the storage according to the carry driving signal
Device array setup module 15, the memory array setup module 15 export divisor code, the speed according to the address signal
It spends module 17 and the broadcasting speed signal is exported according to the divisor code, the programmable logic array module 16 is according to described
Divisor code sends audio coding signal to the audio-frequency module 18, and the audio-frequency module 18 is defeated according to the audio coding signal
The audio signal of predeterminated frequency out, the output module 19 drive the external hair according to the audio signal of the predeterminated frequency
Acoustic equipment 20 carries out sounding.
Specifically, the divisor in the present embodiment represents frequency dividing multiple, and a piece of music includes multiple notes, be can according to need
Total note number in address module, multiple frequency dividing devices are set, for example, note sum is 768, give more songs, every head sound
Happy note is beyond count identical, according to 28× 3=768 can determine that address module 14 includes 8 two divided-frequency devices and 1 three points
Frequency device, and a group address signal A0B~A9B is sent to memory array setup module 15, memory array setup module
15 corresponding divisor code D<the 0>~D<7>of output, programmable logic array setup module 16 is according to divisor code D<4>~D<7
>, corresponding audio coding signal is exported to audio-frequency module 18, determines the frequency of audio signal, mould is arranged in programmable logic array
Block 16 also exports null signals SB to beat module 13.
The beneficial effect of music control switching circuit and device provided by the utility model is: compared with prior art,
Music control switching circuit provided by the utility model receives externally input push button signalling, control module root by control module
Music switching signal is sent according to push button signalling and gives beat module, and frequency of oscillation module sends the first predeterminated frequency signal to section
Module is clapped, acceleration module sends broadcasting speed signal and gives beat module, and when carrying out music switching, beat module is exported to address
The carry driving signal of module high frequency, can play to be switched music within a very short time, and realization is switched fast music
Function, after the completion of music switching, beat module is using broadcasting speed signal as input signal, then passes through address module, storage
Device array setup module, programmable logic array setup module, audio-frequency module and output module switch according to normal speed forward
Music afterwards, music handoff procedure is quick and smooth, greatly improves user experience.
Refering to Fig. 2 and Fig. 3, further, the control module 11 includes power on reset unit and control unit；
Described control unit receives externally input push button signalling, and the power on reset unit and described control unit connect
Connect, described control unit respectively with the frequency of oscillation module 12, the beat module 13, the memory array setup module
15, the programmable logic array setup module 16 and the output module 19 connect, and the power on reset unit is with described
Location module 14 connects；
When the control module 11 powers on, the power on reset unit sends power-on reset signal to the control respectively
Unit and the address module 14, described control unit and the address module 14 are powered on according to the power-on reset signal
It resets, described control unit receives externally input push button signalling, sends music switching signal to institute according to the push button signalling
State beat module 13.
Further, the power on reset unit includes phase inverter inv1, phase inverter inv2, phase inverter inv3, PMOS tube
M1 and polar capacitor C1；
The source level of PMOS tube M1 is connect with power vd D, and the grid of PMOS tube M1 is connect with ground GND, the drain electrode of PMOS tube M1
It is connect respectively with the input terminal of the anode of polar capacitor C1 and phase inverter inv1, the cathode of polar capacitor C1 is connect with ground GND, instead
Phase device inv1, phase inverter inv2 and phase inverter inv3 are sequentially connected in series, the output end of phase inverter inv3 respectively with described control unit
It is connected with the address module 14.
Specifically, the output end of phase inverter inv3 exports power-on reset signal POR, and power-on reset signal POR is distinguished
It is sent to control unit and address module 14, it is made to carry out electrification reset.
Further, described control unit include phase inverter inv4, phase inverter inv5, phase inverter inv6, phase inverter inv7,
Phase inverter inv8, phase inverter inv9, phase inverter inv10, phase inverter inv11, phase inverter inv12, phase inverter inv13, phase inverter
Inv14, phase inverter inv15, phase inverter inv16, nor gate N1, nor gate N2, nor gate N3, nor gate N4, nor gate N5 or
NOT gate N6, nor gate N7, polar capacitor C2, polar capacitor C3 and ZDR module I 1；
The input terminal of phase inverter inv4 is connect with the frequency of oscillation module 12, and phase inverter inv4 and phase inverter inv5 are successively
Series connection, the output end of phase inverter inv5 are connect with the input terminal CK of ZDR module I 1, the input terminal CKB and phase inverter of ZDR module I 1
The input terminal of inv5 connects, and the input terminal D of ZDR module I 1 is connect with the output end of phase inverter inv12, the output of ZDR module I 1
End Q is connect with the input terminal of phase inverter inv6, and phase inverter inv6 is sequentially connected in series with phase inverter inv7, the output end of phase inverter inv7
The cathode of the anode connection of the input terminal B and polar capacitor C2 of AND OR NOT gate N1 respectively, polar capacitor C2 is connect with ground GND, or
The input terminal A of NOT gate N1 is connect with the input terminal of phase inverter inv7, and the input terminal A of the output end AND OR NOT gate N2 of nor gate N1 connects
It connects, the output end connection of the input terminal B AND OR NOT gate N4 of nor gate N2, the input terminal of the output end AND OR NOT gate N4 of nor gate N2
A connection；
The input terminal of phase inverter inv8 is connect with the beat module 13, and phase inverter inv8 successively goes here and there with phase inverter inv9
Connection, the anode connection of the input terminal B and polar capacitor C3 of the output end difference AND OR NOT gate N3 of phase inverter inv9, polar capacitor C3
Cathode with ground GND connect, the input terminal A of nor gate N3 is connect with the input terminal of phase inverter inv9, the output end of nor gate N3
The input terminal B connection of AND OR NOT gate N4, the input terminal C of nor gate N4 are connect with the power on reset unit, and nor gate N4's is defeated
Outlet is connect with the input terminal of phase inverter inv10, and phase inverter inv10 and phase inverter inv11 are sequentially connected in series, phase inverter inv11's
Output end is connect with the beat module 13；
The input terminal of phase inverter inv12 inputs the push button signalling TRIB, the output end AND OR NOT gate N5 of phase inverter inv12
Input terminal B connection, the input terminal A AND OR NOT gate N7 of nor gate N5 output end connection, the input terminal C and reverse phase of nor gate N5
The output end of device inv11 connects, the output end of nor gate N5 pass sequentially through concatenated phase inverter inv13 and phase inverter inv14 with
The input terminal B connection of nor gate N6, the input terminal A of nor gate N6 are connect with the control module 11, the output end of nor gate N6
Connect with the input terminal of phase inverter inv15, the output end of phase inverter inv15 respectively with the frequency of oscillation module 12 and the section
It claps module 13 to connect, mould is arranged with the frequency of oscillation module 12, the memory array respectively in the output end of phase inverter inv13
Block 15, the programmable logic array setup module 16 and the output module 19 connect；
The input terminal of phase inverter inv16 is connect with the beat module 13, the output end AND OR NOT gate N7 of phase inverter inv16
Input terminal B connection, the input terminal A of nor gate N7 connect with the control module 11, the input terminal C AND OR NOT gate of nor gate N7
The output end of N5 connects, the input terminal A connection of the output end AND OR NOT gate N5 of nor gate N7.
Specifically, the ZDR module in the present embodiment is d type flip flop, and the input terminal of phase inverter inv4 receives frequency of oscillation mould
The second predeterminated frequency signal H55, the second predeterminated frequency signal H55 that block 12 is sent can be specifically set the signal for 55Hz, make
It is at least maintained after external key triggering to the input terminal CK's of ZDR module I 1 for the stabilization clock signal of push button signalling TRIB
There is first rising edge signal in signal, i.e. the second predeterminated frequency signal H55 first rising edge signal occurs, makes ZDR module
The output end Q of I1 exports a high level signal, by phase inverter inv6, phase inverter inv7, polar capacitor C2 and nor gate N1
Effect after, export a very short high level pulse signal, be supplied to the latch being made of nor gate N2 and nor gate N4,
Here size and polar capacitor C2 of the duration of high level pulse signal depending on phase inverter inv6 and phase inverter inv7
Size, duration are generally nanosecond or microsecond rank.
What the input terminal reception beat module 13 of phase inverter inv8 was sent finishes signal ENDB, finishes signal
ENDB is the low level pulse signal that the representative a piece of music that beat module 13 generates finishes, by phase inverter
The effect of inv8, phase inverter inv9 and polar capacitor C3 generate a very short high level pulse signal, are supplied to by nor gate
The latch of N2 and nor gate N4 composition, after latch, the output end of phase inverter inv11 generates music switching signal FS,
And music switching signal FS is sent to beat module 13.
The input terminal of phase inverter inv12 inputs push button signalling TRIB, the output end output reset signal of phase inverter inv15
RET, and reset signal is sent to frequency of oscillation module 12 and beat module 13, the output end of phase inverter inv13 exports switch
Signal EN, and switching signal EN is sent respectively to frequency of oscillation module 12, memory array setup module 15, programmable logic
Array setup module 16 and output module 19.The input terminal of phase inverter inv16 equally receives playing for the transmission of beat module 13
Finish signal ENDB.
Refering to Fig. 4, further, the control module 11 further includes key-press input unit 113, the key-press input unit
113 connect with described control unit；
The key-press input unit includes PMOS tube M2, PMOS tube M3 and NMOS tube M4, the source level and grid of PMOS tube M2
It is connect with power vd D, the drain electrode of PMOS tube M2 is connect with the drain electrode of PMOS tube M3 and the drain electrode of NMOS tube M4 respectively, PMOS tube
The source level of M3 is connect with power vd D, and the grid of PMOS tube M3 is connect with ground GND, the source level and grid of NMOS tube M4 with ground GND
Connection, push button signalling TRIB access the drain electrode of PMOS tube M2, and the push button signalling TRIB of output is connect with control unit.
Specifically, control unit receives push button signalling TRIB by key-press input unit 113, in PMOS tube M2, PMOS tube
Under the action of M3 and NMOS tube M4, when external key is failure to actuate, push button signalling TRIB is high level, when external key is pressed,
I.e. external key triggers over the ground, and push button signalling TRIB becomes low level.
Further, the frequency of oscillation module 12 includes oscillating unit and frequency unit；
The oscillating unit is connect with the frequency unit, the oscillating unit respectively with the control module 11 and described
Audio-frequency module 18 connect, the frequency unit respectively with the control module 11, the beat module 13 and the acceleration module
17 connections；
The oscillating unit outputting oscillation signal FOSCO, the oscillating unit respectively send the oscillator signal FOSCO
To the frequency unit and the audio-frequency module 18, the frequency unit sends first according to the oscillator signal FOSCO and presets
Frequency signal H1500 gives the beat module 13.
Specifically, control module 11 sends switching signal EN to oscillating unit, and it is single to frequency dividing to send reset signal RET
Member, when switching signal EN is low level, the pierce circuit in oscillating unit stops working, and can not generate and vibrate and output side
Wave signal, when switching signal EN is high level, pierce circuit generates oscillation outputting oscillation signal FOSCO, and frequency unit connects
Oscillator signal FOSCO is received, under the divider circuit effect in frequency unit, exports the first predeterminated frequency signal H1500, second
Predeterminated frequency signal H55 and third predeterminated frequency signal H165, wherein the frequency of the first predeterminated frequency signal H1500 can be specific
It is set as 1.5KHz, the frequency of third predeterminated frequency signal H165 can be specifically set as 165KHz, H1500, H165 and H55
The signal of other frequencies, the demand depending on frequency needed for integrated circuit can be used.
Refering to Fig. 5, Fig. 6 and Fig. 7, further, the beat module 13 includes the first register setting unit, first defeated
Unit and the second output unit out；
The first register setting unit is connect with first output unit, first output unit and described the
The connection of two output units, the first register setting unit are connect with the acceleration module 17, first output unit point
Not with the control module 11, the frequency of oscillation module 12, the memory array setup module 15 and the address module
14 connection, second output unit respectively with the programmable logic array setup module 16, the audio-frequency module 18 and institute
State the connection of output module 19；
The control module 11 receives externally input push button signalling TRIB, sends music according to the push button signalling TRIB
Switching signal FS and reset signal RET gives first output unit and second output unit, the frequency of oscillation mould
Block 12 sends the first predeterminated frequency signal H1500 to first output unit, and the acceleration module 17 sends the broadcasting speed
Signal TEMPO is spent to the first register setting unit, and the first register setting unit is believed according to the broadcasting speed
Number TEMPO transmission speed signal TEMPOX and cadence signal BEAT give first output unit, the first output unit root
According to the music switching signal FS, the reset signal RET, the first predeterminated frequency signal H1500, the speed signal
The TEMPOX and cadence signal BEAT sends carry driving signal RCLK to the address module 14, and sends and finish
Signal ENDB and switching identification signal RE give second output unit, and the programmable logic array setup module 16 sends sky
Position signal SB gives second output unit, and second output unit is believed according to the music switching signal FS, the reset
Number RET, described signal ENDB, the switching identification signal RE are finished and the null signals SB sends mute signal SIL
To the audio-frequency module 18 and the output module 19.
Specifically, the first register setting unit includes phase inverter inv17, phase inverter inv18, phase inverter inv19, reverse phase
Device inv20, phase inverter inv21, XOR gate N8, nor gate N9, ZSR module I 2, ZSR module I 3, ZSR module I 4 and ZSR module
I5。
The input terminal of phase inverter inv17 is connect with acceleration module 17, receives the broadcasting speed signal that acceleration module 17 is sent
TEMPO, the output end of phase inverter inv17 input terminal CKB, ZSR mould with the input terminal of phase inverter inv18, ZSR module I 2 respectively
The input terminal CKB of input terminal CKB, ZSR module I 4 of block I3 is connected with the input terminal CKB of ZSR module I 5, phase inverter inv18's
Output end output speed signal TEMPOX give the first output unit, also respectively with input terminal CK, ZSR module I 3 of ZSR module I 2
The input terminal CK of input terminal CK, ZSR module I 4 connected with the input terminal CK of ZSR module I 5, the input terminal J of ZSR module I 2,
Mould is arranged with memory array in the input terminal J of input terminal J and the ZSR module I 5 of input terminal J, ZSR module I 4 of ZSR module I 3
Block 15 connects, and successively receives divisor code D<0>, D<1>, D<2>and D<3>that memory array setup module 15 exports, ZSR mould
The output end Q of block I2 is connect with the input terminal D of ZSR module I 3, the output end Q of ZSR module I 3 input with ZSR module I 4 respectively
End D connected with the input terminal C of nor gate N9, the output end Q of ZSR module I 4 respectively with input terminal D, the XOR gate of ZSR module I 5
The input terminal B of the input terminal B and nor gate N9 of N8 are connected, the output end Q of ZSR module I 5 respectively with the input terminal A of XOR gate N8
It is connected with the input terminal A of nor gate N9, the output end of XOR gate N8 is connect with the input terminal D of ZSR module I 2, and nor gate N9's is defeated
Outlet is connect with the input terminal of phase inverter inv19, and phase inverter inv19, phase inverter inv20 and phase inverter inv21 are sequentially connected in series, instead
The phase device inv21 input terminal PSB with input terminal PSB, ZSR module I 4 of input terminal PSB, ZSR module I 3 of ZSR module I 2 respectively
It is connected with the input terminal PSB of ZSR module I 5, the output end of the output end of phase inverter inv20 exports cadence signal BEAT to first
Output unit, also respectively with the input terminal PS of input terminal PS, ZSR module I 4 of input terminal PS, ZSR module I 3 of ZSR module I 2,
The input terminal PS connection of ZSR module I 5.
First output unit includes phase inverter inv22, phase inverter inv23, phase inverter inv24, phase inverter inv25, reverse phase
Device inv26, phase inverter inv27, phase inverter inv28, phase inverter inv29, nor gate N10, nor gate N11, nor gate N12, with
NOT gate N13, NAND gate N14 and NOT gate N15, ZTR module I 6, selector module I7 and selector module I8.
The input terminal A of nor gate N10 receives divisor code D<1>, and input terminal B receives divisor code D<2>, and input terminal C connects
It receives divisor code D<3>, the output end of nor gate N10 is connect with the input terminal S of selector module I7, and selector module I7's is defeated
Enter end 0 input cadence signal BEAT, the 1 input speed signal TEMPOX of input terminal of selector module I7, selector module I7's
Output end is connect with the input terminal of phase inverter inv22, the output end of the phase inverter inv22 input terminal with phase inverter inv23 respectively
It is connected with the input terminal CKB of ZTR module I 6, the output end of phase inverter inv23 is connect with the input terminal CK of ZTR module I 6, ZTR mould
The input terminal 0 of the output end QB and selector module I8 of block I6 are connect, and the input terminal R's and phase inverter inv24 of ZTR module I 6 is defeated
Outlet connection, the output end connection of the input terminal AND OR NOT gate N11 of phase inverter inv24, the input terminal A of nor gate N11 and control
Module 11 connects, and receives reset signal RET, and the input terminal B of nor gate N11 is connect with control module 11, receives music switching letter
Number FS, the input terminal S of selector module I8 are connect with control module 11, receive music switching signal FS, selector module I8's
Input terminal 1 is connect with frequency of oscillation module 12, receive the first predeterminated frequency signal H1500, the output end of selector module I8 with
The input terminal of phase inverter inv25 connects, and phase inverter inv25 and phase inverter inv26 are sequentially connected in series, the output end of phase inverter inv26
Connect with address module 14, send carry driving signal RCLK to address module 14, the output end of phase inverter inv26 also respectively with
The input terminal A of the input terminal A and NAND gate N14 of NAND gate N13 are connected, and the input terminal B's and NAND gate N15 of NAND gate N14 is defeated
Outlet connection, the output end of NAND gate N14 are connect with the input terminal A of the input terminal B of NAND gate N13 and NAND gate N15 respectively, with
The output end of NOT gate N13 is connect with the input terminal of phase inverter inv27, the output end output switching identification signal of phase inverter inv27
The input terminal B of RE, and the input terminal E connection of AND OR NOT gate N12, NAND gate N15 receive the first predeterminated frequency signal H1500,
The input terminal of phase inverter inv28 receives divisor code D<0>, and the input terminal A of the output end AND OR NOT gate N12 of phase inverter inv28 connects
It connects, the input terminal B of nor gate N12 receives divisor code D<1>, and the input terminal C of nor gate N12 receives divisor code D<2>or non-
The input terminal D of door N12 receives divisor code D<3>, and the output end of nor gate N12 is connect with the input terminal of phase inverter inv29, instead
The output end output of phase device inv29 finishes signal ENDB.
Second output unit includes phase inverter inv30, phase inverter inv31, phase inverter inv32 and nor gate N16.
The input terminal A of nor gate N16 receives reset signal RET, and the input terminal B of nor gate N16 receives music switching signal
The input terminal C of FS, nor gate N16 receive switching identification signal RE, the output of the input terminal D and phase inverter inv30 of nor gate N16
The input terminal reception of end connection, phase inverter inv30 finishes signal ENDB, the input terminal E and phase inverter of nor gate N16
The output end of inv31 connects, and the input terminal of phase inverter inv31 receives the vacancy letter that programmable logic array setup module 16 is sent
Number SB, the output end of nor gate N16 are connect with the input terminal of phase inverter inv32, the output end output mute letter of phase inverter inv32
Number SIL.
Beat module 13 is provided with 4 ZSR modules, ZSR module is using the design method of linear feedback shift register
D type flip flop with dual input determines d type flip flop by input terminal PS received signal and input terminal PSB received signal
Input terminal be input terminal D or input terminal J, 4 ZSR modules receive divisor code D<0>~D<3>, and maximum divisor is 24- 1=
15, i.e., maximum frequency dividing multiple is 15, can determine 15 kinds of beats.ZTR module in first output unit is T trigger.Speed
The broadcasting speed signal TEMPO that module 17 generates is sent to beat module 13 and inputs, and when wherein divisor is 1, this can be set
When D<0>=1, D<1>D<2>D<3>be 000, by directly exporting broadcasting speed signal TEMPO, i.e. carry driving signal RCLK
Identical as broadcasting speed signal TEMPO frequency, default is without being divided.
The corresponding beat of one note, so the carry driving signal RCLK that beat module 13 generates, acts on address
Module 14 makes it generate carry, that is, carries out the switching of note.
When music switching signal FS is 1, beat module 13 exports the first predeterminated frequency signal H1500, i.e. carry drives
Signal RCLK is identical as the frequency of the first predeterminated frequency signal H1500, because the frequency of the first predeterminated frequency signal H1500 is
1500Hz, even if continuously playing 50 periods, i.e. 50 notes, also just 33.3ms, people were hardly noticeable that obtain, be reached with this total time
To the purpose for quickly playing the music currently played, the function of being switched fast music is realized in other words.To be switched
After music quickly finishes, music switching signal FS becomes 0, starts with the subsequent music of normal speed forward.
When D<0>=1, D<1>D<2>D<3>be 000, with switching identification signal RE combination producing finish signal ENDB,
Finishing signal ENDB is low level signal, and its period is the half in the first predeterminated frequency signal H1500 period.
When music switching signal FS is 1, the carry driving signal RCLK of beat module output is equal to the first default frequency
Rate signal H1500；When music switching signal FS is 0, switching identification signal RE is also 0.The of this music control switching circuit
One note will be left white, i.e. the corresponding D of first note<1>~D<7>, O1~O7 and null signals SB is 0, and second
It is 000 that note, which corresponds to D<0>=1, D<1>D<2>D<3>,.After pressing external key for the first time, the 0th is quickly played very much
First melody (first note: a blank character is placeholder and second note: end mark), then normal play is real again
The 1st first melody on border.Mute signal SIL signal is represented in following situations, and it is mute for exporting: it is (empty to play first note
Position signal SB signal is effective), when quickly playing (music switching signal FS is effective), after finishing playing (reset signal RET is effective),
Note duration (reverse signal for finishing signal ENDB is effective) when per song finishes,
When being clapped with " removing 4 " for 1: ÷ 1 → 1/4 is clapped, and ÷ 2 → 1/2 is clapped, and ÷ 3 → 3/4 is clapped, and the bat of ÷ 4 → 1, ÷ 6 → 3/2 is clapped,
÷ 8 → 2 is clapped, and ÷ 12 → 3 is clapped etc., and bat is shorter, and divisor is bigger, indicates that frequency is higher, also smaller except being worth.
Refering to Fig. 8, further, the acceleration module 17 includes the second register setting unit；
The second register setting unit respectively with the frequency of oscillation module 12, the memory array setup module
15 and the beat module 13 connection；
The second register setting unit exports the broadcasting speed signal TEMPO according to the divisor code.
Specifically, acceleration module 17 is provided with 4 ZSR modules, is connect using the design method of linear feedback shift register
Divisor code D<4>~D<7>is received, maximum divisor is 24- 1=15, i.e., maximum frequency dividing multiple is 15, can determine 15 kinds of broadcasting speed
Degree, meets different actual demands.Second register setting unit includes phase inverter inv33, phase inverter inv34, phase inverter
Inv35, phase inverter inv36, phase inverter inv37, nor gate N17, XOR gate N18, ZSR module I 9, ZSR module I 10, ZSR mould
Block I11 and ZSR module I 12；
The input terminal of phase inverter inv33 is connect with the frequency of oscillation module 12, the output end of phase inverter inv33 respectively with
The input terminal of phase inverter inv34, input terminal CKB, ZSR module I 11 of input terminal CKB, ZSR module I 10 of ZSR module I 9 it is defeated
Enter to hold the input terminal CKB of CKB with ZSR module I 12 to connect, the output end of the phase inverter inv34 input terminal with ZSR module I 9 respectively
The input terminal CK of input terminal CK, ZSR module I 11 of CK, ZSR module I 10 is connected with the input terminal CK of ZSR module I 12, ZSR mould
The input terminal J of input terminal J and the ZSR module I 12 of input terminal J, ZSR module I 11 of input terminal J, ZSR module I 10 of block I9 is equal
It is connect with the memory array setup module 15, successively receives divisor code D < 4 that memory array setup module 15 exports
>, D<5>, D<6>and D<7>, the output end Q of ZSR module I 9 connect with the input terminal D of ZSR module I 10, ZSR module I 10 it is defeated
Outlet Q is connect with the input terminal C of the input terminal D of ZSR module I 11 and nor gate N17 respectively, and output end Q points of ZSR module I 11
It is not connect with the input terminal B of the input terminal D of ZSR module I 12, the input terminal B of XOR gate N18 and nor gate N17, ZSR module I 12
Output end Q connect respectively with the input terminal A of the input terminal A of XOR gate N18 and nor gate N17, the output end of XOR gate N18 with
The input terminal D connection of ZSR module I 9, the output end of nor gate N17 are connect with the input terminal of phase inverter inv35, phase inverter
Inv35, phase inverter inv36 and phase inverter inv37 are sequentially connected in series, and the output end of phase inverter inv37 is defeated with ZSR module I 9 respectively
Enter to hold the input terminal PSB of input terminal PSB and the ZSR module I 12 of input terminal PSB, ZSR module I 11 of PSB, ZSR module I 10 to connect
It connects, the output end of phase inverter inv36 input terminal PS, ZSR module with input terminal PS, ZSR module I 10 of ZSR module I 9 respectively
The input terminal PS of I11 is connected with the input terminal PS of ZSR module I 12, and is exported broadcasting speed signal TEMPO and be sent to beat module
13。
Further, the audio-frequency module 18 includes third register setting unit and third output unit；
The third register setting unit is connect with the third output unit, the third register setting unit point
It is not connect with the frequency of oscillation module 12 and the programmable logic array setup module 16, the third output unit difference
It is connect with the beat module 13 and the output module 19；
The programmable logic array module 16 sends audio coding signal 01~07 to described according to the divisor code
Third register setting unit, the 12 outputting oscillation signal FOSCO of frequency of oscillation module are simultaneously sent to the third register
Setting unit, the third register setting unit is according to the audio coding signal 01~07 and the oscillator signal FOSCO
Fractional frequency signal is sent to the third output unit, the 13 output mute signal SIL of beat module is simultaneously sent to the third
Output unit, the third output unit export the audio of predeterminated frequency according to the fractional frequency signal and the mute signal SIL
Signal TONE.
Specifically, audio-frequency module 18 equally uses the design method of linear feedback shift register, main to realize that frequency dividing is made
With third register setting unit is exported according to the audio coding signal 01~07 that programmable logic array setup module 16 is sent
Fractional frequency signal determines frequency dividing multiple, the mute signal SIL sent in conjunction with beat module 13, so that it may frequency needed for exporting
Audio signal TONE.
Refering to Fig. 9, further, the output module 19 includes phase inverter inv38, phase inverter inv39, phase inverter
Inv40, phase inverter inv41, phase inverter inv42, phase inverter inv43, phase inverter inv44, phase inverter inv45, NAND gate N19,
NAND gate N20 and NAND gate N21；
The input terminal of phase inverter inv38 is connect with the beat module 13, the output end and NAND gate of phase inverter inv38
The input terminal A connection of N19, the input terminal B of NAND gate N19 are connect with the audio-frequency module 18, the output end difference of NAND gate N19
It is connect with the input terminal of the input terminal B of NAND gate N20 and phase inverter inv39, the input terminal A of NAND gate N20 and the control mould
Block 11 connects, and the output end of NAND gate N20 connect with the input terminal of phase inverter inv40, phase inverter inv40, phase inverter inv41 and
Phase inverter inv42 is sequentially connected in series, and the output end of phase inverter inv42 is connect with the external audible device 20, phase inverter inv39's
Output end is connect with the input terminal A of NAND gate N21, and the output end B of NAND gate N21 is connect with the control module 11, NAND gate
The output end of N21 is connect with the input terminal of phase inverter inv43, and phase inverter inv43, phase inverter inv44 and phase inverter inv45 are successively
Series connection, the output end of phase inverter inv45 are connect with the external audible device 20.
Specifically, the input terminal of phase inverter inv38 receives the mute signal SIL that beat module 13 is sent, NAND gate N19's
Input terminal B receives the audio signal TONE that audio-frequency module 18 is sent, the input terminal of the input terminal A and NAND gate N21 of NAND gate N20
B receives the switching signal EN of the transmission of control module 11, and when switching signal EN is low level, output module is not exported, switch
When signal EN is high level, mute signal SIL executes NAND Logic by phase inverter inv38 and audio signal TONE, intercepts out
Non-mute area, the port of two opposite in phase of final output to BD and BDB drive external piezo to make a sound, or driving
Other external audible devices carry out sounding.
The utility model embodiment also provides a kind of music switching device, and music switching device includes in above-described embodiment
Music control switching circuit, in music control switching circuit the specific structure of modules and function referring to above-described embodiment, by
All technical solutions of above-described embodiment are used in the music switching device, therefore at least with the technology of above-described embodiment
All beneficial effects brought by scheme.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of described device is divided into different functional unit or module, more than completing
The all or part of function of description.Each functional unit in embodiment, module can integrate in one processing unit, can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units, it is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.In addition, each function list
Member, the specific name of module are also only for convenience of distinguishing each other, the protection scope being not intended to limit this application.Above system
The specific work process of middle unit, module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the utility model.
In embodiment provided by the utility model, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, system embodiment described above is only schematical, for example, the module or unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling or direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
Conjunction or communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the utility model can integrate in one processing unit,
It can be each unit to physically exist alone, can also be integrated in one unit with two or more units.It is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.
Embodiment described above is only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to before
Embodiment is stated the utility model is described in detail, those skilled in the art should understand that: it still can be with
It modifies the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit for various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
And range, it should be included within the scope of protection of this utility model.
Claims (10)
1. a kind of music control switching circuit, which is characterized in that including control module, frequency of oscillation module, beat module, address
Module, memory array setup module, programmable logic array setup module, acceleration module, audio-frequency module and output module；
The control module receives externally input push button signalling, the control module respectively with the frequency of oscillation module, institute
State beat module, the address module, the memory array setup module, the programmable logic array setup module and institute
State output module connection, the frequency of oscillation module respectively with the audio-frequency module, the acceleration module and the beat module
Connection, the beat module respectively with the acceleration module, the memory array setup module, the programmable logic array
Setup module, the address module, the audio-frequency module are connected with the output module, the address module and the memory
The connection of array setup module, the memory array setup module respectively with the programmable logic array setup module and described
Acceleration module connection, the programmable logic array setup module connect with the audio-frequency module, the audio-frequency module with it is described
Output module connection, the output module are connect with external audible device.
2. music control switching circuit according to claim 1, which is characterized in that the control module includes electrification reset
Unit and control unit；
Described control unit receives externally input push button signalling, and the power on reset unit is connect with described control unit, institute
State control unit respectively with the frequency of oscillation module, the beat module, the memory array setup module, described compile
Journey logic array setup module is connected with the output module, and the power on reset unit is connect with the address module.
3. music control switching circuit according to claim 2, which is characterized in that the power on reset unit includes reverse phase
Device inv1, phase inverter inv2, phase inverter inv3, PMOS tube M1 and polar capacitor C1；
The source level of PMOS tube M1 is connect with power vd D, and the grid of PMOS tube M1 is connect with ground GND, the drain electrode difference of PMOS tube M1
It is connect with the input terminal of the anode of polar capacitor C1 and phase inverter inv1, the cathode of polar capacitor C1 is connect with ground GND, phase inverter
Inv1, phase inverter inv2 and phase inverter inv3 are sequentially connected in series, the output end of phase inverter inv3 respectively with described control unit and institute
State address module connection.
4. music control switching circuit according to claim 2, which is characterized in that described control unit includes phase inverter
Inv4, phase inverter inv5, phase inverter inv6, phase inverter inv7, phase inverter inv8, phase inverter inv9, phase inverter inv10, reverse phase
Device inv11, phase inverter inv12, phase inverter inv13, phase inverter inv14, phase inverter inv15, phase inverter inv16, nor gate N1,
Nor gate N2, nor gate N3, nor gate N4, nor gate N5, nor gate N6, nor gate N7, polar capacitor C2, polar capacitor C3 and
ZDR module I 1；
The input terminal of phase inverter inv4 is connect with the frequency of oscillation module, and phase inverter inv4 is sequentially connected in series with phase inverter inv5,
The output end of phase inverter inv5 is connect with the input terminal CK of ZDR module I 1, the input terminal CKB and phase inverter inv5 of ZDR module I 1
Input terminal connection, the input terminal D of ZDR module I 1 connect with the output end of phase inverter inv12, the output end Q of ZDR module I 1 and
The input terminal of phase inverter inv6 connects, and phase inverter inv6 is sequentially connected in series with phase inverter inv7, the output end difference of phase inverter inv7
The cathode of the anode connection of the input terminal B and polar capacitor C2 of AND OR NOT gate N1, polar capacitor C2 is connect with ground GND, nor gate
The input terminal A of N1 is connect with the input terminal of phase inverter inv7, the input terminal A connection of the output end AND OR NOT gate N2 of nor gate N1,
The output end of the input terminal B AND OR NOT gate N4 of nor gate N2 connects, and the input terminal A of the output end AND OR NOT gate N4 of nor gate N2 connects
It connects；
The input terminal of phase inverter inv8 is connect with the beat module, and phase inverter inv8 is sequentially connected in series with phase inverter inv9, reverse phase
The anode connection of the input terminal B and polar capacitor C3 of the output end difference AND OR NOT gate N3 of device inv9, the cathode of polar capacitor C3
It is connect with ground GND, the input terminal A of nor gate N3 is connect with the input terminal of phase inverter inv9, the output end and-or inverter of nor gate N3
The input terminal B connection of door N4, the input terminal C of nor gate N4 connect with the power on reset unit, the output end of nor gate N4 and
The input terminal of phase inverter inv10 connects, and phase inverter inv10 and phase inverter inv11 are sequentially connected in series, the output end of phase inverter inv11
It is connect with the beat module；
The input terminal of phase inverter inv12 inputs the push button signalling, the input terminal of the output end AND OR NOT gate N5 of phase inverter inv12
B connection, the output end connection of the input terminal A AND OR NOT gate N7 of nor gate N5, the input terminal C and phase inverter inv11 of nor gate N5
Output end connection, the output end of nor gate N5 passes sequentially through concatenated phase inverter inv13 and phase inverter inv14 AND OR NOT gate N6
Input terminal B connection, the input terminal A of nor gate N6 connect with the control module, the output end and phase inverter of nor gate N6
The input terminal of inv15 connects, and the output end of phase inverter inv15 connects with the frequency of oscillation module and the beat module respectively
Connect, the output end of phase inverter inv13 respectively with the frequency of oscillation module, the memory array setup module, described compile
Journey logic array setup module is connected with the output module；
The input terminal of phase inverter inv16 is connect with the beat module, the input of the output end AND OR NOT gate N7 of phase inverter inv16
B connection is held, the input terminal A of nor gate N7 is connect with the control module, the output of the input terminal C AND OR NOT gate N5 of nor gate N7
End connection, the input terminal A connection of the output end AND OR NOT gate N5 of nor gate N7.
5. music control switching circuit according to claim 1, which is characterized in that the frequency of oscillation module includes oscillation
Unit and frequency unit；
The oscillating unit is connect with the frequency unit, the oscillating unit respectively with the control module and the audio mould
Block connection, the frequency unit are connect with the control module, the beat module and the acceleration module respectively.
6. music control switching circuit according to claim 1, which is characterized in that the beat module includes the first deposit
Device setting unit, the first output unit and the second output unit；
The first register setting unit is connect with first output unit, first output unit and described second defeated
Unit connects out, and the first register setting unit connect with the acceleration module, first output unit respectively with institute
It states control module, the frequency of oscillation module, the memory array setup module to connect with the address module, described second
Output unit is connect with the programmable logic array setup module, the audio-frequency module and the output module respectively.
7. music control switching circuit according to claim 1, which is characterized in that the acceleration module includes the second deposit
Device setting unit；
The second register setting unit respectively with the frequency of oscillation module, the memory array setup module and described
The connection of beat module.
8. music control switching circuit according to claim 1, which is characterized in that the audio-frequency module includes third deposit
Device setting unit and third output unit；
The third register setting unit is connect with the third output unit, the third register setting unit respectively with
The frequency of oscillation module is connected with the programmable logic array setup module, the third output unit respectively with the section
Module is clapped to connect with the output module.
9. music control switching circuit according to claim 1, which is characterized in that the output module includes phase inverter
Inv38, phase inverter inv39, phase inverter inv40, phase inverter inv41, phase inverter inv42, phase inverter inv43, phase inverter
Inv44, phase inverter inv45, NAND gate N19, NAND gate N20 and NAND gate N21；
The input terminal of phase inverter inv38 is connect with the beat module, and the output end of phase inverter inv38 is defeated with NAND gate N19's
Enter A is held to connect, the input terminal B of NAND gate N19 is connect with the audio-frequency module 18, the output end of NAND gate N19 respectively with it is non-
The input terminal B of door N20 is connected with the input terminal of phase inverter inv39, and the input terminal A of NAND gate N20 is connect with the control module,
The output end of NAND gate N20 is connect with the input terminal of phase inverter inv40, phase inverter inv40, phase inverter inv41 and phase inverter
Inv42 is sequentially connected in series, and the output end of phase inverter inv42 connect with the external audible device, the output end of phase inverter inv39 and
The input terminal A connection of NAND gate N21, the output end B of NAND gate N21 are connect with the control module, the output end of NAND gate N21
It is connect with the input terminal of phase inverter inv43, phase inverter inv43, phase inverter inv44 and phase inverter inv45 are sequentially connected in series, phase inverter
The output end of inv45 is connect with the external audible device.
10. a kind of music switching device, which is characterized in that including music switching control described in claim 1 to 9 any one
Circuit.
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| CN201820993077.7U CN208386513U (en) | 2018-06-26 | 2018-06-26 | Music control switching circuit and device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108649948A (en) * | 2018-06-26 | 2018-10-12 | 宗仁科技(平潭)有限公司 | Music control switching circuit and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108649948A (en) * | 2018-06-26 | 2018-10-12 | 宗仁科技(平潭)有限公司 | Music control switching circuit and device |
| CN108649948B (en) * | 2018-06-26 | 2024-05-24 | 宗仁科技(平潭)股份有限公司 | Music switching control circuit and device |
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Address after: 350400 area B, 6th floor, building 17, Taiwan Pioneer Park, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee after: Zongren Technology (Pingtan) Co.,Ltd. Address before: 350400 area B, 6th floor, building 17, Taiwan Pioneer Park, beicuo Town, Pingtan County, Fuzhou City, Fujian Province Patentee before: ZONGREN TECHNOLOGY (PINGTAN) Co.,Ltd. |
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