CN1808624B - Shift cache unit and associated signal drive circuit and display system - Google Patents
Shift cache unit and associated signal drive circuit and display system Download PDFInfo
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- CN1808624B CN1808624B CN 200510001870 CN200510001870A CN1808624B CN 1808624 B CN1808624 B CN 1808624B CN 200510001870 CN200510001870 CN 200510001870 CN 200510001870 A CN200510001870 A CN 200510001870A CN 1808624 B CN1808624 B CN 1808624B
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Abstract
The disclosed shift buffer unit to generate two output pulses by turns comprises: a first unit with a first/second input end coupled to an initial pulse and a sequence signal respectively to output a first output pulse in the first period; and a second unit with a first/second input end coupled to said first output pulse and the reverse-phase signal of said sequence signal respectively to output a second output pulse in the second period.
Description
Technical field
The present invention is relevant for a kind of shift cache unit, especially about a kind of shift cache unit that can produce two output pulses in order.
Background technology
Figure 1 shows that a traditional shift cache unit 10.The tradition shift scratch circuit can contain a plurality of shift cache units 10, produces pulse signal in order, to drive display panels.Figure 2 shows that the sequential chart of the input signal (STB, CLK and CLK) of offset buffer shown in Figure 1.Yet in offset buffer 10, the work period of time sequential pulse CLK and CLK (duty cycle) TC must fully drop among the work period TS of input pulse STB.Moreover because the control of time sequential pulse CLK and CLK, clock pulse phase inverter (clock inver ter) CINV4 and CINV5 can switch apace, thereby consume electric energy in large quantities.In addition, traditional shift cache unit is because the number of its required component is more, so chip area that will be bigger.
Summary of the invention
In view of this, primary and foremost purpose of the present invention is the electric energy loss that is to reduce shift cache unit.
Another object of the present invention is to be to reduce the required package count of shift cache unit, uses and reduces required chip area.
Another purpose of the present invention is to be to provide a kind of shift cache unit that can produce two output pulses in order.According to above-mentioned purpose, the present invention provides a kind of shift cache unit, comprising: a first module, couple an initial pulse and a clock signal, and when being used to a period 1, export one first output pulse; And Unit one second, be coupled to an inversion signal of above-mentioned first output frequency and above-mentioned clock signal, when being used to above-mentioned second round, export one second output frequency, above-mentioned first module comprises: one the one NOR lock has a first input end and couples above-mentioned initial pulse; One first phase inverter has the output terminal that an input end couples an above-mentioned NOR lock; One first frequency phase inverter, have one first control end and be coupled to one first output terminal of an above-mentioned NOR lock, the output terminal that one second control end is coupled to above-mentioned first phase inverter, and one input end be coupled to above-mentioned clock signal, when being used for above-mentioned period 1, above-mentioned clock signal is anti-phase, to export one first signal; One second phase inverter, have an input end and be coupled to an output terminal of above-mentioned first frequency phase inverter, and an output terminal is coupled to one second output terminal of an above-mentioned NOR lock, when being used to above-mentioned period 1, with above-mentioned first signal inversion, to export pulse as above-mentioned first; An and second frequency phase inverter, have one the 3rd control end and be coupled to the above-mentioned output terminal of an above-mentioned NOR lock, the above-mentioned output terminal that one the 4th control end is coupled to above-mentioned first phase inverter, one input end is coupled to the above-mentioned output terminal of above-mentioned second phase inverter, when being used to above-mentioned second round, with the above-mentioned first output pulse inversion, to export a secondary signal, make that above-mentioned second phase inverter is anti-phase with above-mentioned secondary signal, to export pulse as above-mentioned first to above-mentioned second phase inverter; Above-mentioned Unit second more comprises:
One the 2nd NOR lock has the output terminal that one the 3rd input end couples above-mentioned second phase inverter; One the 4th phase inverter has the output terminal that an input end couples above-mentioned the 2nd NOR lock; One the 3rd frequency phase inverter, have one the 5th control end and be coupled to an output terminal of above-mentioned the 4th phase inverter, one the 3rd output terminal that one the 6th control end is coupled to above-mentioned the 2nd NOR lock, the output terminal that an input end is coupled to above-mentioned the 3rd phase inverter, when being used to above-mentioned second round, the above-mentioned inversion signal of above-mentioned clock signal is anti-phase, to export one the 3rd signal; And one the 5th phase inverter, have an input end and couple an output terminal of above-mentioned the 3rd frequency phase inverter, and an output terminal is coupled to a four-input terminal of above-mentioned the 2nd NOR lock, when being used to above-mentioned second round, with above-mentioned the 3rd signal inversion, as above-mentioned second output frequency.
According to above-mentioned purpose, the present invention also provides another offset buffer, and wherein a first module is when a period 1, according to an initial pulse and a clock signal, by one first phase inverter, exports one first output pulse; And one second the unit be when a second round, according to the inversion signal of above-mentioned first output pulse and above-mentioned clock signal,, export one second output pulse by one second phase inverter.
Description of drawings
Fig. 1 is expression one traditional offset buffer.
Fig. 2 is the operation signal sequential chart of traditional offset buffer among Fig. 1.
Fig. 3 is the synoptic diagram of offset buffer of the present invention.
Fig. 4 is another synoptic diagram of offset buffer of the present invention.
Fig. 5 is the operation signal sequential chart of offset buffer of the present invention.
Fig. 6 is the synoptic diagram of signal drive circuit of the present invention.
Fig. 7 is the operation signal sequential chart of signal drive circuit of the present invention.
Fig. 8 is the synoptic diagram of display system of the present invention.
Symbol description:
10: shift cache unit;
STB, CLK, CLK: pulse;
CINV4, CINV5: clock pulse phase inverter;
TS, TC: work period.
400: display system;
410: display module;
300: signal drive circuit;
200, SR1～SRN: shift cache unit;
10: first module;
20: the second unit;
INV1～INV5: phase inverter;
CINV1～CINV3: clock pulse phase inverter;
CLK: clock signal;
STB: initial pulse;
CLK: the inversion signal of clock signal;
NOR1, NOR2:NOR lock;
CP1～CP3: first control end;
CN1～CN2: second control end;
ND1～ND2: node;
Q1～Q4, Q2N-1, Q2N: output pulse;
VDD: first voltage;
VSS: second voltage;
P1～P6, N1～N6: transistor;
TS, TC: work period;
T1: period 1;
T2: second round.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
Figure 3 shows that the synoptic diagram of shift cache unit of the present invention.As shown in the figure, shift cache unit 200 comprises a first module 10 and one second unit 20.First module 10 is in order to receive an initial pulse STB and a clock signal CLK, when being used to a period 1, export one first output pulse Q1, second unit 20 is in order to receive the inversion signal CLK of the first output pulse Q1 and clock signal CLK, when being used to a second round, export one second output pulse Q2.
As shown in Figure 3, first module 10 is to comprise a NOR lock NOR1, two clock pulse phase inverter CINV1 and CINV2, three phase inverter INV1, INV2 and INV3.
NOR lock NOR1 comprises that a first input end couples the output terminal that initial pulse STB and one second input end couple phase inverter INV2.Clock pulse phase inverter CINV1 comprises that an input end couples clock signal CLK, one first control end CP1 and couples the output terminal of NOR lock NOR1, the output terminal that one second control end CN1 couples phase inverter INV1, and an output terminal is coupled to a node ND1.Phase inverter INV1 has an input end to couple the output terminal of NOR lock NOR1, the first control end CP1 of clock pulse phase inverter CINV1 and the second control end CN2 of clock pulse phase inverter CINV2, and an output terminal couples the second control end CN1 of clock pulse phase inverter CINV1 and the first control end CP2 of clock pulse phase inverter CINV2.
Clock pulse phase inverter CINV2 comprises that an input end couples the output terminal of phase inverter INV2, and one first control end CP2 couples the output terminal of phase inverter INV1, and one second control end CN2 couples the output terminal of NOR lock NOR1, and an output terminal couples node ND1.Phase inverter INV2 has that input end couples node ND1, output terminal couples the input end of clock pulse phase inverter CINV2 and second input end of NOR lock NOR1.Phase inverter INV3 has an input end, in order to reception clock signal CLK, and the inversion signal CLK of output timing signal CLK.
Second unit 20 is to comprise NOR lock NOR2, clock pulse phase inverter CINV3, and two phase inverter INV4 and INV5.NOR lock NOR2 has a first input end and couples second input end of NOR lock NOR1 and the output terminal of phase inverter INV2, one second input end couples the output terminal of phase inverter INV5, and an output terminal couples the input end of phase inverter INV4 and the first control end CP3 of clock pulse phase inverter CINV3.Clock pulse phase inverter CINV3 comprises that an input end couples the inversion signal CLK of clock signal CLK, one first control end CP3 couples the output terminal of NOR lock NOR2 and the input end of phase inverter INV4, one second control end CN3 couples the output terminal of phase inverter INV4, and an output terminal couples phase inverter INV5.Phase inverter INV5 has the output terminal that an input end couples clock pulse phase inverter CINV3, and an output terminal couples second input end of NOR lock NOR2.
Fig. 4 is another synoptic diagram of offset buffer 200 of the present invention.As shown in the figure, clock pulse phase inverter CINV1 comprises two PMOS transistor P1 and P2, and bi-NMOS transistor N1 and N2, clock pulse phase inverter CINV2 comprises two PMOS transistor P3 and P4, and bi-NMOS transistor N3 and N4, and clock pulse phase inverter CINV3 comprises two PMOS transistor P5 and P6, and bi-NMOS transistor N5 and N6.In clock pulse phase inverter CINV1, PMOS transistor P1 comprises that one first end couples one first voltage VDD, and a control end couples the output terminal of NOR lock NOR1 and the input end of phase inverter INV1, and one second end.PMOS transistor P2 comprises that one first end couples second end of PMOS transistor P1, and a control end couples clock signal CLK, and one second end couples node ND1.Nmos pass transistor N1 comprises that one first end couples node ND1, and a control end couples the control end of PMOS transistor P2, and one second end.Nmos pass transistor N2 comprises that one first end couples second end of nmos pass transistor N1, and a control end couples the output terminal of phase inverter INV1, and one second end couples one second voltage VSS.
In clock pulse phase inverter CINV2, PMOS transistor P3 comprises that one first end couples the first voltage VDD, and a control end couples the output terminal of phase inverter INV1, and one second end.PMOS transistor P4 comprises that one first end couples second end of PMOS transistor P3, and a control end couples the output terminal of phase inverter INV2, and one second end couples node ND1.Nmos pass transistor N3 comprises that one first end couples node ND1, the control end of a control end PMOS transistor P4, and one second end.Nmos pass transistor N4 comprises that one first end couples second end of nmos pass transistor N3, and a control end couples the output terminal of NOR lock NOR1, and one second end couples the second voltage VSS.
Moreover in clock pulse phase inverter CINV3, PMOS transistor P5 comprises that one first end couples the first voltage VDD, and a control end couples the output terminal of NOR lock NOR2 and the input end of phase inverter INV4, and one second end.PMOS transistor P6 comprises that one first end couples second end of PMOS transistor P5, and a control end couples the inversion signal CLK of clock signal CLK, and one second end couples the input end of phase inverter INV5.Nmos pass transistor N5 comprises that one first end couples the input end of phase inverter INV5, and a control end couples the control end of PMOS transistor P6, and one second end.Nmos pass transistor N6 comprises that one first end couples second end of nmos pass transistor N5, and a control end couples the output terminal of phase inverter INV4, and one second end couples the second voltage VSS.
Fig. 5 is the operation signal sequential chart of offset buffer 200 of the present invention.Please refer to Fig. 4 and Fig. 5, in order to describe the running of offset buffer 200.
When initial, because the output pulse Q1 and the initial pulse STB of first module 10 are all logical zero, so transistor P1, P5, N2 and N6 end and transistor P3, N4 conducting.So clock pulse phase inverter CINV1 can close, clock pulse phase inverter CINV2 can firmly be the output pulse Q1 of logical zero with phase inverter INV2 bolt-lock, and clock pulse phase inverter CINV3 can close, and makes output pulse Q2 maintain logical zero.
When time ts, initial pulse STB can input to the first input end of NOR lock NOR1, makes transistor P1 and N2 conducting, and transistor P3 and N4 end.So clock pulse phase inverter CINV1 can open, and clock pulse phase inverter CINV2 can close.
When period 1 T1, the clock signal CLK of high levle (for example logical one) can input to clock pulse phase inverter CINV1, and converts first signal of a logical zero to, exports phase inverter INV2 to.So phase inverter INV2 exports the output pulse Q1 of a logical one.This moment, because the inversion signal CLK of clock signal CLK, clock pulse phase inverter CINV3 also can open, and the output terminal of phase inverter INV5 is to maintain logical zero.
Second round during T2, clock signal CLK becomes logical zero, and the inversion signal CLK of clock signal CLK becomes logical one, and at this moment, the output terminal of phase inverter INV2 can become logical zero, and clock pulse phase inverter CINV1 can close.Therefore, output pulse Q1 can maintain logical zero, up to the next period 1.In addition, the inversion signal CLK of logical one can input to clock pulse phase inverter CINV3, converts the secondary signal of a logical zero to, exports phase inverter INV5 to.Phase inverter thereby export the output pulse Q2 of a logical one.Moreover when inversion signal CLK became logical zero once again, clock pulse phase inverter CINV3 also can close, and made output pulse Q2 maintain logical zero, up to next second round.
As shown in Figure 5, the work period TC of clock signal CLK need be fully in the work period of initial pulse TS, and therefore shift cache unit of the present invention has preferable fault-tolerance (tolerance).In addition, shift cache unit as shown in Figure 1 needs two clock pulse phase inverters, three phase inverters, two transmission locks, two MOS transistor, a NOR lock and NAND locks, go to produce an output pulse, to drive a display module, yet shift cache unit of the present invention only needs three clock pulse phase inverters, five phase inverters and two NOR locks, promptly can produce two output clock pulses in regular turn, therefore offset buffer of the present invention will need less transistor component and chip area.
Fig. 6 is the synoptic diagram of signal drive circuit of the present invention.As shown in the figure, signal drive circuit 300 comprises a plurality of shift cache unit SR1～SRN that are connected in series, and each offset buffer is identical with Fig. 3 or that shown in Figure 4.Offset buffer SR1～the SRN that is connected in series is output signal Q1, Q2, Q3...Q2N-1 and Q2N in order, and in the offset buffer of present this one-level, the initial pulse of first module is the output of second in previous stage offset buffer pulse.This one-level offset buffer can be exported first, second output pulse in regular turn after a given time postpones at present, and the second output pulse is to input in the shift cache unit of next stage.Therefore, signal drive circuit can produce a plurality of output pulses, and in order to drive liquid crystal display, wherein Fig. 7 is the signal timing diagram of signal drive circuit 300.
As shown in Figure 8, in display system 400, display module 410, a LCD assembly for example, be action property be coupled to aforesaid signal drive circuit 300.Signal drive circuit 300 is to export a plurality of output pulses in order, to drive display module 410.In the present invention, display unit 410 also can be a plasma display module, an organic light emitting display assembly or a cathode-ray tube display assembly.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (5)
1. shift cache unit comprises:
One first module couples an initial pulse and a clock signal, when being used to a period 1, exports one first output pulse; And
Unit one second is coupled to an inversion signal of above-mentioned first output pulse and above-mentioned clock signal, when being used to a second round, exports one second output pulse,
Above-mentioned first module comprises:
One the one NOR lock has a first input end and couples above-mentioned initial pulse;
One first phase inverter has the output terminal that an input end couples an above-mentioned NOR lock;
One first frequency phase inverter, have one first control end and be coupled to one first output terminal of an above-mentioned NOR lock, the output terminal that one second control end is coupled to above-mentioned first phase inverter, and one input end be coupled to above-mentioned clock signal, when being used for above-mentioned period 1, above-mentioned clock signal is anti-phase, to export one first signal;
One second phase inverter, have an input end and be coupled to an output terminal of above-mentioned first frequency phase inverter, and an output terminal is coupled to one second output terminal of an above-mentioned NOR lock, when being used to above-mentioned period 1, with above-mentioned first signal inversion, to export pulse as above-mentioned first; And
One second frequency phase inverter, have one the 3rd control end and be coupled to the above-mentioned output terminal of an above-mentioned NOR lock, the above-mentioned output terminal that one the 4th control end is coupled to above-mentioned first phase inverter, one input end is coupled to the above-mentioned output terminal of above-mentioned second phase inverter, when being used to above-mentioned second round, with the above-mentioned first output pulse inversion, to export a secondary signal, make that above-mentioned second phase inverter is anti-phase with above-mentioned secondary signal, to export pulse as above-mentioned first to above-mentioned second phase inverter;
Above-mentioned Unit second more comprises:
One the 2nd NOR lock has the output terminal that one the 3rd input end couples above-mentioned second phase inverter;
One the 4th phase inverter has the output terminal that an input end couples above-mentioned the 2nd NOR lock;
One the 3rd frequency phase inverter, have one the 5th control end and be coupled to an output terminal of above-mentioned the 4th phase inverter, one the 3rd output terminal that one the 6th control end is coupled to above-mentioned the 2nd NOR lock, the output terminal that an input end is coupled to above-mentioned the 3rd phase inverter, when being used to above-mentioned second round, the above-mentioned inversion signal of above-mentioned clock signal is anti-phase, to export one the 3rd signal; And
One the 5th phase inverter, have an input end and couple an output terminal of above-mentioned the 3rd frequency phase inverter, and an output terminal is coupled to a four-input terminal of above-mentioned the 2nd NOR lock, when being used to above-mentioned second round, with above-mentioned the 3rd signal inversion, as the above-mentioned second output pulse.
2. shift cache unit according to claim 1, wherein above-mentioned first module comprises:
One the 3rd phase inverter comprises that an input end is coupled to above-mentioned clock signal, and in order to above-mentioned sequential is anti-phase, one produces an inversion signal of above-mentioned clock signal.
3. a signal drive circuit comprises:
N shift cache unit according to claim 2, be connected in series, in order to produce 2N output pulse in order, the above-mentioned second output pulse of M shift cache unit in wherein above-mentioned N the shift cache unit inputs to the above-mentioned first module of M+1 shift cache unit, and N 〉=M.
4. a display system comprises:
One display module; And
One signal drive circuit according to claim 3 is in order to produce a plurality of output pulses, to drive above-mentioned display module.
5. display system according to claim 4, wherein above-mentioned display module are a LCD assembly, a plasma display module, an Organic Light Emitting Diode display module or a cathode-ray tube display assembly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510001870 CN1808624B (en) | 2005-01-18 | 2005-01-18 | Shift cache unit and associated signal drive circuit and display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510001870 CN1808624B (en) | 2005-01-18 | 2005-01-18 | Shift cache unit and associated signal drive circuit and display system |
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| Publication Number | Publication Date |
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| CN1808624A CN1808624A (en) | 2006-07-26 |
| CN1808624B true CN1808624B (en) | 2010-04-28 |
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| CN 200510001870 Expired - Fee Related CN1808624B (en) | 2005-01-18 | 2005-01-18 | Shift cache unit and associated signal drive circuit and display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008216961A (en) * | 2007-03-02 | 2008-09-18 | Samsung Sdi Co Ltd | Organic light emitting display and drive circuit thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369871A (en) * | 2001-02-13 | 2002-09-18 | 三星电子株式会社 | Shift register and liquid crystal display using same |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369871A (en) * | 2001-02-13 | 2002-09-18 | 三星电子株式会社 | Shift register and liquid crystal display using same |
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