JP2502742B2 - Horizontal sync signal detector - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video tape recorder (hereinafter abbreviated as VTR).
The present invention relates to a horizontal synchronizing signal detecting device for detecting a horizontal synchronizing signal including a time base fluctuation from the reproduced video signal of.

Conventional technology In recent years, due to the rapid development of semiconductor technology, large-scale digital circuits have been integrated into LSIs and A / D, D / A capable of operating at video rates.
Converters can be realized at low cost, and time axis correction devices (time base collectors) etc. can also be realized by using digital memory even in consumer VTRs.

This time-axis correction device corrects the time-axis fluctuation of the reproduced video signal caused by the relative speed fluctuation of the tape and cylinder of the VTR. In order to correct the time base fluctuation of the reproduced video signal, the time base fluctuation must be detected from the reproduced video signal. In order to detect this time-axis fluctuation, it is general to detect with a synchronizing signal of the reproduced video signal.

An example of the conventional horizontal synchronizing signal detecting device will be described below with reference to FIG.

The reproduced video signal input from the input terminal 1 has its sync signal separated by the sync separation circuit 2, and is input to the gate circuit 3 and the equalization pulse removal circuit 5. The synchronization signal input to the equalization pulse removal circuit 5 is a so-called automatic frequency composed of a phase comparator (PC) 6, a low pass filter (LPF) 7 and a voltage controlled oscillator (VCO) 8 after the equalization pulse is removed. Input to the control circuit 10. The output signal from the voltage controlled oscillator 8 of the automatic frequency control circuit 10 is input to the gate width adjustment circuit 9, and the output signal is output from the gate circuit 3
Is input to The synchronization signal gated by the gate circuit 3 is output to the output terminal 4.

A specific operation of the conventional horizontal synchronizing signal detecting device configured as described above will be described with reference to FIGS. 6 and 7. However, FIG. 7 is an output waveform diagram in each circuit of FIG. 6, and the same reference numerals are given to the same signals.

The reproduction video signal a input from the input terminal 1 is separated into the synchronization signal b by the synchronization separation circuit 2. The equalized pulse removing circuit 5 removes the equalized pulse near the vertical synchronizing signal from the separated synchronizing signal b, and outputs it to the phase comparator 6 as a horizontal synchronizing signal pulse c. Further, the output pulse d from the voltage controlled oscillator 8 whose free-running oscillation frequency is near the horizontal synchronizing signal period (f _H = 15.73 kHz) is input to the phase comparator 6. The phase difference voltage from the phase comparator 6 passes through the low pass filter 7 and is fed back to the voltage controlled oscillator 8, so that the output pulse d from the voltage controlled oscillator 8 is always in phase synchronization with the horizontal synchronizing signal pulse c. It's working. The output pulse d from the voltage controlled oscillator 8 synchronized with the horizontal synchronizing signal pulse c is adjusted by the gate width adjusting circuit 9 to the gate pulse e which is gated for a period of 2 to 3 μsec before and after the leading edge of the synchronizing signal b. It is input to the circuit 3. Sync signal b
Is input to the gate circuit 3, gated by the gate pulse e, and output to the output terminal 4 as the output pulse f. Since the gate pulse e is output from the automatic frequency control circuit 10, the gate pulse e is output in a stable horizontal synchronizing signal cycle and is less likely to be affected by noise. Therefore, even when noise is present in the reproduced video signal at a position sufficiently distant from the front edge of the synchronization signal b as shown in A of FIG. 7A, it can be easily gated and removed.

As described above, by optimizing the response characteristic of the automatic frequency control circuit 10 by selecting the gate width of the gate pulse e, the leading edge of the synchronizing signal b can be stably detected and the time axis fluctuation can be detected.

However, in the above configuration, when there is noise at a position close to the front edge of the synchronization signal b (case B as shown in FIG. 7a), the gate circuit 3 performs the gate operation. A plurality of pulses are detected in the vicinity of the regular sync pulse in the sync signal pulse f, and the time axis fluctuation is erroneously detected. Further, in the case where a skew occurs at the head switching, such as during special reproduction, the gate pulse e created by the automatic frequency control circuit 10 deviates from the sync signal b to be detected, and accurate sync signal detection is performed. There is a problem that you can't.

In view of the above point, the present invention can detect the sync signal without fail even if there is a small noise between the sync signal pulses, and can detect the normal sync signal accurately even during special reproduction. The purpose is to provide a device.

Means for Solving the Problems In order to achieve this object, a horizontal sync signal detecting apparatus of the present invention comprises a sync signal separating means for separating a sync signal from a reproduced input video signal, and a sync signal separating means at the time of normal reproduction. First pulse width detection means for detecting a synchronization signal having a first pulse width or more, and second pulse width detection means for detecting a synchronization signal having a second pulse width or more from the synchronization signal during special reproduction, Depending on the reproduction mode, the first pulse width detecting means, the synchronizing signal selecting means for selecting the output signals of the second pulse width detecting means, and the pulse of the synchronizing signal output from the synchronizing signal selecting means are missing pulse. And a pulse correction means for correcting the pulse when it occurs.

The present invention is the horizontal synchronizing signal detecting device having the above-mentioned configuration, wherein the synchronizing signal is separated by the synchronizing signal separating means, and the separated synchronizing signal having a width of, for example, about 4 μsec or more is regarded as the synchronizing signal. The pulse width detection means and the second pulse width detection means that regards the separated sync signal having a width of, for example, about 2 μsec or more as the sync signal are selected by the sync signal selection means according to the reproduction mode, and the output synchronization is performed. When the signal pulse is not output in the regular horizontal synchronizing signal period, the pulse correcting means corrects with a pulse created by counting from the synchronizing signal pulse immediately before the missing synchronizing signal pulse.

Embodiment An embodiment of the horizontal synchronizing signal detecting apparatus of the present invention will be described with reference to FIG.

The reproduced video signal input from the input terminal 11 is input to the sync separation circuit 12 to separate the sync signal. The separated sync signal is input to the first pulse width detection circuit 13 and the second pulse width detection circuit 14. First pulse width detection circuit 13
Means that the width of the synchronizing signal is, for example, 4 μsec or more, is regarded as the synchronizing signal, and the second pulse width detecting circuit 14
Is to consider a sync signal having a width of, for example, 2 μsec or more as a sync signal. First pulse width detection circuit 1
3. The synchronizing signal pulse output from the second pulse width detection circuit 14 is input to the switching circuit 15 and switched and output by the reproduction mode switching control signal input from the other input terminal 16. The synchronization signal output from the switching circuit 15 is
It is input to each circuit other than the reference oscillator 20 of the synchronization pulse correction circuit 21 including the synchronization pulse generation circuit 17, the synchronization loss determination circuit 18, the counter circuit 19, and the reference oscillator 20. A fixed reference clock is input from the reference oscillator 20 to the counter circuit 19, and its output is input to the sync loss determination circuit 18 and the sync pulse generation circuit 17. Synchronous pulse generation circuit
In 17, when the sync signal is lost by the determination signal from the sync loss determination circuit 18, the signal is switched to the signal from the counter circuit 19 and the corrected sync signal pulse is output to the output terminal 22.

Next, the specific operation of this embodiment will be described with reference to FIGS. 1, 2, and 3.

2 and 3 are output waveform diagrams in each circuit of FIG. 1, and the same symbols are given to the same signals. However, FIG. 2 is a waveform diagram during normal reproduction, and FIG. 3 is a waveform diagram during special reproduction.

The reproduced video signal g input from the input terminal 11 is separated from the sync signal by the sync separation circuit 12. The separated sync signal h is detected by the first pulse width detection circuit 13 during normal reproduction and by the second pulse width detection circuit 14 during special reproduction. The first pulse width detection circuit 13 is a circuit that regards only the pulse in which the pulse width of about 4 μsec or more is detected from the leading edge of the input pulse as a synchronization signal and otherwise regards it as noise. Therefore, when there is noise in the middle of the sync signal such as C and D of the reproduced video signal g in FIG. 2 and the width of the sync signal is 4 μsec or less, the output from the first pulse width detection circuit 13 The synchronizing signal pulse i is E, F in FIG.
The sync signal pulse is not detected. The second pulse width detection circuit 14 is a circuit that regards only the pulse in which the pulse width of about 2 μsec or more is detected from the leading edge of the pulse of the input synchronization signal h as the synchronization signal, and otherwise treats it as noise. . Therefore, if there is noise in the vicinity of the leading edge of the sync signal such as C of the reproduced video signal g in the figure, the noise is removed as in G in the figure j and the phase of the trailing edge of the sync signal h is removed. Is accurately detected, but the reproduced video signal g in FIG.
When there is a noise diagram near the trailing edge of the synchronizing signal as in D of FIG. 7, the phase of the trailing edge of the synchronizing signal h is not accurately detected and a phase error occurs as in H of FIG.

The output signals of the first pulse width detection circuit 13 and the second pulse width detection circuit 14 are input to the switching circuit 15 and other input terminals.
From the reference numeral 16, the reproduction mode switching control signal is used to output by switching the synchronizing signal pulse i of the first pulse width detection circuit 13 for normal reproduction and the synchronizing signal pulse j of the second pulse width detection circuit 14 for special reproduction. ing. The sync signal pulse output from the switching circuit 15 is input to the sync pulse correction circuit 21 and the missing pulse is corrected. In the sync pulse correction circuit 21, the counter circuit starts from the leading edge of the input sync signal pulse.
The reference clock from the reference oscillator 20 is counted at 19 and the period T _H (T _H 61 μse) is slightly shorter than one horizontal scanning period.
If the leading edge of the sync pulse does not come in after passing c), the sync loss determination circuit 18 determines that there is a sync loss, and the output signal 1 of the sync pulse generation circuit 17 is replaced with the output pulse k of the counter circuit 19. , The synchronization signal pulse is corrected. On the other hand, when the leading edge of the sync signal pulse arrives in the period T _H , the sync loss determination circuit 18 determines that there is no sync loss, and the sync pulse generation circuit 17 outputs the sync signal pulse as it is at the output terminal 22. Is output as a sync signal pulse 1.

At the time of normal reproduction, the switching circuit 15 outputs the synchronization signal pulse i output from the first pulse width detection circuit 13, and the pulse omissions occur in the E and F portions of FIG. The synchronization signal pulse 1 is output to the output terminal 22 after being corrected by the correction pulse k from the synchronization pulse correction circuit 21. Since the corrected pulse has a phase close to that of a normal synchronizing signal pulse, during normal reproduction, the synchronizing signal pulse j from the second pulse width detecting circuit 14 is shifted to the synchronizing signal from the first pulse width detecting circuit 13. The corrected pulse l of the pulse i has less malfunction detection. Next, in the case of special reproduction, particularly when the head is switched in the middle of the reproduced video signal, when the noise J is included in the synchronization signal immediately after the head switching I in the reproduced video signal g in FIG. As for the output of the pulse width detection circuit 13 of No. 1, the sync signal pulse is omitted as indicated by K in FIG. In this case, when the switching circuit 15 outputs the synchronizing signal pulse i, the missing pulse is corrected by the synchronizing pulse correction circuit 21 and a signal such as l'in the figure is output. That is, in the K part of the synchronization signal pulse j,
Since a pulse generated by counting from the synchronizing signal pulse L before the horizontal scanning period enters, if there is a skew due to head switching in this period, the phase differs from that of the normal synchronizing signal pulse as indicated by M in FIG. Will be corrected by the pulse. Therefore, in this case, the second pulse width detection circuit
A signal with less pulse dropout such as the output j from 14 can detect the synchronizing signal pulse relatively stably even with respect to the skew immediately after the head switching, and the malfunction is less.

Therefore, during special reproduction, the output j from the second pulse width detection circuit 14 is output to the output terminal 22 through the sync pulse correction circuit 21.
It is output as a synchronization signal pulse l.

Next, a specific embodiment of the first and second pulse width detection circuits 13 and 14 will be described with reference to FIGS. 4 and 5. FIG. 5 is a waveform diagram of each part in FIG. 4, and the same signals are given the same reference numerals.

The mono-multi 24 is triggered at the leading edge of the pulse m having the pulse width T _H including the noise component input to the input terminal 23 to generate the low pulse o of the period Δt, and the clock terminal C _{k of the} latch circuit 26.
To enter. On the other hand, the data input terminal D _IN of the latch circuit 26
Is the pulse n obtained by inverting the pulse m by the inverter circuit 25.
, And pulse n is latched at the trailing edge of pulse o. Further, the pulse m is also input to the reset terminal R of the latch circuit 26, the latch circuit 26 is reset at the trailing edge of the pulse m, and the output of the latch circuit 26 is reset to low.

By the above operation, a pulse q from which the noise component in the input pulse is removed is obtained at the output of the latch circuit 26, which is inverted by the inverter circuit 27 to obtain the output pulse q of the pulse width detection circuit. Here, in the case of the first pulse width detection circuit 13, the time constant Δt of the monomulti 24 is Δt as described above.
It is set to ≧ 4 μsec, and a pulse having a width of Δt or more is detected as a synchronization signal pulse. Further, in the case of the second pulse width detection circuit 14, the time constant Δt of the monomulti 24 is set to Δt ≧ 2 μsec, and the pulse having the width of Δt or more is detected as the synchronization signal pulse.

The sync signal separated as described above is detected by changing the pulse width detection level of the sync signal in each of the normal reproduction and the special reproduction. Even if there is a small noise between the signal pulses, the sync signal can be reliably detected, and the normal sync signal can be accurately detected to detect the time axis fluctuation even during special reproduction.

EFFECTS OF THE INVENTION As described above, according to the present invention, the sync signal separated by the first pulse width detection circuit is 4 μm during normal reproduction.
Anything less than sec is regarded as noise and the pulse is extracted, and the missing sync signal pulse is corrected by the sync pulse correction circuit, so that a stable sync signal pulse can be detected. Also, during special reproduction, if the sync signal pulse of 2 μsec or less in the second pulse width detection circuit is regarded as noise and removed, and the pulse dropout is smaller than in the first pulse width detection circuit, skew may occur. However, the regular sync signal pulse can be stably detected, and the time axis fluctuation can be detected without causing erroneous detection with the corrected pulse.

[Brief description of drawings]

FIG. 1 is a block diagram of a horizontal synchronizing signal detecting apparatus according to an embodiment of the present invention, FIG. 2 is an output waveform diagram of each portion during normal reproduction in FIG. 1, and FIG. 3 is during special reproduction in FIG. FIG. 4 is a block diagram of the pulse width detecting circuit in the embodiment of the present invention, FIG. 5 is an output waveform diagram of each part of FIG. 4, and FIG. 6 is a conventional horizontal synchronizing signal detecting device. FIG. 7 is a block diagram and FIG. 7 is an output waveform diagram of each part of FIG. 11, 16 ... Input terminal, 12 ... Sync separation circuit, 13 ... First pulse width detection circuit, 14 ... Second pulse width detection circuit, 15 ... Switching circuit, 17 ... Sync pulse generation circuit, 18 ... Sync loss detection Circuit, 19 ... Counter circuit, 20 ... Reference oscillator, 21 ... Synchronous pulse correction circuit, 22 ... Output terminal.

Claims (1)

(57) [Claims] 1. A sync signal separating means for separating a sync signal from a reproduced input video signal; a first pulse width detecting means for detecting a sync signal having a first pulse width or more from the sync signal; Second pulse width detecting means for detecting a synchronizing signal having a second pulse width or more from the signal, and output signals of the first pulse width detecting means and the second pulse width detecting means depending on the reproduction mode. A horizontal synchronizing signal detecting device comprising: a synchronizing signal selecting means; and a pulse correcting means for correcting a pulse of the synchronizing signal output from the synchronizing signal selecting means when the pulse is missing.