JPH02149185A - Synchronizing separator device - Google Patents

Abstract

PURPOSE:To attain stable synchronizing separator by controlling a gate circuit so as not transmit an output pulse of a synchronizing separator circuit other than the vicinity of the synchronizing signal and using a pulse a width detection circuit and a synchronizing pulse correction circuit so as to eliminate a mis- detection pulse and to correct missing of synchronizing pulse. CONSTITUTION:Even if noise is superimposed on a synchronizing signal or missing of synchronization takes place such as dropout, mis-detection pulse due to noise component except the vicinity of a synchronizing signal is eliminated by using a control circuit 14 controlling a gate circuit 13 provided after the synchronizing separation circuit 12 and a gate circuit 13 so that an output pulse of the synchronizing separator 12 does not transmit except in the vicinity of the synchronizing signal. Moreover, a pulse width detection circuit 15 and a synchronizing pulse correction circuit 21 eliminate mis-detection pulse due to noise component in the vicinity of the synchronizing signal and execute the correction of synchronizing pulse missing. Thus, the stable synchronizing separation without mis-detection and missing of synchronizing signal is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization separator that separates a horizontal synchronization signal from a reproduced video signal of a video tape recorder (hereinafter abbreviated as VTR). This invention relates to a synchronization separation device for absorbing shaft fluctuations and correcting skew.

Conventional technology: In recent years, with the rapid development of semiconductor technology, large-scale digital circuits have been converted into LSIs, and A/
I) Digital video processing technology that enables D/person converters to be realized at low cost and has functional features such as screen freeze, multi-screen, field noise reducer, etc. using digital memory, even in consumer video equipment. (For example, Japan Broadcasting Publishing Association [Electronics Life J July 1988 issue, pp. 19-32).

When writing a VTR playback video signal to digital memory, it is common to control the memory operation based on the synchronization signal of the video signal, and the reference clock is a clock synchronized with the horizontal synchronization signal (line lock clock). is often used.

Therefore, it is essential that the horizontal synchronization signal, which serves as a synchronization reference for digital memories, has stable synchronization separation without loss of synchronization or false detection due to noise or dropouts that occur during VTR playback. Therefore, conventionally, an automatic frequency control circuit (hereinafter abbreviated as AFC circuit) has been used to stabilize the synchronous separation output.

Hereinafter, an example of the above-mentioned conventional synchronization separation device will be described with reference to the drawings. FIG. 6 is a block diagram of a conventional synchronization separation device, and FIG. 6 is a waveform diagram for explaining the same.

In FIG. 6, 1 is an input terminal, 2 is a low-pass filter (hereinafter abbreviated as LPF), 3 is a synchronization separation circuit, 4 is an equalization pulse removal circuit for removing the equalization pulse portion in the synchronization signal, and 5 is an equalization pulse removal circuit for removing the equalization pulse portion in the synchronization signal. An AFC circuit consisting of a phase comparator 6° loop filter, a voltage controlled oscillator 8 (hereinafter abbreviated as VCO),
9 is an output end.

Regarding the conventional synchronous separation device configured as above,
The operation will be explained below. Here, awd in FIG. 6 corresponds to the waveform diagram of aNa in FIG.

First, the video signal (or luminance signal) that enters the input terminal 1 is band-limited by the LPF 2 and unnecessary noise components are removed, and then synchronously separated by the synchronous separation circuit 3 to obtain a synchronous signal.

An equalization pulseless removal circuit 4 removes equalization pulses for each A horizontal scanning period inserted near the vertical scanning period to obtain a synchronizing pulse C. Further, the synchronization pulse C is passed through the FC circuit 6 to improve stability against noise, synchronization loss, etc., and then a horizontal synchronization signal output d is obtained from the output terminal 9.

Here, as is well known, the mu FG circuit 6 is composed of a phase comparator 6, a loop filter 7, and VCOs, and the free-running oscillation frequency of the VCOs is the horizontal scanning frequency (fH=15.75k )+z), and operates to automatically synchronize the phase so that the phase difference with the synchronized Hullless C of the output Hullest equalization Hals removal circuit 4 of vcos becomes zero. When handling VTR playback signals, try to minimize fluctuations caused by jitter (time axis fluctuations) that occur during VTR playback, synchronization signal loss due to dropouts, synchronization disturbances due to playback of demagnetized tapes, etc. The response speed of the AFC circuit 5 is selected and is normally set to respond in a horizontal scanning period of 10 to 2 degrees. Therefore, for example, if a synchronization signal loss occurs as shown by the circle mark in FIG. When this is passed through the AFC70 circuit, AF
Since the C circuit 5 responds only during 10 to 20 horizontal scanning periods, the synchronizing signal is automatically corrected and output from the output terminal 9, as shown by circle C in FIG.

As mentioned above, conventionally, by passing the mu FG circuit 6,
The response speed of the FC circuit 5, in other words, the integral effect of the human FG circuit 5 is used to absorb synchronization signal dropout and instability of the synchronization signal due to noise.

Problems to be Solved by the Invention However, in the conventional configuration as described above, since the response speed of the FC circuit 5 is used to stabilize the synchronization signal, synchronization due to skew distortion that occurs during high-speed search of the VTR occurs. It cannot respond to signal discontinuities or sudden time axis fluctuation components that occur when the playback head comes into contact with the tape. However, this method has the problem of causing skew distortion and curved vertical lines, making the screen unsightly.

In view of the above, the present invention provides a synchronization separation device that can perform stable synchronization separation without false detection and without loss of synchronization, even if the synchronization signal is discontinuous or sudden fluctuations in the time axis occur. The purpose is to provide.

Means for Solving the Problems In order to solve the above problems, the synchronization separation device of the present invention includes a low-pass filter that limits the band of an input video signal, and a synchronization separator that separates a synchronization signal from the output of the low-pass filter. a gate circuit that applies a gate to the output pulse of the synchronization separation circuit, a control circuit that controls the gate circuit, and a high/low/high width detection circuit that extracts a pulse having a predetermined pulse width or more from the output of the gate circuit. , a synchronization pulse correction circuit that corrects the synchronization pulse when there is a pulse omission in the synchronization pulse output from the pulse width detection circuit.

Effect of the Invention With the above-described configuration, the present invention can stabilize the synchronization signal without directly passing it through the human FC circuit, and can immediately deal with skew distortion during high-speed search of a VTR and rapid time axis fluctuation components of the reproduced signal. When applied to a time base collector (TBC) 8, it is possible to remove bends in vertical lines and skew distortion.

Embodiment Hereinafter, a synchronization separation device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a synchronization separation device in a first embodiment of the present invention, and FIG. 2 is a waveform diagram of each part. Here, a in Figure 1
-h corresponds to the waveform diagrams a to h in FIG.

First, the video signal (or brightness signal) a input to the input terminal 1 is band-limited by the LPF 2 and unnecessary noise components are removed, and then supplied to the clamp circuit 11, where it is clamped to a predetermined DC voltage value. At the same time, the sag component contained in the input video signal a is removed. The video signal clamped to the DC voltage is sent to the synchronous separation circuit 12.
and the gate control circuit 14. Synchronous separation circuit 1
In step 2, the voltages of the synchronizing signal portion are compared at a predetermined threshold level, and only the synchronizing signal component is separated to obtain the waveform shown in FIG.

Here, the noise components (■, ■) shown by ■, ■, ■ in Figure 2 a and the irregular synchronization signal (o) are erroneously detected as they are and are output as shown in the waveform, and the gate The signal is supplied to the circuit 13.

On the other hand, the gate control circuit 14 includes a sync separation circuit 3, an equalization pulse removal circuit 4, and an AFC circuit 5, and the sync signal C separated by the sync separation circuit 3 is transmitted to the equalization pulse removal circuit After the equalization pulse portion for each A horizontal scanning period near the vertical scanning return line is removed in step 4, the AFC circuit 5
is supplied to

As described in the conventional example, the FC circuit 5 is composed of a phase comparator 6, a loop filter 7, and a vcoa, and is phase-synchronized with the synchronization signal C, and has a control pulse width wider than that of the synchronization signal C. Generate pulse d.

The control pulse d is used as a control signal for the gate circuit 13, and the gate circuit 13 is configured to output an output pulse only when a low pulse of the synchronization signal exists during a period when the control pulse d is at a low level. That is, the gate circuit 13 includes the inverter circuits 22 and 23, and the HA
When a synchronizing signal is input to the inverter circuit 22 and a control pulse d is input to the inverter circuit 23, an output pulse e is obtained as the output of the HAND gate 13.

In this way, even if the synchronization separation circuit 12 erroneously detects noise components (for example, the part ■ in FIG. For example, the portion 0 in FIG. 2) will be removed from the output of the gate circuit 13.

Next, from the output pulse e of the gate circuit 13, a pulse width detection circuit 16 removes the pulse having a predetermined pulse width or less as a noise component to obtain a synchronization pulse r.

That is, note that the normal synchronization pulse has a pulse width t8 of approximately 4.7μ, and the pulse @tH is approximately 2 to 3 μm.
Pulses with a width of μ (for example, part ■ in Figure 2) are considered to be false detection pulses due to noise, and are completely removed, with a pulse width of tH
A synchronizing pulse f is generated only when the value is 2 to 3 μm or more.

Finally, the synchronizing pulse f is corrected for missing synchronizing pulses by a synchronizing pulse correction circuit 21. The synchronization pulse correction circuit 21 is the synchronization pulse generation circuit 16. Discrimination circuit 17 for synchronization. Counter circuit 18. Clock generation circuit 19. crystal oscillator 20
The clock of the clock generation circuit 19 is counted by the counter circuit 18 from the rising edge of the synchronization pulse f, and even after a period TH (TH-=61μ), which is slightly shorter than one horizontal scanning period, the synchronization pulse f is If a falling edge does not come in, the circuit 17 determines that there has been a loss of synchronization, and the output of the synchronization pulse generation circuit 16 is replaced by the output of the counter circuit 18, Harres g, to correct the synchronization pulse. (See O in the second diagram). on the other hand,
If the fall of the synchronizing force less f is input during the period TH,
When there is no loss of synchronization, the determination circuit 17 determines that there was no loss of synchronization.
The output of the synchronization pulse generation circuit 16 is to directly output the synchronization pulse r to the output terminal 9 as a synchronization pulse h.

Note that the pulse width detection circuit 15 detects the pulse width t.

Although any configuration may be used as long as it allows a pulse having a width of 2 to 3 microns or more to pass through, in this embodiment, a pulse width detection circuit as shown in FIG. 3 is used. FIG. 3 is a block diagram of the above-mentioned pulse width detection circuit, and FIG. 4 is a waveform diagram of each part. Here, a' to e' in FIG. 3 are a' to e' in FIG.
This corresponds to the waveform of e'.

The operation of the pulse width detection circuit used in this example is explained below in the third example.
This will be explained with reference to the figures and FIG.

Pulse containing noise input to input terminal 31 @TH
The monomulti 32 is triggered by the falling edge of the pulse a', and a low pulse C' with a period Δt is generated, and the latch circuit 3
4 to clock terminal C. On the other hand, latch circuit 3
For the data input terminal No. 4, the pulse width a' is inverted by the inverter circuit 33, the pulse width a' is inputted, and the pulse width a' is latched at the rising edge of the pulse b/pulse C' (point ■ in Figure 4).
. Furthermore, the pulse a' is sent to the reset terminal R of the latch circuit 34.
is also input, the latch circuit 34 is reset at the rising edge of the pulse a', and the output of the latch circuit 34 is reset to low (point ■ in FIG. 4).

Through the above operation, a pulse d' from which noise in the input pulse has been removed is obtained as the output of the latch circuit 34. This is inverted by the inverter circuit 36, and the pulse width detection circuit 1
6 output pulses e' are obtained. Here, the time constant Δt of the monomulti 32 is the pulse width TH of the synchronizing signal, as described above.
Since Δt is approximately 4.7μ wide, the formula is set to Δt = 2 to 3μ, which is about half of 4.7μ, and pulses with a width greater than Δ are detected as synchronous pulses. .

As described above, according to this embodiment, even if noise is superimposed on the synchronization signal or loss of synchronization occurs due to dropout, etc., the gate circuit provided after the synchronization separation circuit and the synchronization separation circuit other than the vicinity of the synchronization signal A side hearing circuit that controls the gate circuit so that the output pulse of the circuit does not pass through removes erroneously detected pulses due to noise other than the vicinity of the synchronization signal, and a pulse width detection circuit and a synchronization pulse correction circuit eliminate the By removing erroneously detected pulses due to noise near the sync signal and correcting missing sync pulses, stable synchronization separation without erroneous detection or missing synchronization can be performed.

Further, according to this embodiment, the synchronous pulse is not immediately passed through the human yc circuit to be stabilized, and the erroneously detected pulse is removed by the gate circuit and the pulse width detection circuit, and the synchronous pulse is detected using the counter circuit. The synchronization pulse is stabilized by correcting it, and it can instantly compensate for steep time axis fluctuations caused by contact between the tape and the head that occur during playback of "/TR" and skew distortion during high-speed search. Accurate synchronous separation pulses can be obtained in response.

In this embodiment, the clock generation circuit 19 is configured to generate a clock using a crystal oscillator 20, but as shown by the broken line in FIG. A pulse may also be used as a clock.

Furthermore, although the gate control circuit 14 is composed of a synchronization separation circuit 3, an equivalent pulse removal circuit 4, and an AFC circuit 6,
Instead of the C circuit 6, integration for one horizontal scanning period is performed,
The structure may be such that the gate control pulse d can be generated before and after the synchronization pulse b based on the integral value.

Further, although the synchronization separation circuits 3 and 12 have been described as separate circuits, they may be shared in order to simplify the circuit configuration.

Further, the processing described in the present invention can also be realized by digital processing after A/D conversion of the video signal.

Effects of the Invention As described above, according to the present invention, even if synchronization loss occurs due to noise superimposed on the synchronization signal9, dropout, etc., the output pulse of the synchronization separation circuit is prevented from passing through except in the vicinity of the synchronization signal. The gate circuit is controlled to eliminate erroneously detected pulses due to noise other than those near the sync signal, and the pulse width detection circuit and sync pulse correction circuit eliminate erroneously detected pulses due to noise near the sync signal. By performing this and correcting synchronization pulse dropouts, stable synchronization separation without false detection or synchronization dropouts can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization separation device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a block diagram of a pulse width detection circuit of this embodiment, and FIG. 4 6 is a waveform diagram of each part, FIG. 6 is a block diagram of a conventional example, and FIG. 6 is a waveform diagram of each part of FIG. 3.12... Synchronization separation circuit, 4... Equalization pulse removal circuit, 6... AFC circuit, 6...
...Phase comparator, 7...Lube filter, 8...VCO, 11...Clamp circuit, 13...Gate circuit, 14... ...
...Gate control circuit, 16...Pulse width detection circuit, 16...Synchronization pulse generation circuit, 17...
・・Discrimination circuit for synchronization, 18・・Counter circuit, 19・・Clock generation circuit, 2Q・・・・
...Crystal oscillator, 21...Synchronization signal correction circuit. Name of agent: Patent attorney Shigetaka Awano and 1 other person 2nd
Figure Figure Figure

Claims (3)

[Claims] (1) A low-pass filter that limits the band of an input video signal, a sync separation circuit that separates a sync signal from the output of the low-pass filter, a gate circuit that applies a gate to the output pulse of the sync separation circuit, and the gate circuit. A control circuit for controlling, a pulse width detection circuit for extracting a pulse having a predetermined pulse width or more from the output of the gate circuit, and a pulse width detection circuit for correcting the synchronization pulse when there is a pulse omission in the synchronization pulse output from the pulse width detection circuit. A synchronous separation device comprising a synchronous pulse correction circuit. (2) The control circuit includes a separation circuit that separates a synchronization signal from a low-pass filter output, an automatic frequency adjustment circuit configured such that the separation circuit output and the output of the voltage controlled oscillator are phase-synchronized, and the automatic frequency adjustment circuit. 2. The synchronization separation device according to claim 1, wherein the gate circuit is controlled so that the output pulse of the synchronization separation circuit is transmitted only during an output pulse generation period of the circuit. (3) The synchronization pulse correction circuit includes a counter circuit that counts a predetermined time from an input synchronization pulse, a synchronization pulse omission determination circuit that determines whether or not an input synchronization pulse has occurred based on the output of the counter circuit and the input synchronization pulse; If the synchronization pulse dropout determination circuit determines that the input synchronization pulse has been dropped, outputs the counter output;
If it is determined that the input sync pulse is not missing,
Claim 1, further comprising a synchronization pulse generation circuit configured to output the input synchronization pulse as it is.
The synchronization separation device described.