JPS6038068B2 - AFC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called counter-type AFC circuit suitable for application to a write clock pulse generation circuit of a time axis error correction device for color video signals reproduced from a VTR, and particularly to an input horizontal synchronizing signal. The purpose of the present invention is to propose a system that can rapidly lock the phase and obtain an output horizontal synchronizing signal without any dropout even if there is a large phase variation or dropout in the input horizontal synchronization signal due to, for example, skew in a VTR. .

Below, with reference to FIG. 1, an embodiment in which the present invention is applied to an AFC circuit for PAL color video signals will be described in detail.

21 is a phase lock droop (hereinafter abbreviated as PLL), which will be explained below.

27 is a variable frequency oscillator whose center frequency is a frequency N (1135 in this example) multiplied by the horizontal frequency.

In this example, the center frequency of this variable frequency oscillator is four times the color subcarrier frequency. Reference numeral 29 is a frequency division counter which divides the carry output of the variable frequency oscillator 27 by a factor of 1 and can be cleared by the output itself.

In the counter 29, CK is a clock pulse input terminal, CARRY is a carry output terminal, and CL is a clear input terminal. Carry output CR of counter 29 (Fig. 2~
(see F in FIG. 5) is supplied to the clear input terminal CL through the NOR circuit 17. 24 is a signal HP (see E in FIGS. 1 to 5) having a predetermined phase relationship with respect to the input horizontal synchronization signal P (see A in FIGS. 2 to 5 and FIG. 6) and a frequency divider counter. This is a phase comparator circuit that supplies the phase of the IJ output of the variable frequency oscillator 29 through the first gate circuit 30, compares the phases thereof, and controls the oscillation frequency of the variable frequency oscillator 27 based on the output. The first gate circuit 30 consists of AND circuits 22 and 23, and the signal HP is supplied to the AND circuit 22, and the carry output CR of the counter 29 is supplied to the AND circuit 23. A gate signal is supplied. And these AND circuits 22 and 23
The output of is supplied to the phase comparator circuit 24. This phase comparator circuit 24 uses, for example, an MC4044 phase/frequency detector. The output of the phase comparator circuit 24 is supplied to a charge pump 25. This charge pump 25 is driven by two positive and negative comparison outputs from the phase comparison circuit 24. The output of the charge pump 25 is supplied to a low pass filter 26. This low pass filter 26
A fully integral type filter is used, and the current is driven by a charge pump 25. The output of this low-pass filter 26 is then supplied to a variable frequency oscillator 27 to control its oscillation frequency and phase. 31 determines whether the phase fluctuation of the reproduced horizontal synchronizing signal separated from the reproduced color video signal from the VTR as the input horizontal synchronizing signal supplied to the input terminal exceeds a predetermined phase range; and if it does not exceed the first
This is a phase fluctuation discriminating circuit that closes and opens the gate circuit 30 of.

This phase variation discriminator circuit 31 consists of first and second discriminator circuits 9 and 10. The first judgment circuit 9 is a circuit that detects when the phase of the input horizontal synchronizing signal is delayed or when the input horizontal synchronizing signal is missing. The second discrimination circuit 10G is a discrimination circuit that detects that the phase of the input horizontal synchronizing signal has advanced. The following signals are supplied to the first and second discrimination circuits 9 and 101. The input horizontal synchronizing signal P from the input state 1 (see Figures 2 to 5 A and 6) is input to the first wind pulse generation circuit 2-3, which is composed of a monostable multipipelator. 3- is supplied to the pulse generating circuit 4, and the above-mentioned pulse HP is outputted from this pulse generating circuit 4. Four first wind pulses W, (see FIGS. 2 to 5C) from the first wind pulse generation circuit 2 are supplied to the first discrimination circuit 9. Further, the input horizontal synchronizing signal P from the input terminal 1 is supplied to the pulse generation circuit 7, and the pulse signal S2 obtained from this (Figs. 2 to 5
) is supplied to the second discrimination circuit 10'. 35 indicates the contents A, B, . . . of each bit of the above-mentioned dividing counter 29.
This is a decoder that supplies timing signals TP, .

A pulse signal TP (see FIGS. 2 to 5B) indicating this timing is supplied to the pulse generation circuit 6 and the second wind pulse generation circuit 8. This second window pulse generation circuit 8 is supplied with V as a set pulse based on the output of the above-mentioned /A circuit 17. And the number of pulse generation is 0
The pulse signal S, (see FIGS. 2 to 5G) from the path 6 is supplied to the first discrimination circuit 9, and the second wind pulse W2 from the second wind pulse generation circuit 8 (see FIGS. 5) is supplied to the second discrimination circuit 101. The discrimination outputs DT, (see FIGS. 2 to 5 J) and the second discrimination output DT2 (see FIGS. 2 to 5 K) from these first and 25th discrimination circuits 9 and 10 are NAND. circuit 1
V is supplied to 1. The output of this NAND circuit is then combined as a gate signal to each AND circuit 022 and 23 of the first gate circuit 30 through the NOR circuit 13.
12 is a phase fluctuation determination circuit 31 when there is no input horizontal synchronizing signal at the time of power-on and for a period longer than the field
If no output is obtained from the
and 23 to open them and activate the PLL 21.

14, when the phase fluctuation of the input horizontal synchronizing signal exceeds a predetermined phase range based on the output of the phase fluctuation discriminating circuit 31, a lock pulse having a predetermined phase relationship with respect to the input horizontal synchronizing signal is passed, and a frequency division counter 29 is output. A second gate circuit that clears , and is an AND circuit in this example.

The output W from the first wind pulse generation circuit 2 is supplied to the lock pulse generation circuit 5, and the lock pulse KL (see ○ in FIGS. 2 to 5) is obtained from the lock pulse generation circuit 5. This is supplied to the AND circuit 14. Furthermore, the output of the NOR circuit 13 is supplied to an AND circuit 14 via an inverter circuit 15 as a gate signal. Then, the output of the AND circuit 14 is passed through a delay circuit 16 for phase compensation, and further passed through a NOR circuit 17 to a clear terminal C of a frequency division counter 29.
I am trying to supply it to L. Incidentally, the lock pulse generation circuit 5, the pulse generation circuits 6 and 7, and the second wind pulse generation circuit 8 are supplied with a frequency signal from the variable frequency oscillator 17, and outputs synchronized therewith are obtained from each of these circuits. It is made so that it can be done.

I will explain further. 20 is an output horizontal synchronization signal output terminal.

The output of the /A circuit 18 is the output horizontal synchronizing signal P' (Fig.
5L and 6), the output of the AND circuit 19 is supplied together with the carry CR output of the cylinder division counter. The output of the AND circuit 14 is supplied to the AND circuit ZI9, and the inhibit gate signal from the decoder 35 is also supplied to the AND circuit ZI9. When the phase of the input horizontal synchronization signal is stable, the carry output CR of the counter 29 is obtained as the output horizontal synchronization signal P' at the output terminal 20, and even when the phase of the input horizontal synchronization is delayed or missing. It is similar,
When the phase of the input horizontal synchronizing signal advances, the lock pulse KL from the lock pulse generating circuit 5 is outputted from the output terminal 20' as an output horizontal synchronizing signal. Note that the phase of the input horizontal synchronizing signal is delayed in the AND circuit 19, and immediately after the carry output of the frequency dividing counter is obtained as the output horizontal synchronizing signal at the output terminal 20, the lock pulse KL is output as the output horizontal synchronizing signal. This is a circuit to prohibit the use of The operation of the AFC circuit shown in FIG. 1 will be explained below with reference to FIGS. 2 to 6.

First, FIG. 2 and FIGS. 6A and 6B will be explained. FIG. 2 and FIGS. 6A and 6B show the case where there is no phase variation in the input horizontal synchronizing signal, that is, the case is locked-in. Figure 2A
and FIG. 6A shows the input horizontal synchronization signal P without phase fluctuations supplied to the input terminal 1. Pn indicates that certain pulse, and Pn+1 indicates the next pulse. FIG. 2A shows the rising edge of the horizontal synchronizing pulse. Figure 2B
The timing signal TP obtained from the decoder 35 is shown in FIG. FIG. 2C shows the first wind pulse from the first wind pulse generating circuit 2 in FIG. This is a pulse that rises in coincidence with the rise of the horizontal synchronizing signal P and rises after a predetermined time. FIG. 2D shows the lock pulse KL from the lock pulse generating circuit 5, which is a negative pulse and has a predetermined phase relationship with the input horizontal synchronizing signal P. FIG. 2E shows the waveform of the pulse HP obtained from the pulse generating circuit 4. This is a positive pulse substantially in phase with pulse KL. Figure 2 F shows the carry force CR obtained from the frequency division counter.
This waveform is a member pulse. FIG. 2G shows the waveform of the pulse S obtained from the pulse generating circuit 6. This pulse S is a positive pulse. FIG. 2 shows the waveform of the second wind pulse W2 obtained from the second wind pulse generating circuit 8. In FIG. FIG. 2 shows the waveform of the positive pulse S2 obtained from the pulse generating circuit 7. 2J and 2K show the waveforms of the discrimination outputs of the first and second discrimination circuits 9 and IQ. FIG. 2L shows the waveform of the output horizontal synchronizing signal P' obtained from the two output terminals, and the horizontal synchronizing pulses Pn, Pn+ of the input horizontal synchronizing signal P are indicated by dashes, respectively. Next, time 7 to 74 in Figure 2
I will explain about it.

D, is the pulse S. from the rising edge of the first wind pulse W, that is, the rising edge of the input horizontal synchronizing signal P. This is the time until the rise of 72 is the time from the rise of the pulse S to the fall of the lock pulse KL.

? 3 is the time from the rising edge of the timing signal TP, that is, from the rising edge of the second wind pulse W2 to the rising edge of the pulse S2. 74 is the time from the rise of the pulse S to the fall of the carry output CR, that is, the fall of the second wind pulse W2.

And these times 7, to ↑4 are ↑. <A4 and 73
The first and second wind pulses W,
, W2 was selected, and the pulse H was accidentally set during a short skew.
P passes through the first gate circuit 30, or when there is a long skew, the output of CAIJ and CR may be accidentally transferred to the first gate circuit 3.
It is designed so that it never passes through 0. In this case, the same can be said of the horizontal synchronizing pulses Pn and Pn+ as follows.

That is, since the first discrimination circuit 9 reads the level of the first window pulse W, at the rising edge of the pulse S, the output DT of the first discrimination circuit 9 is "1". or,
In the second discrimination circuit 10, the level of the second wind pulse W2 is lowered at the rising edge of the pulse S2, so the output DL of the second discrimination circuit 10 similarly remains at "1". Therefore, the output of the NAND circuit 11 becomes "0", the output of the NOR circuit 13 becomes "1", and the AND circuits 22 and 23 of the first gate circuit 30 are opened to establish a predetermined phase relationship with respect to the input horizontal synchronizing signal. The pulse HP and the carry output CR of the frequency dividing counter 29 are supplied to the phase comparator circuit 24 and compared in phase and frequency.
1 will form a closed loop. At this time, the carrier power CR of the frequency dividing counter 29 is output from the output terminal 2.
Since the AND circuit 14 is closed, the lock pulse KL from the lock pulse generation circuit 5 is obtained as the output horizontal synchronizing signal P' (see Figures 2L and 6B). You will not be able to do so. Next, Figures 3 and 6
Regarding FIGS. C and D, a case where the horizontal synchronizing pulse Pn+ of the input horizontal synchronizing signal P is advanced in phase by Q with respect to the previous horizontal synchronizing pulse Pn, that is, a case where there is a short skew will be described.

In this case, the second discrimination circuit 10
Since the part where there is no wind pulse W2, that is, the part where it is "0", is read by the rising edge of pulse S2,
The output DT2 of the second discrimination circuit 10 becomes "0". Therefore, the output of the AND circuit 11 becomes "1", and the /A circuit 13
The output becomes "0", and the AND circuits 22 and 23 of the first gate circuit 30 are closed. Therefore, the signal to be compared is not supplied to the phase comparator circuit 24, and the variable frequency oscillator 2
7 oscillates at a constant frequency, its oscillation output is supplied to the frequency division counter 29, and its carry output CR is supplied to the clear input terminal CL through the NOR circuit 17. On the other hand, as the output of the NOR circuit 13 becomes "0", the output of the inverter circuit 15 becomes "1", the AND circuit 14 is opened, and the lock pulse KL is changed from the AND circuit 14 to the AND circuit 1.
The horizontal synchronizing signal P' (see FIGS. 3L and 6D) is output from the output terminal 201 through the 9-NOR circuit 18. In this case, the counter 29 is rapidly cleared approximately at the timing of the output horizontal synchronizing signal P', that is, at the lock pulse KL. Next, regarding FIGS. 4 and 6 E and F, the horizontal synchronizing pulse Pn0 in the input horizontal synchronizing signal P. If the phase is delayed by Q with respect to the previous horizontal synchronization pulse Pn,
That is, the case of a long skew will be explained.

At this time, in the first discriminating circuit 9, the part of the first wind pulse W, which is absent, ro'' is suppressed by the rising edge of the pulse S, so that the output DT of the first discriminating circuit 9
, becomes "0" and similarly, the output of the NAND circuit 11 becomes "IJ
Therefore, the first gate circuit 30 is closed as in the case of FIG. In this case, the carry output CR from the frequency dividing counter 29 is the output horizontal synchronizing signal P' (L in Fig. 4).
, see FIG. 6F). In this case, the counter 29 is rapidly cleared at the timing of the lock pulse KL. 5 and 6G, this is a case where no horizontal synchronizing pulse is obtained for a while after the horizontal synchronizing pulse Pn of the input horizontal synchronizing signal P.

In this case as well, the output DT from the first discrimination circuit 9 becomes "0" as in FIG.
The carry output CR is the output horizontal synchronizing signal P' (Figure 5L
, see Figure 6). According to the present invention described above, the phase can be rapidly locked to the input horizontal synchronization signal, and even if the input horizontal synchronization signal has a large phase fluctuation or loss due to skew in a VTR, for example, the output horizontal synchronization can be maintained without loss. A that can get the signal
An FC circuit can be obtained.

[Brief explanation of the drawing]

Figure 1 is a system diagram showing one embodiment of the present invention, Figures 2 to 6
The figure is a time chart for explaining the operation. 1 is an input horizontal synchronizing signal input terminal, 2 is a first wind pulse generation circuit, 5 is a lock pulse generation circuit, 8 is a second wind pulse generation circuit, 9 and 10 are first and second discrimination circuits, 12 14 is an AND circuit as a second gate circuit; 20 is an output horizontal synchronization signal output terminal;
21 is a phase-locked loop (PLL), 24 is a phase comparison circuit, 25 is a charge pump, 26 is a low-pass filter, 27 is a variable frequency oscillator, 29 is a frequency division counter, 30 is a first gate circuit, 31 is a phase variation discrimination circuit,
35 is a decoder. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A variable frequency oscillator whose center frequency is N times the horizontal frequency, and whose output is 1/N
a frequency dividing counter which is cleared by the frequency divided output, and a phase comparison circuit which connects the signal having a predetermined phase relationship with the input horizontal synchronizing signal and the frequency divided output via a first gate circuit. and controls the oscillation frequency of the variable frequency oscillator based on the output of the phase comparison circuit, and also determines whether the phase fluctuation of the input horizontal synchronization signal exceeds a predetermined phase range, and if a phase fluctuation determination circuit that closes the first gate and opens the first gate when the first gate does not exceed the range; and a phase fluctuation determination circuit that determines whether the phase fluctuation of the input horizontal synchronization signal exceeds the predetermined range based on the output of the phase fluctuation determination circuit. and a second gate circuit that clears the frequency division counter by passing a lock pulse having a predetermined phase relationship with respect to the input horizontal synchronization signal, and outputs the carry output of the frequency division counter as the horizontal synchronization signal. An AFC circuit characterized in that, when the lock pulse is output from the second gate circuit, the lock pulse is used as the output horizontal synchronizing signal instead of the carry output of the frequency dividing counter.