JPH05167881A - Input signal error detecting circuit - Google Patents

Abstract

PURPOSE:To exactly detect whether or not an input signal exists and a data error from an inputted digital video signal. CONSTITUTION:A detecting circuit is provided with a synchronizing separator circuit 11 for separating a synchronizing signal (SYNC) and a reference signal (IDSIG) from an inputted digital video signal, a counter 12 and a decoder 13 for forming a separated signal and a regenerated pulse from one signal, and an error detecting circuit 14 for comparing the regenerated pulse and the other signal and detecting whether or not the signal exists and a data error. In such a way, even if an inputted signal noise, etc., are mixed in, whether or not the signal exists and the data error can be detected exactly and surely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal error detection circuit for detecting the presence or absence of a signal and the correctness of input data from an input digital video signal.

[0002]

2. Description of the Related Art Conventionally, as an apparatus for handling digital video signals, there is known a video switcher which detects an input signal from an input digital signal and switches a switch or the like. The above device is provided with a detection circuit as shown in FIG. 4, the input digital video signal is separated by the sync separation circuit 1 into the sync signal (SYNC), and the sync signal (SYNC) is integrated into the integration circuit 2. The presence or absence of the input signal required for switching is detected by integrating by.

[0003]

However, in the above-mentioned conventional detection circuit, there is no problem when accurate data as shown in FIG. 4A is input, but as shown in FIG. 4B. In addition, since it reacts to inaccurate input data in which noise or the like is mixed in the signal, there is a problem such as erroneously detecting the input data.

The present invention has been made in order to improve the above-mentioned inconvenience, and provides an input signal error detection circuit for detecting the presence or absence of a signal and the correctness of input data from an input digital video signal to provide an accurate input data. The purpose is to enable detection of.

[0005]

To achieve the above object, the present invention provides a sync separation circuit for separating a sync signal (SYNC) and a reference signal (IDSIG) from an input digital video signal, and a separated signal. And a counter and a decoder for forming a regenerated pulse from one of them, and the presence or absence of a signal and a data error are detected by comparing the regenerated pulse with the other signal.

[0006]

With the above structure, even if erroneous data such as noise is input to the input digital video signal, the presence or absence of the input signal and the data error can be reliably detected.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings shown in FIGS.

FIG. 1 is a block diagram of an input signal error detection circuit, FIG. 2 is a signal waveform diagram showing a signal processing process, and FIG. 3 is a concrete circuit diagram.

In FIG. 1, 11 is a sync separation circuit, which is shown in FIG.
(A) is input, the input video signal is separated into a sync signal (SYNC) and a reference signal (IDSIG), and the sync signal (SY) is input.
NC) to the counter 12 and to the reference signal (IDSI
G) is sent to the error detection circuit 14.

The synchronizing signal (SY) input to the counter 12
NC) is regenerated (signal reproduction) by the counter 12 and the decoder 13 at the next stage, and the regenerated pulse is output to the error detection circuit 14. Error detection circuit 14
Is the input regenerated pulse and sync separation circuit 11
The input sync signal (SYNC) is compared, the presence or absence of a signal or the correctness of input data is determined, and an error signal is output if there is an error.

FIG. 3 shows a specific example of the above circuit. In the circuit, DFF represents a D-type flip-flop, which is driven by a common clock signal.

Now, as shown in FIG. 2A, the reference signal (IDSI) is included in the range A to B in the synchronizing signal (SYNC) portion.
When the signal to which G) is added is input to the sync separation circuit 11, the DFF 15 and the AND gate 32 of the sync separation circuit 11 are input.
In FIG. 2B, the synchronization signal (SYNC) shown in FIG.
Is separated into a reference signal (d in FIG. 2) consisting of a pulse having a width W ₁ corresponding to the width between B and B, the synchronization signal (SYNC) is a counter reset pulse to the counter 12, and the reference signal (IDSIG) is an error detection signal. It is sent to the DFF 17 of the circuit 14.

A reference signal (ID
SIG) is inserted at a fixed position of the synchronizing signal (SYNC), and therefore, the position between A ′ and B ′ is also equal to the position between A and B. On the other hand, the counter 12 is reset by the synchronization signal (SYNC) input to the counter 12, the counter 12 starts counting, and the decoder 13 at the next stage
2e by reproducing the signal from the counter output.
The error detection circuit 1 that reproduces the generate pulse shown in
4 to DFF17.

Since the counter 12 is started by the edge of the sync signal (SYNC),
The relationship between the sync signal (SYNC) and the regenerate pulse is constant.

The regenerated pulse input to the DFF 17 of the error detection circuit 14 is compared with the reference signal (IDSIG) input from the sync separation circuit 11, and the DFF 17
The judgment result is output.

That is, when correct data is inserted in the digital video signal, a synchronization signal (SYNC)
A regenerate pulse synchronized with the output signal is output to the DFF 17, and the sync separation circuit 11 outputs the reference signal (IDSI).
Since G) is output, “H” with a signal is output from the output of the DFF 17.

Since there is no output from the sync separation circuit 11 when there is no signal, an asynchronous regenerate pulse is output from the decoder 13 to the DFF 17 and the reference signal (I
Since "DSIG) is not input," L "with no signal is output from the DFF 17, and it becomes possible to detect the presence or absence of a signal.

On the other hand, if erroneous data such as noise is input to the digital video signal, the synchronization signal (S
The relationship between YNC) and the reference signal (IDSIG) is not constant. Therefore, the positional relationship between the regenerated pulse output from the decoder 13 to the DFF 17 and the reference signal (IDSIG) is deviated, so that the output of the DFF 17 becomes "L", which enables error detection. ..

A synchronizing signal (SYNC) and a synchronizing signal (SYNC) are input from the digital video signal input as described above.
By extracting the reference signal (IDSIG) added to and comparing the two, the presence or absence of the input signal and the data error are detected, so that the presence or absence of the input signal and the data error can be accurately detected.

In the above embodiment, the sync signal (SYNC) is used.
Is sent to the counter 12 and the regenerator pulse is created by the decoder 13, but the reference signal (IDSIG) is sent to the counter 12 and the regenerate pulse is created by the decoder 13, and this is generated by the error detection circuit 14 by the synchronization signal (SYNC). Similar effects can be obtained by comparing with.

Further, by changing the width W ₁ of the reference signal (IDSIG), the jitter component in the video signal can be absorbed, and the regenerated pulse is generated not every horizontal cycle but every two horizontal cycles or every vertical cycle. If the output is output to, it is possible to add hysteris to the detection, so that a more stable detection result can be obtained.
Further, the reference signal (I) inserted in the synchronization signal (SYNC)
Even if there is no DSIG), the presence or absence of an input signal and the error can be detected by detecting the leading edge and the trailing edge of the synchronization signal (SYNC) and performing the same processing.

[0022]

As described above in detail, the present invention extracts the synchronizing signal and the reference signal from the input digital video signal, forms the regenerate pulse from one signal, and generates the regenerate pulse and the other signal. Since the presence or absence of an input signal and data error are detected by comparing the above, the presence or absence of an input signal can be detected accurately and stably, and incorrect data such as noise is mixed in the input signal. If so, this is detected as an error, so that incorrect data is not output and the reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an input signal error detection circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a processing process of an input signal error detection circuit according to an embodiment of the present invention.

FIG. 3 is a specific circuit diagram of an input signal error detection circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional input signal detection circuit.

[Explanation of symbols]

 11 sync separation circuit 12 counter 13 decoder 14 error detection circuit

Claims (1)

[Claims] 1. A sync separation circuit for separating a sync signal (SYNC) and a reference signal (IDSIG) from an input digital video signal, a counter and a decoder for forming a regenerate pulse from the separated signal, and a regenerator. An input signal error detection circuit comprising an error detection circuit that compares the rate pulse with the other signal to detect the presence or absence of a signal and a data error.