JPH11112833A - Horizontal synchronizing separator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide horizontal synchronizing signals not to be affected by the operation disturbance of AFC(automatic frequency control). SOLUTION: This circuit is provided with a synchronizing slice circuit 26, a masking circuit 28 and an AFC circuit 32, a switching circuit 54 is switched by switching signals prepared in a switching signal preparation circuit 52 and a first HD(horizontal synchronizing signal) outputted from the masking circuit 28 and a second HD outputted from the AFC circuit 32 are switched at each set period Ta and Tb. By setting the set periods Ta and Tb to a period when the operation of the AFC circuit 32 is disturbed and the period when the operation is stable, the first and second HDs are switched and outputted at each set period Ta and Tb. Thus, in the case of being incorporated in a video signal processing circuit, in the case that VTR signals are inputted as synthetic video signals, first HD signals are outputted in the period (set period Ta) when the operation of the AFC circuit 32 is disturbed by skewness in the VTR signals and the generation of adverse effects (a phenomenon that the upper part of a display screen is bent) by the operation disturbance of the AFC circuit 32 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog composite video signal (or composite video signal) such as a TV signal (video signal from a television broadcasting station) or a VTR signal (video signal from a video tape recorder). The present invention relates to a horizontal sync separation circuit for separating a horizontal sync signal from a horizontal sync signal.

[0002]

2. Description of the Related Art As a thin and lightweight display device,
A display device using a PDP (plasma display panel) or an LCD (liquid crystal display) panel has attracted attention. Such a display device is a direct drive system using a digitized input video signal. Therefore, when an analog composite video signal is input, a video signal processing circuit as shown in FIG. 12 is used.

That is, R (red), G (green), and B (blue) signals are created from the analog composite video signal input to the input terminal 12 by the analog video processing circuit 10, and the R, G, and B signals are An A / D (analog / digital) conversion circuit 14 converts the signals into digital R, G, and B signals, and inputs the signals to a digital video processing circuit 16. The HD signal (horizontal synchronization signal) and VD signal (vertical synchronization signal) separated from the input composite video signal by the synchronization separation circuit 18 are input to the digital video processing circuit 16 as timing signals. PL
The L (phase locked loop) circuit 20 creates a clock phase-synchronized with the HD signal and outputs the clock to the A / D conversion circuit 14 and the digital video processing circuit 16. For this reason, a video signal having a bit number corresponding to the PDP or the LCD panel is sent from the digital video processing circuit 16 to the display device 22, and a multi-tone image is displayed. For example, a multi-tone image is displayed by the sub-frame lighting method.

The horizontal sync separation circuit of the sync separation circuit 18 in FIG. 12 has conventionally been configured as shown in FIG. 13 or FIG. The horizontal sync separation circuit 24 shown in FIG.
Clamp / sync slice circuit 26 and masking circuit 2
8, the clamp / sync slice circuit 26
After fixing the level of the composite video signal input to the input terminal 12 to a constant level, the synchronous portion is sliced and
(A) is output, and the masking circuit 28 masks a certain masking period Tm from the falling edge of the composite sync signal to output an equalized pulse or a cutoff signal. FIG.
An HD signal as shown in (b) was output from the output terminal 29.

[0005] A horizontal sync separation circuit 30 shown in FIG.
Consists of a clamp / sync slice circuit 26, a masking circuit 28 and an AFC (automatic frequency control) circuit 32,
The AFC circuit 32 compares the phase with a comparison signal using the output signal of the masking circuit 28 as a reference signal, and outputs a signal (for example, a detection pulse) according to the phase difference.
4 and an LPF (low-pass filter) for smoothing and outputting the output signal (for example, output pulse) of the phase comparator 34
36, a VCO (Voltage Controlled Oscillator) 38 that changes and outputs a clock oscillation frequency Fo in accordance with the output voltage of the LPF 36, and divides the frequency of the clock output from the VCO 38 by 1 / n to generate an HD signal (frequency Fh) from the output terminal 39 and a frequency divider 40 for outputting the HD signal to the phase comparator 34 as a comparison signal. The following equation (1) holds between Fo, n, and Fh. Fo = Fh × n (1)

[0006] As shown in FIG.
A counter 42 for counting clocks output by O38,
An X count decoder 44 for decoding that the count value of the counter 42 becomes X (for example, X = n-1) corresponding to the frequency division ratio n of the frequency divider 40 and outputting a signal; A Y count decoder 46 for decoding that the count value has become Y (Y <X) and outputting a signal;
RS which uses the output signal of count decoder 44 as a set signal and the output signal of Y count decoder 46 as a reset signal
The output signal of the RS flip-flop 48 is used as an HD signal and a comparison signal to the phase comparator 34. The output signal of the X count decoder 44 is output as a CLR (clear) signal to the reset side of the counter 42 to reset the counter 42.

Assume that the clock (frequency Fo) output from the VCO 38 is as shown in FIG.
Assuming that the counting of clocks starts at time t1, the counted value becomes as shown in FIG. Therefore, the Y count decoder 46 outputs a pulse signal as shown in FIG. 17C every time the count value of the counter 42 becomes Y (each time t2, t4,...). Each time the count value of X becomes X (t3, t5,...), A pulse signal as shown in FIG. 4D is output, and the inverted Q output side of the RS flip-flop 48 outputs the same signal after t3. An HD signal as shown in FIG. 7E is output, and this HD signal is input to the phase comparator 34 as a comparison signal.
As shown in FIG. 17E, the HD signal is a pulse signal having an L level period of Tl and a period of Ts, and the masking circuit 28 is controlled by the frequency control operation of the AFC circuit 32.
Is a signal that is phase-synchronized with the signal output from.

[0008]

However, the horizontal sync separation circuit 24 shown in FIG. 13 has the following advantages and disadvantages. (1) Advantage: Since the synchronization timing of the input composite video signal is transmitted to the subsequent PLL circuit 20 as it is, this PL
The convergence operation of the L circuit 20 is accelerated, and when a signal whose S / N ratio (signal-to-noise ratio) is equal to or less than a set value (for example, a non-standard signal having an S / N ratio such as a VTR signal) is input, the PLL circuit 2
Operation of 0 is easily stabilized. (2) Disadvantage: Since only the HD signal is separated by clamping, slicing, and masking, a signal whose S / N ratio exceeds a set value (for example, a signal having a poor S / N ratio such as a TV signal of a weak electric field) ) Is input, noise tends to be mixed into the separated HD signal, and this noise is
The operation of the PLL circuit 20 is likely to be disturbed as a disturbance of the circuit 20.

The horizontal synchronization separation circuit 3 shown in FIG.
0 has the following advantages and disadvantages. (1) Advantages: Even when a signal (for example, a TV signal) whose S / N ratio exceeds a set value is input, noise is not mixed into the separated HD signal, and the PLL circuit 2 in the subsequent stage
0 is hardly disturbed. (2) Disadvantage: When a signal (for example, a VTR signal) whose S / N ratio is equal to or less than a set value is input, the operation of the AFC circuit 32 is disturbed by the skew of the HD signal always present in the VTR signal, Since the subsequent PLL circuit 20 converges after the frequency control operation converges, the convergence of the PLL circuit 20 is slowed down as a result, and adverse effects such as bending of the upper part of the display screen are likely to occur.
For example, a general-purpose VTR adopts an oblique scanning method,
The track of the head is switched for each vertical scan, and a phase delay or a phase advance occurs in a specific HD signal (for example, the HD signal 5H before the beginning of the VD signal) due to the head switching, and a display that displays the entire original image It is known that a skew phenomenon in which an upper portion is inclined obliquely appears on a display screen of a device (for example, a PDP display device).

The present invention has been made in view of the above-mentioned points, and has been described in connection with a horizontal synchronization separation circuit having a synchronization slice circuit, a masking circuit and an AFC circuit as shown in FIG. For example, skew)
Is input, a horizontal synchronizing signal is obtained from the output side of the masking circuit during the period when the operation of the AFC circuit is disturbed, and the AFC is performed during the period when the operation of the AFC circuit is stable. An object of the present invention is to obtain a horizontal synchronizing signal from the output side of the circuit and obtain a horizontal synchronizing signal which is not affected by disturbance of the operation of the AFC circuit. Therefore, when the horizontal sync separation circuit according to the present invention is incorporated in the video signal processing circuit of FIG. 121, a composite video signal (for example, VT) containing a component (for example, skew) that disturbs the operation of the AFC circuit.
When the (R signal) is input, it is possible to prevent an adverse effect (for example, a phenomenon that an upper portion of a display screen is bent) due to a disturbance in the operation of the AFC circuit.

[0011]

According to a first aspect of the present invention, there is provided a horizontal synchronizing separation circuit which slices a synchronizing portion of an input synthesized video signal and outputs a synthesized synchronizing signal; A masking circuit for masking a signal other than the horizontal synchronizing signal and outputting it as a first horizontal synchronizing signal; and an AFC circuit for generating a signal that is phase-synchronized with the first horizontal synchronizing signal by transmission frequency control and outputting the signal as a second horizontal synchronizing signal. , A switching signal generating circuit for generating a switching signal for switching for each of the set periods Ta and Tb, and a switching circuit for switching and outputting the first and second horizontal synchronizing signals by the switching signal.

The switching circuit is switched by the switching signal created by the switching signal creation circuit every set period Ta and Tb, so that the horizontal synchronizing signal output from the switching circuit is output from the masking circuit every set period Ta and Tb. Switching is made between the first horizontal synchronizing signal and the second horizontal synchronizing signal output from the AFC circuit. For this reason, the set periods Ta and Tb are
By setting the period during which the operation of the AFC circuit is disturbed and the period during which the operation of the AFC circuit is stable, the period during which the operation of the AFC circuit is disturbed (for example, the phase difference between the first and second horizontal synchronization signals exceeds the set value) During this period, the first horizontal synchronization signal output from the masking circuit is output as a horizontal synchronization signal,
A period during which the operation of the AFC circuit is stable (for example, first,
During the period when the phase difference of the second horizontal synchronization signal is equal to or less than the set value),
The second horizontal synchronization signal output from the AFC circuit can be output as a horizontal synchronization signal.

According to a second aspect of the present invention, in the first aspect of the invention, the AFC circuit is compared with the first horizontal synchronization signal output from the masking circuit as a reference signal so that a general-purpose circuit can be used as the AFC circuit. A phase comparator that compares a signal with a phase and outputs a signal corresponding to the phase difference, an LPF that smoothes and outputs an output signal of the phase comparator,
A VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF and outputs the same, and divides the frequency of the output clock of the VCO to create a second horizontal synchronizing signal. And a frequency divider that outputs the comparison signal to the phase comparator.

According to a third aspect of the present invention, there is provided a horizontal sync separation circuit for slicing a sync portion of an input synthesized video signal and outputting a synthesized sync signal, and masking a portion of the synthesized sync signal other than the horizontal sync signal. A masking circuit for processing and outputting as a first horizontal synchronization signal, and comparing the phase with a comparison signal using the first horizontal synchronization signal as a reference signal;
A phase comparator that outputs a signal corresponding to the phase difference, an LPF that smoothes and outputs an output signal of the phase comparator, and a VCO that changes and outputs a clock oscillation frequency according to an output voltage of the LPF. A switching signal generation circuit for generating a switching signal for switching for each of the setting periods Ta and Tb;
A frequency dividing / switching circuit for dividing the frequency of the output clock of O to generate a second horizontal synchronizing signal and for switching and outputting the first and second horizontal synchronizing signals with a switching signal; Characterized by

The frequency dividing / switching circuit divides the frequency of the output clock of the VCO to generate a second horizontal synchronizing signal, and uses the switching signal generated by the switching signal generating circuit to generate the first and second horizontal synchronizing signals. Is switched and output for each of the set periods Ta and Tb. Therefore, the set periods Ta and Tb are set to AF
The operation of the AFC circuit is disturbed by setting the period during which the operation of the C circuit (consisting of the phase comparator, the LPF, the VCO, and the dividing circuit unit of the frequency divider / switching circuit) is disturbed and the period during which the operation is stable. During the period, the first horizontal synchronizing signal can be output as the horizontal synchronizing signal, and during the period when the operation of the AFC circuit is stable, the second horizontal synchronizing signal can be output as the horizontal synchronizing signal.

According to a fourth aspect of the present invention, in order to simplify the circuit configuration of the frequency dividing / switching circuit, the frequency dividing / switching circuit includes a counter for counting a clock output from the VCO, An X count decoder that decodes that the count value of the counter has reached X corresponding to the frequency division ratio and outputs a signal, and decodes that the count value of the counter has reached Y (Y <X). , A Y-count decoder for detecting a falling edge or a rising edge of the first horizontal synchronizing signal, and a counter for switching the detection signal of the edge detection circuit and the output signal of the X-count decoder with a switching signal. And a RS flip-flop that uses the output signal of the switching circuit as a set signal and the output signal of the Y count decoder as a reset signal. The output signal of the RS flip-flop outputs a comparison signal to the phase comparator and outputting the results as a horizontal synchronizing signal.

According to a fifth aspect of the present invention, in order to simplify the configuration of the switching signal generating circuit, the vertical synchronizing signal is converted from the synthesized synchronizing signal output from the synchronizing slice circuit. A vertical sync separation circuit for separation is provided.
Based on the vertical synchronizing signal and the first horizontal synchronizing signal, the switching signal generating circuit sets a switching period T for a total period of one field period.
It is configured to generate a switching signal for switching for each of a and Tb.

A horizontal sync separation circuit according to a sixth aspect of the present invention includes a sync slice circuit for slicing a sync portion of an input synthesized video signal and outputting a synthesized sync signal, and a masking process for a synthesized sync signal other than the horizontal sync signal. A masking circuit that outputs a signal as a first horizontal synchronization signal, an AFC circuit that generates a signal that is phase-synchronized with the first horizontal synchronization signal by transmitting frequency control, and outputs the signal as a second horizontal synchronization signal; A lock / unlock detection circuit for outputting a lock / unlock detection signal based on whether or not the phase difference between the signals is equal to or less than a set value; and a first / second horizontal synchronization signal based on the lock / unlock detection signal. And a switching circuit for switching and outputting.

According to a lock / unlock detection signal corresponding to whether or not the phase difference between the first and second horizontal synchronization signals is equal to or less than a set value, the first horizontal synchronization signal output from the masking circuit and the second output from the AFC circuit. Switching to the horizontal synchronization signal. Therefore, during a period in which the phase difference between the first and second horizontal synchronization signals exceeds a set value (for example, a period during which the operation of the AFC circuit is disturbed), the first horizontal synchronization signal output from the masking circuit is horizontal. A period in which the phase difference between the first and second horizontal synchronization signals is less than or equal to a set value (for example,
During the period when the operation of the AFC circuit is stable), the second horizontal synchronization signal output from the AFC circuit is output as a horizontal synchronization signal.

According to a seventh aspect of the present invention, in the sixth aspect of the invention, the AFC circuit is compared with the first horizontal synchronization signal output from the masking circuit as a reference signal so that a general-purpose circuit can be used as the AFC circuit. A phase comparator that compares a signal with a phase and outputs a signal corresponding to the phase difference, an LPF that smoothes and outputs an output signal of the phase comparator,
A VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF and outputs the same, and divides the frequency of the output clock of the VCO to create a second horizontal synchronizing signal. And a frequency divider that outputs the comparison signal to the phase comparator.

The horizontal synchronizing separation circuit according to the eighth aspect of the present invention includes a synchronizing slice circuit for slicing a synchronizing portion of the input synthesized video signal and outputting a synthesized synchronizing signal, and masking the synthesized synchronizing signal other than the horizontal synchronizing signal. A masking circuit for processing and outputting as a first horizontal synchronization signal, and comparing the phase with a comparison signal using the first horizontal synchronization signal as a reference signal;
A phase comparator that outputs a signal corresponding to the phase difference, an LPF that smoothes and outputs an output signal of the phase comparator, and a VCO that changes and outputs a clock oscillation frequency according to an output voltage of the LPF. While dividing the frequency of the output clock of the VCO to create a second horizontal synchronizing signal,
A frequency dividing / switching circuit for switching and outputting the first and second horizontal synchronization signals, and outputting a lock / unlock detection signal based on whether or not the phase difference between the first and second horizontal synchronization signals is equal to or less than a set value. And a lock / unlock detection circuit for
The switching circuit switches and outputs the first and second horizontal synchronizing signals in response to a lock / unlock detection signal.

The frequency dividing / switching circuit divides the frequency of the output clock of the VCO to generate a second horizontal synchronizing signal, and generates the first and second signals based on the lock and unlock detection signals of the lock / unlock detection circuit. Two horizontal synchronization signals are switched and output. Therefore, during a period in which the phase difference between the first and second horizontal synchronization signals exceeds a set value (for example, a period during which the operation of the AFC circuit is disturbed), the first horizontal synchronization signal is output as a horizontal synchronization signal, The second horizontal synchronizing signal is output as a horizontal synchronizing signal during a period in which the phase difference between the first and second horizontal synchronizing signals is equal to or less than a set value (for example, a period during which the operation of the AFC circuit is stable).

According to a ninth aspect of the present invention, in order to simplify the configuration of the frequency dividing / switching circuit, the frequency dividing / switching circuit may be simplified.
The switching circuit includes a counter, an X count decoder, a Y count decoder, an edge detection circuit, a switching circuit, and an RS flip-flop. The output signal of the RS flip-flop is output as a horizontal synchronizing signal and is also output as a comparison signal to a phase comparator. Output.

According to a tenth aspect of the present invention, in the sixth, seventh, eighth or ninth aspect of the present invention, the lock / unlock detection circuit is provided with a second horizontal synchronization to simplify the configuration of the lock / unlock detection circuit. A gate pulse generation unit that generates a gate pulse in which a conduction period is set only for a set period Th including a rising edge (or a falling edge) of a signal, and using the gate pulse as a rising edge (or a falling edge) of the first horizontal synchronization signal A lock / unlock determination unit that latches and outputs the signal as a lock / unlock detection signal.

According to an eleventh aspect of the present invention, in order to simplify the configuration of the gate pulse generating section and the lock / unlock judging section, the gate pulse generating section includes a second edge detecting circuit, a counter, a count decoder, b
Consisting of a count decoder and an RS flip-flop,
A lock / unlock determination unit is provided with a first edge detection circuit and D
It is composed of flip-flops.

According to a twelfth aspect of the present invention, in the sixth, seventh, eighth or ninth aspect, the rising edge (or falling edge) of the first HD deviates even once from the GP set period Th (H level period). In order to reduce the possibility of erroneous determination based on the determination of sensitive lock and unlock, such as determining that the phase difference has exceeded the set value, a lock / unlock detection circuit includes a gate pulse generator, Outputs a lock detection signal when the lock / unlock determination section and the lock determination signal of the lock / unlock determination section continue multiple times, and outputs an unlock detection signal when the unlock determination signal continues multiple times. And a judgment result integrating unit.

According to a thirteenth aspect of the present invention, in the twelfth aspect of the present invention, the gate pulse generating section, the lock / unlock determining section and the determination result integrating section are provided with a second edge to simplify the configuration. It comprises a detection circuit, a counter, an a-count decoder, a b-count decoder, and an RS flip-flop.
An edge detection circuit and a D flip-flop are provided, and the determination result integration unit includes a first and a second gate circuit, a first and a second integration circuit, a c count decoder, a d count decoder, and an RS.
It is composed of a flip-flop.
The output signal of the flip-flop is used as a lock / unlock detection signal.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of a horizontal sync separation circuit according to the present invention, and the same parts as those in FIGS. In FIG. 1, 12 is an input terminal, 50 is a vertical sync separation circuit, 52 is a switching signal generation circuit, and 54 is a switching circuit. The input terminal 12 includes a clamp / sync slice circuit 26, a masking circuit 28,
An AFC circuit 32 is sequentially coupled, and the AFC circuit 32 includes a phase comparator 34, an LPF 36, a VCO 38, and a frequency divider 40.
It is composed of

The vertical synchronization separation circuit 50 is configured to separate a VD signal (vertical synchronization signal) from the combined synchronization signal output from the clamp / synchronization slice circuit 26 and output the VD signal (vertical synchronization signal).

The switching signal generation circuit 52 is a switching signal for switching every set period Ta, Tb based on the VD signal output from the vertical synchronization separation circuit 50 and the first HD signal output from the masking circuit 28. Is configured to be output. The set periods Ta and Tb are:
The preset period is set corresponding to a period during which the operation of the AFC circuit 32 is disturbed and a period during which the operation of the AFC circuit 32 is stable due to the skew of the horizontal synchronization signal that always exists in the VTR signal. In particular,
The sum of the set periods Ta and Tb is set to be equal to the vertical scanning period, and the set period Tb depends on set values M and N described later.

As shown in FIG. 2, the switching signal generation circuit 52 includes an edge detection circuit 56 for detecting a falling edge of the first HD signal, and an edge detection circuit for detecting a falling edge of the VD signal. A circuit 58, a counter 60 that counts detection pulses of the edge detection circuit 56 and is cleared by the detection pulse of the edge detection circuit 58,
An M count decoder 62 that decodes the count value of 0 to the set value M and outputs a signal, and decodes the count value of the counter 60 to the set value N (N <M) and outputs a signal. An N-count decoder 64 for outputting the signal and an RS flip-flop 66 for setting the output signal of the M-count decoder 62 as a set signal and the output signal of the N-count decoder 64 as a reset signal. It is configured to output as a switching signal. The set values M and N are determined such that the value of M−N corresponds to the set value Tb. The M and N count decoders 62 and 64 are not limited to this, but are configured such that the set values M and N can be rewritten by external control (for example, by manual operation).

The switching circuit 54 receives the first HD signal output from the masking circuit 28 and the frequency divider 40 of the AFC circuit 32 based on the switching signal output from the RS flip-flop 66 of the switching signal generation circuit 52. The second HD signal to be output is switched and output to the output terminal 68 as an HD signal (horizontal synchronization signal).

Next, the operation of FIG. 1 will be described with reference to FIGS. 2 and 3. For convenience of explanation, VT is caused by skew phenomenon.
Assuming that the horizontal scanning period of a specific horizontal synchronizing signal (for example, the horizontal synchronizing signal 5H before the beginning of the VD signal) included in the R signal changes (e.g., expands), the input terminal 12
Is expressed as shown in FIG. 3 (a).

(A) Clamp / synchronous slice circuit 26
After fixing the level of the VTR signal input to the input terminal 12 to a fixed level, the synchronous portion is sliced to output a composite synchronous signal, and the masking circuit 28 outputs the composite synchronous signal from the falling of the composite synchronous signal to the masking period Tm. During this time, an HD signal as shown in FIG. 3B is output as a first HD signal by masking the equalizing pulse and the cutting pulse. This first
In the HD signal, the horizontal scanning period of the signal portion corresponding to the skew phenomenon is extended as shown in FIG. The vertical sync separation circuit 50 converts the synthesized sync signal output from the clamp / sync slice circuit 26 into a V signal as shown in FIG.
The D signal is separated and output.

(B) In the AFC circuit 32, the phase comparator 3
4 uses the first HD signal output from the masking circuit 28 as a reference signal, compares the phase with the comparison signal, outputs a detection pulse corresponding to the phase difference, and the detection pulse is smoothed by the LPF 36, input to the VCO 38, and Oscillation frequency F
, the frequency divider 40 divides the frequency Fo of the clock output from the VCO 38 by 1 / n and outputs it as a second HD signal, and outputs the second HD signal to the phase comparator 34.
Is output as a comparison signal.

(C) The switching signal generation circuit 52 is shown in FIG.
A switching signal as shown in (1) is created and output. Next, FIG.
It will be described in detail with reference to FIG. The counter 60 operates when the VD signal falls (at time t1, time t4).
Each time,..., The detection pulse is cleared by the detection pulse of the edge detection circuit 58 and the counting of the detection pulse of the first HD signal output from the edge detection circuit 56 is started. The N count decoder 64 outputs an output signal (eg, H) every time the count value of the counter 60 reaches the set value N (at t2,...).
Level signal) is output to the reset terminal of the RS flip-flop 66, and the inverted Q output side of the RS flip-flop 66 is set to the H level. The M count decoder 62 outputs an output signal (for example, H) every time the count value of the counter 60 reaches the set value M (at t3,...).
Level signal) is output to the set terminal of the RS flip-flop 66, and the inverted Q output side of the RS flip-flop 66 is set to L level. Therefore, as shown in FIG. 3D, the switching signal signal output from the inverted Q output side of the RS flip-flop 66 is from t0 to t2, from t3 to t5 (not shown),.
Are set at L level, t2 to t3, t5 (not shown) to t6 (not shown),.
Becomes H level.

(D) The switching circuit 54, based on the switching signal from the RS flip-flop 66 of the switching signal generation circuit 52, as shown in FIG. 3 (e), outputs the first HD signal output from the masking circuit 28 and the AFC Divider 40 of circuit 32
And the second HD signal output from the
Output to Therefore, the skew phenomenon causes the AFC circuit 32
During the period in which the frequency control operation is disturbed (corresponding to the set period Ta), the switching signal becomes L level, the first HD signal output from the masking circuit 28 is output as an HD signal, and the frequency control operation of the AFC circuit 32 is stopped. During the period in which the operation converges and the operation is stable (corresponding to the set period Tb), the AFC
The second HD signal output from the frequency divider 40 of the circuit 32 is
Output as a signal. Therefore, when the horizontal sync separation circuit of FIG. 1 is incorporated in the video signal processing circuit of FIG. 12 and a VTR signal is input as a composite video signal, the horizontal skew of the horizontal sync signal that is always present in the VTR signal causes a bend at the top of the display screen. Can be prevented from occurring.

In the above-described embodiment, the case where the AFC circuit is constituted by the phase comparator, the LPF, the VCO and the frequency divider has been described. However, the present invention is not limited to this.
The C circuit may be any circuit that creates a signal that is phase-synchronized with the first HD signal output from the masking circuit by oscillation frequency control and outputs the signal as the second HD signal.

FIG. 4 shows a second embodiment of the horizontal sync separation circuit according to the present invention. The same parts as those in FIGS. 1, 15, and 16 are denoted by the same reference numerals, and detailed description of corresponding parts is omitted. . In FIG. 4, reference numeral 70 denotes a frequency dividing / switching circuit. The frequency dividing / switching circuit 70 includes a counter 42, an X count decoder 44, a Y count decoder 46, an RS flip-flop 48, a switching circuit 54a, and an edge detecting circuit 57. Have been.

The edge detection circuit 57 detects the falling edge of the first HD signal output from the masking circuit 28 and outputs an edge detection signal. The switching circuit 54a switches and outputs the detection signal of the edge detection circuit 57 and the output signal of the X count decoder 44 according to the switching signal from the switching signal generation circuit 52. Side and the RS flip-flop 48
Is connected to the set side. The Y count decoder 4
6 is coupled to the reset side of the RS flip-flop 48, and the inverted Q output of the RS flip-flop 48 is coupled to the comparison signal input of the phase comparator 34 and to the output terminal 68. I have.

Next, the operation of FIG. 4 will be described with reference to FIGS. 3, 5, and 17.
Will be described together. For convenience of explanation, the VTR signal input to the input terminal 12 is a signal as shown in FIG. 3A, a first HD signal output from the masking circuit 28, a VD signal output from the vertical sync separation circuit 50, and a switching signal generation circuit. Each of the switching signals output from 52 is shown in FIG.
Assume that (c) and (d).

(A) From time t2 to time t3 and time t5 in FIG.
A switching signal output from the switching signal generation circuit 52, such as from time t6 to time t6 (not shown),.
In (corresponding to the operation stabilization period of the AFC circuit), the switching circuit 54a is in the connection state shown by the dotted line in FIG.
Has the same function as the circuits shown in FIG. 15 and FIG. That is, the phase comparator 34, the LPF 36, and V
In the set period Tb during which the operation of the AFC circuit composed of the CO 38 and the frequency divider (consisting of the counter 42, the X count decoder 44, the Y count decoder 46, and the RS flip-flop 48) is stable, the RS flip-flop is used. As shown in FIG. 17 (e), the HD signal output from the inverted Q output side 48 to the output terminal 68 is a signal synchronized in phase with the first HD signal output from the masking circuit 28 by the frequency control action of the AFC circuit. Become.

(B) From t0 to t2 in FIG. 3D, t3
The switching signal output from the switching signal generation circuit 52 is set at an L level for a time period Ta from time to time t5 (not shown).
In the period (corresponding to the period during which the operation of the AFC circuit is disturbed), the switching circuit 54a is in the connection state shown by the solid line in FIG. 4, and the frequency dividing / switching circuit 70 operates as follows.

For convenience of explanation, the clock (frequency Fo) output from the VCO 38 is shown in FIG. 5A, the count value of the counter 42 is shown in FIG. 5B, and the first HD signal output from the masking circuit 28 is shown in FIG. It is assumed that it is shown in FIG. The Y count decoder 46 outputs a pulse signal as shown in FIG. 5C to the reset side of the RS flip-flop 48 every time the count value of the counter 42 becomes Y (t12, t14,...) And resets. And the X count decoder 4
6, the count value of the counter 42 becomes X (at t11, t
At 13:00, t15,...), A pulse signal as shown in FIG. 3D is output to the non-connection side (connection side indicated by a dotted line) of the switching circuit 54a. The edge detection circuit 57 detects the falling edge of the first HD signal and outputs an edge detection signal as shown in FIG. 5 (f), which is input to the reset side of the counter 42 via the switching circuit 54a. And reset, and input to the set side of the RS flip-flop 48 to set it. Therefore, after the time t11, the first HD as shown in FIG.
The first HDa signal is input to the phase comparator 34 as a comparison signal while the signal a is output. The horizontal scanning period of the first HD signal output from the masking circuit 28 changes (eg, expands) due to skew,
When the edge detection signal by the edge detection circuit 57 changes, a phase difference occurs between the first HD signal (reference signal) and the first HDa signal (comparison signal) input to the phase comparator 34, and the X count decoder 44 and Y Even if the output signal of the count decoder 46 changes, the output signal of the X count decoder 44 is cut off by the switching circuit 54a, so that the RS flip-flop 48 is not set. This R
Since the S flip-flop 48 is set by the edge detection signal of the first HD signal detected by the edge detection circuit 57, the first HDa signal output from the inverted Q output side of the RS flip-flop 48 is always in phase with the first HD signal. It becomes a synchronized signal. In addition, during the period when the operation of the AFC circuit is disturbed, the output signal of the Y count decoder 46 based on the automatic frequency control of the AFC circuit changes the Tl in the L level period, but the phase of the first HDa signal and the phase of the first HD signal are changed. Does not affect synchronization.

(C) Therefore, when the horizontal sync separation circuit of FIG. 4 is incorporated in the video signal processing circuit of FIG. 12 and a VTR signal is input as a composite video signal, the skew of the horizontal sync signal necessarily present in the VTR signal causes Bending can be prevented from occurring at the top of the display screen.

In the embodiment shown in FIG. 4, the frequency dividing / switching circuit is constituted by a counter, an X count decoder, a Y count decoder, an edge detecting circuit, a switching circuit and an RS flip-flop. Not limited,
What is necessary is just to generate the second horizontal synchronizing signal by dividing the frequency of the output clock of the VCO, and to switch and output the first and second horizontal synchronizing signals with the switching signal.

In the embodiment shown in FIGS. 1 and 4, a vertical synchronizing separation circuit is provided, and the switching signal generation circuit sets the sum to one vertical scanning period (one field) based on the vertical synchronizing signal and the first HD signal. Period), a switching signal for switching for each of the set periods Ta and Tb is created to simplify the configuration of the switching signal creation circuit. However, the present invention is not limited to this.
What is necessary is just to generate a switching signal for switching for each of the set periods Ta and Tb corresponding to a period during which the operation of the AFC circuit is disturbed and a period during which the operation is stable.

FIG. 6 shows a third embodiment of the horizontal synchronizing separation circuit according to the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. 6, 12 is an input terminal, 11 is a lock / unlock detection circuit, 54b
Is a switching circuit. The input terminal 12 has a clamp
The synchronous slice circuit 26, the masking circuit 28, and the AFC circuit 32 are sequentially coupled. The AFC circuit 32 includes a phase comparator 34, an LPF 36, a VCO 38, and a frequency divider 40.

The lock / unlock detection circuit 11
Based on whether the phase difference between the first HD signal output from the masking circuit 28 and the second HD signal output from the frequency divider 40 is equal to or smaller than a set value, a lock detection signal (for example, H
Level signal) and an unlock detection signal (for example, an L level signal). More specifically, the lock / unlock detection circuit 11 includes a gate pulse generation unit 13 and a lock / unlock determination unit 15, as shown in FIG.

The gate pulse generator 13 detects an edge of the second HD signal output from the frequency divider 40, detects the rising edge of the second HD signal, and uses the detection signal of the edge detector 17 as a clear signal to output the signal from the VCO 38. Counter 19 that counts the number of clocks (frequency Fo) to be performed, and the count value of the counter 19 is set values a and b (a and b are a <b.
a and b count decoders 21 and 23 that decode the fact that the integers satisfy b) and output signals, and the detection signals of the edge detection circuit 17 are used as clear signals, and the a and b count decoders 21 and 23 are used as the clear signals. And an RS flip-flop 25 that uses the output signal of the RS flip-flop 25 as a set signal and a reset signal. A GP (gate pulse) is output from the inverted Q output side of the RS flip-flop 25. The GP
Are the gate pulses in the conduction period only for the set period Th including the rising edge of the second HD signal, the set values a and b
Is set to a value corresponding to one or the other of the beginning and end of the set period Th.

The lock / unlock determination unit 15 detects the rising edge of the first HD signal output from the masking circuit 28, and the gate pulse generation unit 1 based on the detection signal of the edge detection circuit 27.
And a D flip-flop (D-type flip-flop) 31 for latching the GP output from the D flip-flop 3. The Q output of the D flip-flop 31 is output as a lock / unlock detection signal.

The switching circuit 54 b outputs a first HD signal output from the masking circuit 28 and a second HD signal output from the frequency divider 40 according to a lock / unlock detection signal output from the lock / unlock determination unit 15. 2HD
A signal is switched and output to the output terminal 68.

Next, the operation of FIG. 6 will be described with reference to FIGS. 7 and 8. For the sake of convenience of description, a component (for example, a change in the horizontal scanning period of the HD signal 5H before the beginning of the VD signal due to a skew phenomenon) which causes synchronization disturbance included in the composite video signal (for example, the VTR signal) input to the input terminal 12 )
8A, the rising edge of the first HD signal output from the masking circuit 28 is at t1, as shown in FIGS.
At times t2, t4, t6 and t7, the frequency divider 4
(C) in the same figure when the second HD signal output from 0 rises.
As shown in (d), t1, t2, t3 (t2 <t3 <t
4), t5 (t4 <t5 <t6), and t7. That is, the first and second Hs between the times t2 and t7.
It is assumed that the phase difference of the D signal exceeds the set value, and the AFC circuit 32 enters the frequency control operation and the operation is disturbed.

(A) The gate pulse generator 13 operates as follows. The counter 19 has t1, t as shown in FIG.
At 2, t3, t5, and t7, the clock is cleared by the edge detection signal output from the edge detection circuit 17 and the clock output from the VCO 38 is counted, so that a count value as shown in FIG. The a-count decoder 21 outputs a decode signal as shown in FIG. 8 (f) every time the count value becomes a, and the b-count decoder 23 shows a decode signal as shown in FIG. 8 (g) every time the count value becomes b. Output such a decoded signal. The RS flip-flop 25 is cleared by the detection signal output from the edge detection circuit 17,
Since they are set and reset by the decode signals of the a and b count decoders 21 and 23, the signals are output from the inverted Q output side as shown in FIG.
GP is output as shown in (h). The set values a and b of the a and b count decoders 21 and 23 correspond to the GP conduction period T.
h (H level period) corresponds to the end and the beginning.

(B) The lock / unlock determination section 15 operates as follows. The D flip-flop 31 latches the GP output from the RS flip-flop 25 of the gate pulse generation unit 13 by an edge detection signal output from the edge detection circuit 27 as shown in FIG. The lock / unlock detection signal shown in FIG. That is, the level of the GP latched by the edge detection signals at the times t1 and t2 is H level, t4 and t6.
Since the level of the GP latched by the edge detection signal at the time is L level and the level of the GP latched by the edge detection signal at the time t7 is H level, the lock is performed at t4 when the phase difference between the first and second HD signals exceeds the set value. The detection signal changes to an unlock detection signal, and the unlock detection signal changes to the lock detection signal at t7 when the phase difference between the first and second HD signals becomes equal to or less than a set value (in the figure, the phase difference is synchronized with 0). .

(C) The switching circuit 54b outputs the first H output from the masking circuit 28 in response to the lock / unlock detection signal output from the lock / unlock determination unit 15.
The D signal and the second HD signal output from the frequency divider 40 are switched and output to the output terminal 68. Therefore, the horizontal sync separation circuit of FIG. 6 is incorporated in the video signal processing circuit of FIG. 11, and the synthesized video signal (for example, VT
The phase difference between the first and second HD signals exceeds a set value due to a component (for example, a component that causes a skew phenomenon) included in the R signal) that causes synchronization disturbance, and the AFC circuit 32 enters a frequency control operation. Even when the operation is disturbed, the first HD signal is output as the horizontal synchronization signal during the period when the operation is disturbed, and the second HD signal is output during the period when the operation is stable.
Since the signal is output as a horizontal synchronizing signal, a defect on the display screen due to a component causing a synchronization disturbance included in the composite video signal (for example, a defect such as a bending of the upper part of the display screen due to a skew phenomenon) occurs. It can be prevented from occurring. When a composite video signal (for example, a TV signal) that does not disturb the operation of the AFC circuit 32 is input to the input terminal 12, the output of the lock / unlock detection circuit 11 is always a lock detection signal. , Switching circuit 54b
Is in the connection state indicated by the dotted line, and the second HD signal is always output from the output terminal 68 as a horizontal synchronization signal.

In the embodiment of FIG. 6, the case where the AFC circuit is constituted by the phase comparator, the LPF, the VCO and the frequency divider has been described. However, the present invention is not limited to this.
The FC circuit creates a signal that is phase-synchronized with the first HD signal output from the masking circuit by controlling the oscillation frequency,
What is necessary is just to output as a 2nd HD signal.

FIG. 9 shows a fourth embodiment of the horizontal synchronizing separation circuit according to the present invention. The same parts as those in FIGS. 4 and 6 are designated by the same reference numerals, and the detailed description of the corresponding parts is omitted. FIG.
In the figure, 70a is a frequency dividing / switching circuit, and this frequency dividing / switching circuit 70a
4, Y count decoder 46, RS flip-flop 4
8, the switching circuit 54c and the edge detection circuit 57.

The switching circuit 54c switches and outputs the detection signal of the edge detection circuit 57 and the output signal of the X count decoder 44 according to the lock / unlock detection signal of the lock / unlock detection circuit 11. Its output is coupled to the reset side of the counter 42 and to the set side of the RS flip-flop 48. The output side of the Y count decoder 46 is connected to the reset side of the RS flip-flop 48, the inverted Q output side of the RS flip-flop 48 is connected to the comparison signal input side of the phase comparator 34, and the output terminal 68 Is bound to.

The lock / unlock detection circuit 11
6, the first HD signal output from the masking circuit 28 and the decode signal (corresponding to the second HD signal in FIG. 6) output from the X count decoder 44 of the frequency dividing / switching circuit 70a, as in the embodiment of FIG. A lock detection signal (for example, an H level signal) and an unlock detection signal (for example, an L level signal) are output based on whether the phase difference is equal to or less than a set value, and the switching circuit 54c is shown by a solid line and a dotted line. It is configured to switch to the connection side.

When the phase difference is equal to or less than the set value and the switching circuit 54c is connected to the connection side indicated by the dotted line by the lock detection signal (during the period when the operation of the AFC circuit is stable), the switching circuit 54c is switched to the state shown in FIG. The connection state is indicated by a dotted line inside, and has the same function as the circuits shown in FIGS. 15 and 16. That is, the phase comparator 34, LPF 36, VC
The operation of the AFC circuit composed of O38 and the frequency divider (consisting of the counter 42, the X count decoder 44, the Y count decoder 46, and the RS flip-flop 48) is stabilized, and from the inverted Q output side of the RS flip-flop 48 The HD signal to be output is, as shown in FIG.
Due to the frequency control action of the circuit, the signal is phase-synchronized with the first HD signal output from the masking circuit 28.

When the phase difference exceeds the set value and the switching circuit 54c is connected to the connection side indicated by the solid line by the unlock detection signal (when the operation of the AFC circuit is disturbed), FIGS. It operates in the same way as the example shown by. That is, the horizontal synchronization signal output from the output terminal 68 is
Similarly to the signal shown in (g), the first HDa signal is phase-synchronized with the first HD signal. In this case, the phase comparator 34
4. Even if the phase difference occurs between the first HD signal (reference signal) and the first HDa signal (comparison signal) input to the X and the output signals of the X count decoder 44 and the Y count decoder 46 change, the embodiment of FIG. Similarly to the above, since the RS flip-flop 48 is set by the edge detection signal of the first HD signal, the first HDa signal output from the inverted Q output side of the RS flip-flop 48 is always a signal whose phase is synchronized with the first HD signal. . When a composite video signal (for example, a TV signal) that does not disturb the operation of the AFC circuit is input to the input terminal 12, the output of the lock / unlock detection circuit 11 is always a lock detection signal. Switching circuit 5
4c is in the connection state indicated by the dotted line, and the second HD signal is always output from the output terminal 68 as a horizontal synchronization signal.

In the embodiment shown in FIG. 9, the frequency dividing / switching circuit is constituted by a counter, an X count decoder, a Y count decoder, an edge detecting circuit, a switching circuit and an RS flip-flop. Not limited,
What is necessary is just to generate the second horizontal synchronizing signal by dividing the frequency of the output clock of the VCO, and to switch and output the first and second horizontal synchronizing signals with the switching signal.

In the embodiment shown in FIGS. 6 and 9, in order to simplify the configurations of the gate pulse generation unit and the lock / unlock determination unit, the gate pulse generation unit includes a second edge detection circuit, a counter, a , B count decoder and RS flip-flop, and the lock / unlock determination unit is configured with the first edge detection circuit and D flip-flop. However, the present invention is not limited to this. The lock / unlock determination unit outputs the gate pulse generated by the gate pulse generation unit to the rising edge of the first HD signal for a set period Th including the rising edge (or falling edge) of the 2HD signal. (Or a falling edge) and output as a lock / unlock detection signal.

In the embodiment shown in FIGS. 6 and 9, in order to simplify the structure of the lock / unlock detection circuit,
Although the case where the lock / unlock detection circuit is constituted by the gate pulse generation unit and the lock / unlock determination unit has been described, the present invention is not limited to this, and the first HD signal output from the masking circuit and the frequency divider ( Alternatively, a lock / unlock detection signal may be output based on whether or not a phase difference from a comparison signal (for example, a second HD signal) output from a frequency dividing / switching circuit is equal to or smaller than a set value.

For example, as shown in FIG. 10, the present invention is also used when the lock / unlock detection circuit 11a is composed of the gate pulse generation unit 13, the lock / unlock determination unit 15, and the determination result accumulation unit 41. can do. With such a configuration, it is possible to reduce the possibility that an erroneous determination based on the determination of the sensitive lock or unlock occurs. For example, for unlock detection, the first HD is G
If the phase deviates even once from the set period Th (H level period) of P, it is not determined that the phase difference with the comparison signal (for example, the second HD signal) has exceeded the set value, but a plurality of preset unlocks have occurred. First, an unlock detection signal is output. The details will be described below.

The judgment result integrating section 41 includes first and second gate circuits 43 and 45, first and second integrating counters 47 and 4.
It comprises 9, c and d count decoders 51 and 53, first and second inverting circuits 61 and 63, and an RS flip-flop 65.

The first gate circuit 43 uses the inverted Q output of the D flip-flop 31 as a gate signal to determine whether or not to pass an edge detection signal of the edge detection circuit 27 (a signal detecting a rising edge of the first HD signal). Decide, the second
The gate circuit 45 is configured to determine whether to pass the edge detection signal of the edge detection circuit 27 using the Q output of the D flip-flop 31 as a gate signal.
Therefore, when one of the first and second gate circuits 43 and 45 passes the edge detection signal of the first HD signal,
This means that the other is blocking the edge detection signal of the first HD signal.

The first and second integrating counters 47 and 49
Are cleared by the output signals of the second and first inverting circuits 63 and 61, and the first and second gate circuits 43 and 45 are cleared.
Of the c and d count decoder 5
Numerals 1 and 53 indicate that the count values of the first and second integrating counters 47 and 49 are set values c and d (c and d are integers of 2 or more, c = d
), And outputs a signal. The first and second inverting circuits 61 and 63 output the signals c and d.
The signals obtained by inverting the output signals of the count decoders 51 and 53 are used as a clear signal as the second and first integration counters 49 and 53.
47. The RS flip-flop 65 is configured to output the output signal of the c count decoder 51 as a set signal, output the signal of the d count decoder 53 as a reset signal, and output the inverted Q signal as a lock / unlock detection signal. Have been.

Next, the operation of the lock / unlock detection circuit 11a of FIG. 10 will be described with reference to FIG. For convenience of explanation, as shown in FIGS.
It is assumed that the phase of the HD signal matches the phase of the comparison signal (for example, the second HD signal), and the output of the first inverting circuit 61 clears the second integration counter 49 immediately before time t1. (A) As in the case of FIG. 7, the edge detection circuit 27,
17 outputs an edge detection signal as shown in FIGS.
From the inverted Q output side of the RS flip-flop 25 outputs a GP as shown in FIG. At time t1, the output time of the edge detection signal is the conduction time Th of the GP.
Since it is within the (H-level period), an H-level signal (lock determination signal) is output from the Q output side of the D flip-flop 31 of the lock / unlock determination unit 15 as shown in FIG. In the case of FIG. 7, this H level signal (lock determination signal) is output to the switching circuit as a lock detection signal. In the case of FIG. 10, however, it is output to the switching circuit via the determination result integrating unit 41. When an H level signal (lock determination signal) is output from the Q output side of the D flip-flop 31, the second
Since the gate circuit 45 passes the edge detection signal in the conductive state, the count value of the second integrating counter 49 at time t1 becomes 1.

(B) Assuming that the state in which the phase difference between the first HD signal and the comparison signal is equal to or less than the set value continues and the count value of the second integrating counter 49 reaches the set value d at t2, the d count decoder 53 11 changes from L level to H level as shown in FIG. 11 (j), and a lock detection signal (H level signal) as shown in FIG. 11 (k) is output from the inverted Q output side of the RS flip-flop 65. I do.

(C) The cause of the disturbance of the operation of the AFC circuit (for example, the skew of the horizontal synchronizing signal in the VTR signal)
Assuming that the phase difference between the first HD signal and the comparison signal exceeds the set value immediately before time t3, as shown in FIGS. 11 (b) and 11 (c), the edge detection signal is output during the GP conduction period Th.
(H level period), the Q output of the D flip-flop 31 changes from H level to L level at t3, and the second gate circuit 45 is turned off. On the other hand, an H level signal (lock determination signal) is output from the inverted Q output side of the D flip-flop 31 to make the first gate circuit 43 conductive and pass the edge detection signal. d at t3
The output of the count decoder is L as shown in FIG.
Since the level changes to a level and the first integration counter 47 is reset, the first integration counter 47 starts counting the edge detection signal that has made the first gate circuit 43 conductive.

(D) If the phase difference between the first HD signal and the comparison signal continues to exceed the set value and the count value of the first integrating counter 47 reaches the set value c at t4, the c count decoder 11 (i) changes from the L level to the H level as shown in FIG. 11 (i), and from the inverted Q output side of the RS flip-flop 65, an unlock detection signal (L level signal) as shown in FIG. 11 (k). Output.

(E) At time t5 when one horizontal scanning period (1H) of the first HD signal has elapsed from time t4, the output side of the c count decoder 51 changes to L level, and the set side of the RS flip-flop 65 is set to L level. , Until the H level signal is input to the reset side of the RS flip-flop 65. Further, when the output side of the c count decoder 51 changes to L level at t5, this L level signal clears the second integration counter 49 via the first inversion circuit 61, and waits for the input of the lock determination signal.

[0075]

According to the first aspect of the present invention, there is provided a horizontal sync separation circuit comprising a sync slice circuit, a masking circuit, an AFC circuit,
A switching signal generation circuit and a switching circuit, wherein the switching circuit is set by the switching signal generated by the switching signal generation circuit for a set period T.
The horizontal synchronization signal output from the switching circuit is switched between the first horizontal synchronization signal output from the masking circuit and the second horizontal synchronization signal output from the AFC circuit for each of the set periods Ta and Tb. Configured. Therefore, by setting the set periods Ta and Tb corresponding to the period during which the operation of the AFC circuit is disturbed and the period during which the operation is stable, the period during which the operation of the AFC circuit is disturbed (for example, the first and the second). During the period when the phase difference of the second horizontal synchronization signal exceeds the set value, the first horizontal synchronization signal output from the masking circuit is output as the horizontal synchronization signal, and the operation of the AFC circuit is stable (for example, during the period). , The second horizontal synchronizing signal output from the AFC circuit can be output as a horizontal synchronizing signal during the period when the phase difference between the first and second horizontal synchronizing signals is equal to or less than the set value. Therefore, when the horizontal sync separation circuit according to the present invention is incorporated in the video signal processing circuit of FIG. 12, when a composite video signal (for example, a VTR signal) including a component (for example, skew) that disrupts the operation of the AFC circuit is input. In addition, it is possible to prevent an adverse effect due to unstable operation of the AFC circuit (a phenomenon in which an upper portion of a display screen is bent).

According to a second aspect of the present invention, since the AFC circuit in the first aspect of the present invention includes a phase comparator, an LPF, a VCO, and a frequency divider, a general-purpose circuit can be used as the AFC circuit.

The horizontal sync separation circuit according to the third aspect of the present invention comprises a sync slice circuit, a masking circuit, a phase comparator,
An LPF, a VCO, a switching signal generating circuit, and a frequency dividing / switching circuit are provided. The frequency dividing / switching circuit divides a frequency of an output clock of the VCO to generate a second horizontal synchronizing signal and generate a switching signal. The first and second horizontal synchronizing signals are switched and output for each of the set periods Ta and Tb by a switching signal generated by the circuit. Therefore, the setting period Ta
And Tb are set in accordance with a period during which the operation of the AFC circuit (including a phase comparator, an LPF, a VCO, and a frequency dividing circuit unit of a frequency dividing / switching circuit) is disturbed and a period during which the operation is stable. During a period in which the operation of the AFC circuit is disturbed (for example, a period in which the phase difference between the first and second horizontal synchronization signals exceeds a set value), the first horizontal synchronization signal is output as a horizontal synchronization signal, During the period when the operation of the circuit is stable,
The second horizontal synchronization signal can be output as a horizontal synchronization signal. Therefore, when incorporated in the video signal processing circuit,
When a composite video signal (for example, VTR signal) including a component (for example, skew) that disturbs the operation of the AFC circuit is input,
It is possible to prevent adverse effects due to unstable operation of the AFC circuit (a phenomenon that the upper part of the display screen is bent).

According to a fourth aspect of the present invention, in the third aspect, the frequency dividing / switching circuit comprises a counter, an X count decoder, a Y count decoder, an edge detection circuit, a switching circuit, and an RS flip-flop. Since the output signal of the flip-flop is output as a horizontal synchronization signal and output as a comparison signal to the phase comparator, the circuit configuration of the frequency dividing / switching circuit can be simplified.

According to a fifth aspect of the present invention, in the first, second, third or fourth aspect of the present invention, there is provided a vertical synchronizing separation circuit for separating a vertical synchronizing signal from a synthesized synchronizing signal outputted from the synchronizing slice circuit, Is generated based on the vertical synchronizing signal and the first horizontal synchronizing signal so as to generate a switching signal for switching every set period Ta or Tb in which the sum is one field period. Can be easily done.

The horizontal sync separation circuit according to the present invention comprises a sync slice circuit, a masking circuit, an AFC circuit,
A lock / unlock detection circuit and a switching circuit, and a first horizontal output from the masking circuit based on a lock / unlock detection signal corresponding to whether or not the phase difference between the first and second horizontal synchronization signals is equal to or smaller than a set value. The synchronous signal and the second horizontal synchronous signal output from the frequency divider are switched and output. Therefore, during a period in which the phase difference between the first and second horizontal synchronization signals exceeds a set value (for example, a period during which the operation of the AFC circuit is disturbed), the first horizontal synchronization signal output from the masking circuit is horizontal. A period in which the phase difference between the first and second horizontal synchronization signals is less than or equal to a set value (for example,
During the period when the operation of the AFC circuit is stable), the second horizontal synchronization signal output from the AFC circuit is output as a horizontal synchronization signal. Therefore, when incorporated in a video signal processing circuit, when a composite video signal (for example, a VTR signal) containing a component (for example, a skew) that disturbs the operation of the AFC circuit is input, adverse effects due to the unstable operation of the AFC circuit may occur. Can be prevented.

According to a seventh aspect of the present invention, in the sixth aspect, the AFC circuit includes a phase comparator, an LPF, a VCO, and a frequency divider, so that a general-purpose circuit can be used as the AFC circuit.

The horizontal sync separation circuit according to the eighth aspect of the present invention comprises a sync slice circuit, a masking circuit, a phase comparator,
An LPF, a VCO, a frequency dividing / switching circuit, and a lock / unlock detecting circuit. The frequency dividing / switching circuit divides the frequency of the output clock of the VCO to generate a second horizontal synchronizing signal, and・ Locking of unlock detection circuit,
The first and second horizontal synchronization signals are switched and output according to the unlock detection signal. Therefore, the first,
During the period when the phase difference of the second horizontal synchronization signal exceeds the set value (for example, during the period when the operation of the AFC circuit is disturbed),
A first horizontal synchronizing signal is output as a horizontal synchronizing signal,
During the period when the phase difference of the second horizontal synchronization signal is equal to or less than the set value (for example, during the period when the operation of the AFC circuit is stable), the second
The horizontal synchronization signal is output as a horizontal synchronization signal. Therefore, when incorporated in a video signal processing circuit, when a composite video signal (for example, a VTR signal) containing a component (for example, a skew) that disturbs the operation of the AFC circuit is input, adverse effects due to the unstable operation of the AFC circuit may occur. Can be prevented.

According to a ninth aspect of the present invention, in the invention of the eighth aspect, the frequency dividing / switching circuit comprises a counter, an X count decoder, a Y count decoder, an edge detection circuit, a switching circuit, and an RS flip-flop. Since the configuration is such that the output signal of the flip-flop is output as a horizontal synchronizing signal and output as a comparison signal to the phase comparator, the configuration of the frequency dividing / switching circuit can be simplified.

According to a tenth aspect, in the sixth, seventh, eighth, or ninth aspect, the lock / unlock detection circuit comprises:
Rising edge (or falling edge) of the second horizontal synchronization signal
And a gate pulse generation unit that generates a gate pulse that is turned on only for the set period Th, and latches the gate pulse at the rising edge (or falling edge) of the first horizontal synchronization signal to generate a lock / unlock detection signal. It consists of a lock / unlock judgment unit that outputs
The configuration of the unlock detection circuit can be simplified.

According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, the gate pulse generator comprises a second edge detecting circuit, a counter, an a-count decoder, a b-count decoder and an RS flip-flop, and a lock / unlock determination is made. Since the unit is configured by the first edge detection circuit and the D flip-flop, the configurations of the gate pulse generation unit and the lock / unlock determination unit can be simplified.

According to a twelfth aspect of the present invention, in the sixth, seventh, eighth or ninth aspect of the present invention, the lock / unlock detection circuit comprises:
A gate pulse generation unit, a lock / unlock determination unit,
The lock / unlock determination section comprises a lock detection signal when the lock determination signal continues for a plurality of times, and a determination result integrating section for outputting an unlock detection signal when the unlock determination signal continues for a plurality of times. Therefore, it is possible to avoid an overly sensitive determination such as immediately determining unlock when the phase difference between the first HD signal and the comparison signal (for example, the second HD signal) exceeds the set value.

According to a thirteenth aspect of the present invention, in the twelfth aspect of the present invention, the gate pulse generator is provided with a second edge detecting circuit,
A lock / unlock determination unit is configured with a first edge detection circuit and a D flip-flop, and a determination result integration unit is configured with a first and a second gate circuit. , A first integration circuit, a second integration circuit, a c-count decoder, a d-count decoder, and an RS flip-flop.
Since the unlock detection signal is used, the configurations of the gate pulse generation unit, the lock / unlock determination unit, and the determination result integration unit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a horizontal sync separation circuit according to the present invention.

FIG. 2 is a block diagram illustrating a specific example of a switching signal generation circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIGS. 1 and 2;

FIG. 4 is a block diagram showing a second embodiment of the horizontal sync separation circuit according to the present invention.

FIG. 5 is a timing chart for explaining the operation of FIG. 4;

FIG. 6 is a block diagram showing a third embodiment of the horizontal sync separation circuit according to the present invention.

FIG. 7 is a block diagram showing a specific example of a lock / unlock detection circuit in FIG. 6;

FIG. 8 is a timing chart for explaining the operation of FIG. 7;

FIG. 9 is a block diagram showing a fourth embodiment of the horizontal sync separation circuit according to the present invention.

FIG. 10 is a block diagram showing another specific example of the lock / unlock detection circuit in FIG. 6 or 7;

FIG. 11 is a timing chart for explaining the operation of FIG. 10;

FIG. 12 is a block diagram showing a video signal processing circuit which receives a composite video signal and uses a display device such as a PDP display device or an LCD display device as an output device.

FIG. 13 is a block diagram showing a conventional example of a horizontal synchronization separation circuit provided in the synchronization separation circuit in FIG.

FIG. 14 is a waveform diagram illustrating the operation of FIG.

FIG. 15 is a block diagram showing another conventional example of the horizontal sync separation circuit provided in the sync separation circuit in FIG.

16 is a block diagram illustrating an example of a frequency divider in FIG.

FIG. 17 is a timing chart for explaining the operation of FIG. 16;

[Explanation of symbols]

Reference Signs List 10: analog video processing circuit, 11, 11a: lock / unlock detection circuit, 12: input terminal, 13: gate pulse generator, 14: A / D (analog / digital) conversion circuit, 15: lock / unlock determination Department,
16 Digital video processing circuit 17, 27, 57
... edge detection circuit, 18 ... synchronization separation circuit, 19 ... counter, 20 ... PLL circuit, 21,23,44,4
6, 51, 53: Count decoder, 22: Display device, 24, 30: Horizontal sync separation circuit, 25, 48,
65… RS (reset / set) flip-flop,
26: clamp / synchronous slice circuit, 28: masking circuit, 29, 39, 68: output terminal, 32: AF
C (automatic frequency control) circuit, 34 ... phase comparator, 36
... LPF (Low Pass Filter), 38 ... VCO (Voltage Controlled Oscillator), 40 ... Divider, 42 ... Counter,
43: first gate circuit, 45: second gate circuit, 4
7, 49: integrating counter, 61, 63: inverting circuit,
First HD signal: First horizontal synchronization signal.

Claims (13)

[Claims] 1. A synchronizing slice circuit for slicing a synchronizing portion of an input synthesized video signal and outputting a synthesized synchronizing signal, and masking a portion of the synthesized synchronizing signal other than a horizontal synchronizing signal to form a first horizontal synchronizing signal. A masking circuit for outputting, a AFC circuit for generating a signal synchronized in phase with the first horizontal synchronizing signal by transmission frequency control and outputting the signal as a second horizontal synchronizing signal, and a switching signal for switching every set period Ta, Tb. A horizontal synchronization separation circuit comprising: a switching signal generation circuit to be generated; and a switching circuit that switches and outputs the first and second horizontal synchronization signals according to the switching signal. 2. An AFC circuit comprising: a phase comparator for comparing a phase with a comparison signal using a first horizontal synchronization signal output from a masking circuit as a reference signal, and outputting a signal corresponding to a phase difference;
LPF for smoothing and outputting the output signal of this phase comparator
And a VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF and outputs the frequency. The frequency of the output clock of the VCO is divided and output as a comparison signal to the phase comparator. 2. The horizontal synchronization separation circuit according to claim 1, further comprising a frequency divider that outputs the second horizontal synchronization signal. 3. A synchronizing slice circuit for slicing a synchronizing portion of an input synthesized video signal and outputting a synthesized synchronizing signal, and masking a portion of the synthesized synchronizing signal other than the horizontal synchronizing signal to produce a first horizontal synchronizing signal. A masking circuit for outputting, a phase comparator for comparing a phase with a comparison signal using the first horizontal synchronization signal as a reference signal, and outputting a signal corresponding to the phase difference; LPF, a VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF, and outputs the VCO.
A switching signal generation circuit for generating a switching signal for switching every Tb; a second horizontal synchronization signal generated by dividing the frequency of the output clock of the VCO; A horizontal sync separation circuit comprising a frequency dividing / switching circuit for switching and outputting a horizontal sync signal. 4. A frequency dividing / switching circuit, comprising: a counter for counting a clock output from a VCO; and an X count for decoding the fact that the count value of the counter has reached X corresponding to the frequency dividing ratio and outputting a signal. A decoder, a Y count decoder for decoding that the count value of the counter becomes Y (Y <X) and outputting a signal, and an edge detecting circuit for detecting a falling or rising edge of the first horizontal synchronization signal A switching circuit for switching a detection signal of the edge detection circuit and an output signal of the X count decoder by a switching signal and outputting the signal to the reset side of the counter; a set signal for the output signal of the switching circuit; And an RS flip-flop that uses the output signal of
4. The horizontal synchronizing separation circuit according to claim 3, wherein an output signal of the S flip-flop is output as a horizontal synchronizing signal and is output as a comparison signal to a phase comparator. 5. A vertical synchronizing separation circuit for separating a vertical synchronizing signal from a composite synchronizing signal output from a synchronizing slice circuit, wherein a switching signal generating circuit performs a sum based on the vertical synchronizing signal and a first horizontal synchronizing signal. 5. The horizontal sync separation circuit according to claim 1, wherein a switching signal is generated for switching every set period Ta, Tb during which one field period is set. 6. A synchronizing slice circuit for slicing a synchronizing portion of an input synthesized video signal and outputting a synthesized synchronizing signal, and masking processing of the synthesized synchronizing signal other than the horizontal synchronizing signal to form a first horizontal synchronizing signal. A masking circuit for outputting a signal, an AFC circuit for generating a signal that is phase-synchronized with the first horizontal synchronization signal by transmission frequency control and outputting the signal as a second horizontal synchronization signal, and a phase difference between the first and second horizontal synchronization signals. A lock / unlock detection circuit that outputs a lock / unlock detection signal based on whether or not the value is equal to or less than a set value;
A switching circuit for switching between the first and second horizontal synchronizing signals according to the lock / unlock detection signal and outputting the signals. 7. An AFC circuit comprising: a phase comparator that compares a phase with a comparison signal using a first horizontal synchronization signal output from a masking circuit as a reference signal, and outputs a signal corresponding to a phase difference;
LPF for smoothing and outputting the output signal of this phase comparator
And a VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF and outputs the frequency. The frequency of the output clock of the VCO is divided and output as a comparison signal to the phase comparator. 7. The horizontal sync separation circuit according to claim 6, further comprising a frequency divider that outputs the second horizontal sync signal. 8. A synchronizing slice circuit for slicing a synchronizing portion of the input synthesized video signal and outputting a synthesized synchronizing signal, and masking processing of the synthesized synchronizing signal other than the horizontal synchronizing signal to produce a first horizontal synchronizing signal. A masking circuit for outputting, a phase comparator for comparing a phase with a comparison signal using the first horizontal synchronization signal as a reference signal, and outputting a signal corresponding to the phase difference; LPF, a VCO that changes the oscillation frequency of the clock in accordance with the output voltage of the LPF and outputs the frequency, and divides the frequency of the output clock of the VCO to create a second horizontal synchronizing signal. A frequency dividing / switching circuit for switching and outputting the second horizontal synchronization signal, and locking based on whether or not the phase difference between the first and second horizontal synchronization signals is equal to or less than a set value;
A lock / unlock detection circuit that outputs an unlock detection signal, wherein the frequency division / switching circuit switches and outputs the first and second horizontal synchronization signals with the lock / unlock detection signal. A horizontal sync separation circuit characterized by: 9. A frequency dividing / switching circuit, comprising: a counter for counting a clock output from a VCO; and an X count for decoding that the count value of the counter becomes X corresponding to a frequency dividing ratio and outputting a signal. A decoder, a Y count decoder for decoding that the count value of the counter becomes Y (Y <X) and outputting a signal, and an edge detecting circuit for detecting a falling or rising edge of the first horizontal synchronization signal A switching circuit for switching between the detection signal of the edge detection circuit and the output signal of the X count decoder and outputting the signal to the reset side of the counter; a set signal for the output signal of the switching circuit; An RS flip-flop as a reset signal, outputting an output signal of the RS flip-flop as a horizontal synchronizing signal and comparing the output signal with a phase comparator. Horizontal sync separator of claim 8, wherein comprising output as signal. 10. A lock / unlock detection circuit, comprising: a gate pulse generation section for generating a gate pulse in which a conduction period is set for a set period Th including a rising edge (or a falling edge) of a second horizontal synchronization signal; 10. A lock / unlock determination unit which latches a pulse at a rising edge (or a falling edge) of the first horizontal synchronization signal and outputs the pulse as a lock / unlock detection signal.
A horizontal sync separation circuit as described. 11. A gate pulse generator for detecting a rising edge (or a falling edge) of a second horizontal synchronizing signal.
An edge detection circuit, a counter that counts a clock output from the VCO, and a count value of which is cleared by a detection signal of the second edge detection circuit, wherein the count value of the counter corresponds to one of the start and end of the set period Th An a-count decoder that decodes the signal a and outputs a signal, and outputs a signal by decoding that the count value of the counter becomes b corresponding to the other of the beginning and the end of the set period Th. The lock / unlock determination unit includes a b count decoder and an RS flip-flop that outputs a gate pulse using one output signal of the a and b count decoder as a set signal and the other output signal as a reset signal. A first edge detection circuit for detecting a rising edge (or a falling edge) of a horizontal synchronizing signal, and a gate output from the RS flip-flop It latches the scan in detection signal of the first edge detection circuit locks the horizontal sync separator of claim 10, wherein comprising a D flip-flop for outputting a detection signal of the unlock. 12. A lock / unlock detection circuit, comprising: a gate pulse generator for generating a gate pulse in which a conduction period is set only for a set period Th including a rising edge (or a falling edge) of a second horizontal synchronization signal; A lock / unlock determination unit that latches a pulse at a rising edge (or a falling edge) of the first horizontal synchronization signal and outputs a lock / unlock determination signal, and a plurality of lock determination signals of the lock / unlock determination unit. 10. The horizontal synchronization according to claim 6, further comprising a determination result integrating unit that outputs a lock detection signal when the lock determination signal is continued a plurality of times and an unlock detection signal when the unlock determination signal is continued a plurality of times. Isolation circuit. 13. A gate pulse generator for detecting a rising edge (or a falling edge) of a second horizontal synchronizing signal.
An edge detection circuit, a counter that counts a clock output from the VCO, and a count value of which is cleared by a detection signal of the second edge detection circuit, wherein the count value of the counter corresponds to one of the start and end of the set period Th An a-count decoder that decodes the signal a and outputs a signal, and outputs a signal by decoding that the count value of the counter becomes b corresponding to the other of the beginning and the end of the set period Th. The lock / unlock determination unit includes a b count decoder and an RS flip-flop that outputs a gate pulse using one output signal of the a and b count decoder as a set signal and the other output signal as a reset signal. A first edge detection circuit for detecting a rising edge (or a falling edge) of a horizontal synchronizing signal, and a gate output from the RS flip-flop And a D flip-flop for latching the first horizontal synchronizing signal using the inverted Q output of the D flip-flop as a gate signal. One gate circuit, a second gate circuit that controls the passage of a first horizontal synchronization signal using the Q output of the D flip-flop as a gate signal, and counts the first horizontal synchronization signal that has passed through the first and second gate circuits. First and second integrating circuits, and outputs a signal by decoding that the count value of the first integrating circuit has become c (c is an integer of 2 or more) and outputs the output signal to the second integrating circuit. The c count decoder as a clear signal to the circuit, and the count value of the second integrating circuit is d (d
Is an integer of 2 or more), outputs a signal, outputs the signal, and uses this output signal as a clear signal to the first integrating circuit, and one of the outputs of the c and d count decoders. 13. The horizontal synchronizing separation circuit according to claim 12, comprising an RS flip-flop having a signal as a set signal and the other output signal as a reset signal, wherein an output signal of the RS flip-flop is used as a lock / unlock detection signal.