JPH0810859B2 - Phase synchronization circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a phase locked loop circuit suitable for clock reproduction.

[Technical background of the invention and its problems]

In recent years, various so-called high-definition television systems have been proposed, which enable higher-definition image transmission than the NTSC color television system, and one of them has been proposed by Ninomiya et al. Channel transmission system (MU
SE) ”Technical Report of the Television Society, TEBS95-2, Showa 59
MUSE (Multiple Sub-Nyquist Sa
mpling Encoding).

The MUSE system thins out the lattice points of the image information represented by sample values for each lattice point and transmits it by thinning out the lattice points according to a predetermined rule in order to minimize the frequency bandwidth required for signal transmission. This is a method for approximating grid point information that has not been transmitted by using inter-frame and inter-frame interpolation. The grid point information to be transmitted in this method is
PAM with constant sampling period, for example 1 / (16.2MHz) period
Although it is transmitted as a (pulse amplitude modulation) signal, in order to save the transmission bandwidth, the baseband conversion total transfer characteristic is the Nyquist condition, that is, the isolated pulse sample value is t = nT (n
It is selected as narrow as possible within a range satisfying the condition that ≠ O and T become O at the sampling period). Therefore,
If the phase of the sampling clock of the PAM demodulator (sampling circuit) on the receiving side deviates even slightly from the original phase, inter-sample crosstalk occurs in the demodulated output accordingly.
The crosstalk between the samples is finally displayed horizontally on the playback screen.
In the MUSE system, which aims at high-quality image transmission, it must be kept as small as possible because it leads to a reduction in resolution in both the vertical and vertical directions. That is, in the MUSE system, the phase of the sampling clock on the receiving side needs to be very accurately synchronized with the clock on the transmitting side.

By the way, in the MUSE system, the sampling clock itself is not transmitted, and instead, HD (horizontal synchronization) signals and FP (frame pulses) signals as shown in FIGS. 2 (a) and 2 (b) are transmitted as synchronization signals. Has been done. The HD signal is inserted at the head of each horizontal scan line signal. One horizontal scanning line is 480T with the clock cycle T = 1 / (16.2MHz)
, But the first to twelfth sampling points are defined as shown in FIG. 2 (a). On the other hand, the FP signal is 11
Adjacent two in one frame consisting of 25 horizontal scan lines
It is inserted in one set of horizontal scanning lines and is defined as shown in FIG.

In this way, both the HD signal and FP signal are created by dividing the clock frequency (16.2MHz),
In particular, since the waveform of the HD signal is a waveform whose amplitude value at the sampling time is accurately specified, the sampling clock can be reproduced on the receiving side with the HD signal as a reference.

To reproduce the sampling clock on the receiving side, concretely, oscillate with the phase comparator with the received input signal as one input, the loop filter with the output of this phase comparator as the input, and the output of the loop filter. This is performed using a phase locked loop circuit composed of a voltage controlled oscillator whose frequency is controlled. That is, the voltage-controlled oscillator is controlled by the phase error signal obtained by the phase comparison between the FP signal detected from the input signal and the internal FP signal created internally based on the output of the voltage-controlled oscillator, and the output of the voltage-controlled oscillator is controlled. Phase error signal obtained by comparing the phase error of the sampling clock obtained within a certain range and then the phase comparison between the HD signal in the input signal and the internal HD signal created internally based on the output of the voltage controlled oscillator. By controlling the voltage-controlled oscillator with, the phase error of the sampling clock is driven to a value very close to zero, so that the sampling clock correctly phase-synchronized with the clock on the transmitting side is reproduced.

However, such a phase locked loop has a problem that the initial pull-in time is long. That is, in the conventional phase locked loop circuit, the initial pull-in is performed by the phase locked loop based on the FP signal, but the FP signal is 1 /
Since it arrives only once in 30 seconds, the phase correction of the sampling clock by this phase locked loop can be performed only 30 times per second. Although it depends on the degree of phase shift of the sampling clock in the initial state and the amount of one-time correction by the phase locked loop, the time required for initial pull-in, that is, the phase error of the sampling clock is
The time required to enter the pull-in range of the phase-locked loop based on the HD signal is usually on the order of a few seconds to a few tens of seconds, which is an unacceptable length for a general television receiver. Also, when a video disk or VTR with many signal loss (dropout) is used as the input signal source, the FP signal is erroneously detected, or the phase error value due to the HD signal becomes an erroneous value, resulting in synchronization. There was a problem of instability.

[Object of the Invention] When the reproduction clock is phase-locked with the clock on the transmission side by a two-step operation based on two kinds of synchronization signals having different periods, the object of the present invention is to reduce the time required for the phase synchronization to be established. The object is to provide a phase synchronization circuit that can be significantly shortened and that can stably maintain phase synchronization even for a video disc with many dropouts or a VTR playback signal.

[Outline of Invention]

The phase locked loop circuit according to the present invention has a clock cycle T of m.
First synchronization signal with a period of twice (m is a rational number greater than 1) and mn times the clock period T (n is a rational number greater than 1)
In a phase synchronization circuit that receives an input signal including a second synchronization signal having a period of, and generates a reproduction clock that is phase-synchronized with the clock, the first synchronization signal and the first reproduction synchronization signal included in the input signal. A phase comparator for comparing the phases of and, a loop filter having the output of the phase comparator as an input, a voltage controlled oscillator for controlling the oscillation frequency by the output of the loop filter to generate a reproduction clock of cycle T, A frequency dividing circuit for dividing the reproduction clock output from the voltage controlled oscillator into 1 / m and 1 / mn to obtain first and second reproduction synchronizing signals respectively corresponding to the first and second synchronizing signals; Means for detecting the presence timing of the second synchronizing signal in the input signal, and comparing the detection timing of the second synchronizing signal with the timing of the second reproducing synchronizing signal, Out-of-sync is detected, and when the out-of-sync state is continuously detected for a predetermined time or more, the second
The frequency divider circuit is reset to a predetermined initial state at the next detection timing of the sync signal of
It is characterized in that it is provided with means for stopping the detection of the out-of-synchronization and stopping the operation of the loop filter by a signal indicating an abnormal signal such as a dropout included in the reproduction signal of the VTR.

That is, instead of forming a phase locked loop by a second synchronizing signal having a long period such as an FP signal, the detection timing of the second synchronizing signal in the input signal and the second timing generated on the receiving side corresponding to this Out-of-sync state of the reproduction clock is detected by comparison with the timing of the reproduced-sync signal, and the out-of-sync state occurs continuously over a certain period of time, and
When the input signal is not abnormal, the frequency divider circuit is reset to forcibly perform the pull-in operation.

〔The invention's effect〕

According to the present invention, in the initial state, the phase of the reproduction clock is forced to fall within the pull-in range of the phase-locked loop based on the first synchronization signal. Therefore, the phase of the reproduction clock is regenerated every time the second synchronization signal arrives. Compared with the conventional method of performing correction, not only the time until the phase synchronization is established can be shortened remarkably, but also the synchronization can be stably maintained for the input signal including the dropout.

Example of Invention

FIG. 1 shows an embodiment in which the present invention is applied to a phase synchronizing circuit for sampling / clock reproduction on the receiving side in MUSE type television transmission. In the figure,
The HD signal shown in FIGS. 2 (a) and 2 (b) (first
Of the baseband television signal including the FP signal (the second synchronization signal) and the FP signal (the second synchronization signal).
It is converted to a bit-like digital signal.

The A / D converter 2 operates according to a sampling clock supplied from a VCXO (voltage controlled crystal oscillator) 8. VCXO
8 may be an oscillator that directly outputs the required sampling clock frequency of 16.2 MHz, or may be a combination of an oscillator and a frequency divider that oscillates at another frequency with a fixed ratio of 16.2 MHz. . The sampling clock output from the VCXO8 is led to the output terminal 9.

The output of the A / D converter 2 is divided into two, one of which is introduced into the FP (frame pulse) detection circuit 3 and the other of which is introduced into a phase comparison circuit (hereinafter referred to as HD phase comparison circuit) 5 for HD (horizontal synchronization) signals. . Of the outputs of the A / D converter 2, only the MSB (Most Significant Bit) is input to the FP detection circuit 3. The function of the FP detection circuit 3 agrees with that during the output of the A / D converter 2 by paying attention to the fact that the FP signal has a waveform of a specific shape defined as shown in FIG. It is to detect the time when the pattern appears. That is, in the MSB sequence of the output of the A / D converter 2, as shown in FIG.
It detects an event that a value pattern and a binary pattern in which 1 and O are reversed are present with a difference of 480 clocks. In the binary pattern sequence of FIG. 3, the first “1” time (indicated by the mouth) of the last “1” sequence is called the detected FP point, and the FP detected from the input signal.
The time base of the signal.

On the other hand, the output of the VCXO8 is 1 / mn by the frequency dividing circuits 11 and 12,
That is, the frequency is divided into 1 / (480 × 1125) and introduced as an internal FP signal (IFP) of 30 Hz into a phase synchronization circuit (hereinafter referred to as FP phase comparison circuit) 4 for FP (frame pulse).

The FP phase comparison circuit 4 is provided with a dropout signal indicating a missing input signal input to the input terminal 1.
Supplied through 20.

In the FP phase comparison circuit 4, a phase comparison is made between the detected FP point and a specific point (called an internal FP point) of the internal FP signal which is the output of the frequency dividing circuit 12, and the difference between them is within ± 1 clock range. If there is "O", otherwise "1" is output. Specifically, this is achieved by creating a window pulse with a width of 3 clocks in which the falling point of the internal FP signal is the rising edge and detecting with the gate circuit whether the detected FP point falls within this window pulse. It

The output of the FP phase comparison circuit 4 is supplied to the determination circuit 13.
The determination circuit 13 observes the output of the FP phase comparison circuit 4 in the cycle of the internal FP signal, and when a "1" is continuously observed a predetermined number of times (for example, 8 times), a "1" is generated as a reset pulse. Output to circuit 14. The determination circuit 13 is realized by, for example, a counter.

The reset pulse generation circuit 14 outputs "O" from the judgment circuit 13.
When it transits from "1" to "1", it enters the standby state, and the reset pulse 15 is generated at the timing of the detected FP point which first arrives after entering this standby state. The reset pulse 15 resets the loop filter 6 and the frequency dividing circuits 11 and 12 to a predetermined initial state.

The dropout signal is also supplied to the loop filter 6 through the terminal 20.

At this time, the initial state of the frequency dividing circuits 11 and 12 is such that the detected FP point and the internal FP point are within ± 1 clock and the input signal
It is assumed that the phase difference between the HD signal and the internal HD signal output from the frequency dividing circuit 11 is set within the range of ± 1 clock.

At this point, the phase comparator 10 including the A / D converter 2 and the HD phase comparison circuit 5 to the loop filter 6 to the D / A converter 7 to VCXO8 to the frequency dividing circuit 11 to the phase comparator 10 A phase locked loop of loops is formed.

FIG. 4 shows a specific configuration diagram of the FP phase comparison circuit 4, the determination circuit 13 and the reset pulse generation circuit 14, and its operation will be described with reference to the timing chart of FIG. The internal FP signal IFP from the frequency dividing circuit 12 is supplied to the window pulse generating circuit 41 configured by the counter, and the three clocks (clock ... φ) whose rising point is the falling point of the internal FP signal IFP.
A width window pulse IFPW is created. The window pulse IFPW is masked in the AND circuit 43 by the dropout signal D input from the terminal 20 and inverted by the NT circuit, and becomes the signal a. The signal a is the NAND circuit 42 and the counter 13
Supplied to 1 clock (CK) input. FP detection circuit 3
Then, the FP signal is supplied to the NAND circuit 42 and the AND circuit 141.
The output signal b of the NAND circuit 42 is cleared by the counter 131 (C
^- L) is supplied to the input. The output signal C of the counter 132 is A
The NT circuit 13 is supplied to the ND circuit 141 and the NT circuit 132.
The output of 2 is fed to the enable (EP) input of counter 132.

The output signal d of the AND circuit 141 is supplied to the input of the latch 142 operating with the clock φ, and the output signal 15 thereof is a reset pulse and is supplied to the frequency dividing circuit 12.

First, when the power is turned on, the phases of the internal FP signal IFP and the FP signal are different even though they are in an asynchronous state. For simplicity, the input signal is normal and the dropout signal D indicating the abnormality is at low level. Therefore, since the FP signal is outside the window pulse IFPW, the counter 131 is not cleared and is counted up by the window pulse IFPW. This counter stops operating unless the signal C goes high and the enable of the counter 131 goes low when it is counted up eight times in a row. At the same time, the AND circuit 141 enters the passing state, the FP signal is supplied to the latch 142, and the latch output is reset pulse 15 to reset the loop filter 6 and the frequency dividing circuits 11 and 12 to a predetermined initial state. To do. The operation in the synchronous pull-in state after reset will be described later. After a lapse of a predetermined time, the synchronization is established and the synchronization holding state is set. In the synchronous hold state, the FP signal is the window pulse IF
Since it is in the PW, the counter 131 is cleared for each FP signal, resetting is not required, and stable synchronization is maintained.
Here, consider a state in which an input signal is missing due to dropout. The dropout is a VT
This occurs when using R or a video disk. When the dropout signal D from the input signal source becomes high level, the window pulse signal a becomes low level,
Since the clock of the counter 131 disappears, the count up is not performed and the reset pulse 15 is not generated. Therefore, even if the dropout occurs and the FP signal is not correctly generated, the reset is not applied.

The HD phase comparison circuit 5 is specifically realized by the configuration shown in FIG. That is, the sample value series consisting of the 8-bit parallel signal from the A / D converter 2 is passed through the four-stage shift registers 21 to 24, the coefficient circuits 26 and 27, the adder circuits 25 and 28, and the shift register 29 as a phase error signal. Is output. Here, the shift registers 21 to 24 have the same 16.2 Hz as the A / D converter 2.
, While the shift register 29 is driven by an internal HD signal obtained by dividing the sampling clock by 1/480. If the arithmetic operation performed by the phase comparator 10 is expressed by an expression, the analog input to the A / D converter 2 is x (t), the digital output value of the shift register 29 is y, and the sampling of the A / D converter 2 is performed.・ The phase error of the clock normalized by the sampling period T is φ (note that 1 /
Since the timing word difference of the internal HD signal determined by the initial condition of the 480 frequency divider 13 is also included in φ, | φ | can be 1 or more) as y = 1/2 {× (φT−2T) + × ( φT + 2T)-× (φ
T) (1) FIG. 7 shows the calculation result of the equation (1) with φ being the horizontal axis and y being the vertical axis. Although y is a periodic function with a period of 480 with respect to φ, only the limited section of −3 <φ <3 shows the phase comparison characteristic. For other sections, no meaningful information is obtained from the phase comparator 10 regarding the phase error φ of the sampling clock.

By the way, in the initial state in which the phase locked loop is formed, the phase error φ of the sampling clock is within the range of -1 <φ <1 in FIG. However, at this time, the oscillation frequency of the VCXO8 is still deviated from the original clock frequency, and if left unattended, | φ | becomes a large value in a short time. However, since the phase-locked loop is already formed and the initial state is within the effective range (−3 <φ <3) of the phase comparison characteristic of FIG. 7, the parameters of the loop filter 6 are appropriate. If so, φ will converge in the vicinity of O without deviating from this range.

The transfer function of the loop filter 6 at this time is the Z conversion display of the sampling period 480T (the period of the HD signal). Kf: Gain constant [VOlt] b: Integral system distribution ratio (O <b << 1). At this time, the transmission relationship of the entire phase locked loop is Kd: Phase comparator sensitivity [1 / red] Kv: VCXO modulation sensitivity [Hz / volt]. K is a loop gain, usually K << 1. The operating characteristics of this phase locked loop are determined by K and b. When b≈K / 4 (4), critical damping occurs, under damping occurs when b is larger than this, and over damping occurs when b is small. The phase jitter of the playback sampling clock during critical damping is S / S of the input signal.
The order is K times N (voltage value).

FIG. 8 shows a specific example of the configuration of the loop filter 6 described above, which is composed of coefficient circuits 31 and 32 for respectively providing a gain constant Kf and an integral system distribution ratio b, an adder circuit 33 and a latch 34. It is composed of a cumulative addition circuit (digital integration circuit), an addition circuit 35, and a latch 38 which holds the output thereof. When the reset pulse 15 is given, the content of the latch 34 holding the second term in the parentheses on the right side of the equation (2) is cleared to O.

Normally, in a phase locked loop using a perfect integration type loop filter as shown in equation (2), the lock pull-in range is infinite, but the output y of the phase comparator 10 is φ as shown in FIG.
In the case of the phase comparison characteristic in which only a part of one period of the above is non-zero, the synchronous pull-in range is finite. The reason is explained as follows. Now, assuming that there is a deviation between the clock frequency of the input signal and the oscillation frequency of the VCXO8, once at a certain time, φ =
Even if it is initially set to O, | φ |
Grows.

The phase locked loop operates so as to pull back this | φ | in the direction of O, and the pulling back force is proportional to the loop gain K in the range where | φ | is small. Depending on the force relationship between | φ | that increases due to the frequency difference and K that tries to pull it back, | φ | converges to O, or | φ | gradually increases and exceeds 3 It is decided whether or not it will fall out of control.

For a certain value of K, there is a certain limit on the initial frequency difference for | φ | to converge to O.

This limit is called a sync pull-in range. The sync pull-in range is
Although it depends on the value of φ at the time of resetting, the larger K is, the wider it is.

According to the computer simulation, K = 1/10
The synchronization pull-in range when 0, b = K / 4 (critical damping) is represented as shown in FIG. 9 with the initial phase shift φ as the horizontal axis. Vertical axis Δf is VCXO initial frequency 16.2MH
It is a deviation from z. As in the first and third quadrants, Δf and φ
When the signs are the same, the sync pull-in range is attached as shown in this figure, but when Δf and φ are different signs as in the second and fourth quadrants, the situation is slightly different. For example, the second
In the quadrant, when −3 ≦ φ ≦ O, rapid synchronization pull-in is performed, and even when φ <−3, it takes time, but soon the synchronization pull-in is performed. This is because even if the control voltage is not applied to the VCXO8, in this case, since Δf is positive, φ shifts to the right with time, and eventually exceeds φ = −3 and enters the synchronous pull-in range. It is within the shaded area in the figure that the mechanism of the phase-locked loop actively works to reach the locked state. The initial phase error φ and the initial frequency difference of the sampling clock when the frequency dividing circuits 11 and 12 and the loop filter 6 are reset by the reset pulse 15 from the reset pulse generating circuit 14 are within the above sync pull-in range. If so, the phase-locked loop operates normally, and φ eventually converges to O.

In the steady state where phase synchronization is established, the phase error φ
Is usually almost O, so the output of the FP phase comparison circuit 4 is "O" with a high probability. This output becomes "1" only when the input noise or the phase synchronization is lost for some reason (including when the power is turned on). In the former case, "1" appears only once, whereas in the latter case, "1" appears continuously over several frames. The determination circuit 13 distinguishes the two from each other, and in the case of out-of-synchronization, the reset pulse generation circuit 14 generates the reset pulse 15 and the operation of the phase locked loop is restarted from the beginning.

Further, due to the dropout, when the input signal is missing, the output of the HD phase comparison circuit 5 becomes an abnormal value, so the calculation operation of the loop filter 6 is stopped. this is,
This is realized by stopping the clocks of the latches 34, 38 by the dropout signal D. At this time DAC7
, The value immediately before the dropout continues to be supplied, so the stability of synchronization is the stability of the VCX8 itself. However, during the normal dropout period (longer than 1 second), the frequency phase drift of the VCX8 can be neglected sufficiently, so by keeping the arithmetic operation of the loop filter 6 stable during this period. To be done.

Further, even if the input signal of the loop filter 6 is forced to be O, that is, the input signal of the coefficient unit 31 is O, the same effect can be obtained.

According to the present invention, the time required from the occurrence of the loss of synchronization once to the establishment of the synchronization again is the time T ₁ from the occurrence of the loss of synchronization to the generation time point of the reset pulse 15 and the phase error φ from the reset time point to the steady state. It is the sum of the time T ₂ required to reach the state.

T ₁ differs depending on how many consecutive “1” s are determined to be out of synchronization by the determination circuit 13, but if this is set to 8, T ₁ will be 8/30 [sec]. Become. T ₂ is the loop gain K, the degree of damping (determined by b), the initial frequency difference (difference between the clock frequency when the frequency divider circuits 11 and 12 are reset and the oscillation frequency of the VCXO8) and the phase error immediately after the reset. Although it depends on the value, it is on the order of NT / K (NT is the period of HD signal) in the vicinity of critical damping. As an example, if K = 1/100, T ₂ = 3 [msec]
Therefore, even if this is added to T ₁ , the total time from the loss of synchronization to the establishment of synchronization is 1/3 [sec].
However, the conventional method requires a few seconds, which is a significant reduction compared to the conventional method.

FIG. 10 shows another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that the loop filter of the phase locked loop has a variable transfer function (especially closed loop bandwidth) in two stages. Is used, and its transfer function is switched by the timer 17.

The purpose of this embodiment is to expand the frequency pull-in range and reduce the phase jitter of the reproduction sampling clock in the steady state. Generally, both parties have mutually contradictory requirements,
The larger the loop gain K, the wider the frequency pull-in range, but the phase jitter increases. If K is made small, the phase jitter can be made small, but the frequency pull-in range becomes narrow. To solve this contradiction, K may be increased immediately after the operation of the phase locked loop is started, and K may be changed to a smaller value after a certain time has elapsed. This is achieved in the embodiment shown in FIG.

FIG. 11 shows a concrete example of the configuration of the loop filter 16 in FIG. 10, in which the gain constant Kf and the integral system distribution ratio b
Two sets of coefficient circuits are provided like 31a, 31b and 32a, 32b, and one of them is selected by the switching switch 36, 37.
One is getting selected. Switching switch 36, 37
Is controlled by the output 18 of the timer circuit 17.

Now, when the judgment circuit 13 detects the loss of synchronization and the reset pulse generation circuit 14 generates the reset pulse 15, the frequency dividing circuits 11 and 12, the judgment circuit 13 and the reset pulse generation circuit 14 are reset by this. At the same time, the timer 15 is set, and the switching switches 36 and 37 are connected to the coefficient circuits 31a and 32a, respectively. At this time, the latch 34 of the loop filter 16 is also reset to a predetermined initial state. However, this resetting of the latch 34 does not have to be performed in the case of a short time synchronism. Then, the output 18 of the timer 17 causes the switching switches 36 and 37 to be switched to the coefficient circuits 31b and 32b, respectively, after a lapse of a predetermined time from the generation of the reset pulse 15. As a result, the loop filter 16 switches the loop gain K depending on, for example, the gain constant Kf from 1/100 to 1/1000 and the integral system distribution ratio b from 1/400 to 1/4000. That is, the closed loop bandwidth is switched to the narrower one. However, in this case, the integrated value itself held in the latch 34 in the loop filter 16 is inherited as it is when the coefficient circuits 31a and 32a are connected. By doing so, the sync pull-in range remains the same as in the case of the embodiment of FIG. 1 (its characteristics are shown in FIG. 7), and the phase jitter of the reproduction sampling clock is represented by the RMS value. Can be reduced to

In this embodiment, two transfer functions of the loop filter 16 are prepared and switched after a predetermined time has passed.
It is obvious that the same effect can be obtained even if three or more transfer functions are prepared and sequentially switched.

FIG. 12 shows another embodiment of the reset stopping means. The difference from FIG. 4 is that only the clock signal of the counter 131 is stopped by the dropout signal D.

Further, the reset pulse 15 is masked by the dropout signal D, and when the dropout signal comes, the reset pulse 15 is not reset and the similar effect is obtained.

The present invention is not limited to the above-mentioned embodiment, but for example, in the embodiment, an example in which the present invention is applied to a phase synchronization circuit for clock reproduction on the receiving side in MUSE type television transmission is described. The invention can be applied to various phase locked loop circuits other than this. In addition, the phase-locked loop does not include an A / D converter or D / A converter, but the phase-comparator or loop filter is composed of analog circuits, or the loop filter is a microprocessor software. It can also be applied to a digital phase-locked loop circuit such as that implemented in. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention.
2 (a) and 2 (b) are waveform diagrams of the horizontal synchronizing signal and the frame pulse inserted in the transmission signal in the MUSE system, and FIG. 3 is a diagram showing a binary pattern detected by the frame pulse detection circuit. FIG. 4 is a concrete configuration diagram of the FP phase comparison circuit 4, the decision circuit 13 and the reset pulse generation circuit 14 in the embodiment of FIG. 1, and FIG. 5 is a timing diagram for explaining FIG. FIG. 6 is a specific configuration diagram of the phase comparison circuit for the horizontal synchronization signal, and FIG. 7 is a characteristic diagram showing the relationship between the output of the phase comparator including the phase comparison circuit for the horizontal synchronization signal and the phase error of the sampling clock. FIG. 8 is a concrete configuration diagram of the loop filter in the embodiment of FIG. 1, FIG. 9 is a diagram showing the result of computer simulation regarding the frequency pull-in range of the phase locked loop, and FIG. 10 is another embodiment of the present invention. FIG. 11 is a block diagram of the phase-locked loop circuit, FIG. 11 is a specific block diagram of the loop filter in the same embodiment, and FIG. 12 is another embodiment of the reset stopping means. 3 ... Frame pulse detection circuit, 4 ... Phase comparison circuit for frame pulse, 5 ... Phase comparison circuit for horizontal synchronizing signal, 6 ... Loop filter, 8 ... Voltage controlled oscillator, 10 ...
Phase comparator, 11.12 ... Frequency divider circuit, 13 ... Judgment circuit, 14 ... Reset pulse generation circuit, 16 ... Loop filter, 17 ... Timer circuit.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yoshimichi Otsuka 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Technology Laboratory (72) Inventor Yoshinori Izumi 1-10 Kinuta, Setagaya-ku, Tokyo No. 11 Broadcasting Technology Laboratory of Japan Broadcasting Corporation (72) Inventor Seiichi Koshi 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Laboratory of Japan Broadcasting Corporation

Claims (2)

[Claims] 1. A first synchronizing signal having a period of m times the clock period T (m is a rational number greater than 1) and the clock period T.
A phase synchronization circuit that receives an input signal including a second synchronization signal having a period of mn times (n is a rational number greater than 1) and that generates a recovered clock that is phase-synchronized with the clock. A phase comparator that compares the phase of the first synchronization signal with the phase of the first reproduction synchronization signal, a loop filter that receives the output of this phase comparator, and the oscillation frequency is controlled by the output of this loop filter, and the cycle T The voltage-controlled oscillator that generates the recovered clock of
A frequency dividing circuit for obtaining first and second reproduction synchronizing signals corresponding to the first and second synchronizing signals by dividing into / mn, and detecting the existence timing of the second synchronizing signal in the input signal Means for detecting the loss of synchronization of the reproduction clock by comparing the detection timing of the second synchronization signal with the timing of the second reproduction synchronization signal, and this out-of-synchronization state is continuously detected for a predetermined time or longer. Reset means for resetting the frequency dividing circuit to a predetermined initial state at the next detection timing of the second synchronizing signal, and a signal indicating an abnormality of the input signal to stop the reset operation and the loop filter. And a means for stopping the arithmetic operation of the phase-locked loop circuit. 2. The reset operation stopping means stops comparing the detection timing of the second synchronizing signal with the timing of the second reproduction synchronizing signal. The phase synchronization circuit described.