JPS6229271A - Television receiver - Google Patents

Abstract

PURPOSE:To obtain a screen that does not cause a viewer to feel uncomfortable with lowering the luminance of the screen or interrrupting an output signal itself by deciding whether it is a pull in state or not by the logical product of the reset signal of a divider in a vertical synchronous circuit and the logic OR of two control signals in an internal oscillator control circuit. CONSTITUTION:An inverter 20 inverts the reset signal that resets a frame counter 8. It is assumed that the inverted reset signal 21 is the first unlock detecting signal. A NOR gate circuit 22 takes the negation of the logic OR of two control signals that controls an updown counter 11. It is assumed that the output 23 in the second unlock detecting signal. In other words, the detecting signals 21 and 23 become zero in an unlock time. A logical circuit 24 generates the third unlock detecting signal 25 from previous stated two unlock detecting signals, and it is constituted that the output 25, when it is zero, is inverted to one when both of inputs 21 and 23 become one, and adversely, the output 25, when it is one, is inverted to zero when the input 21 becomes zero, regardless of the state of the input 21.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization device for a television receiver.

2. Description of the Related Art Satellite television broadcasting currently carried out in Japan uses radio waves obtained by FM modulating an NTSC signal as a video signal. This has the advantage of being able to use existing receivers since the NTSC signal can be obtained directly by demodulating the FM signal, but it also has the following disadvantages. In other words, in the NTSC signal, the synchronization signal protrudes below the video signal, that is, it is negative polarity synchronization, so about 30% of the frequency deviation of FM modulation is spent only on the synchronization signal, which is disadvantageous in terms of S/N. It is.

For this reason, MA is the preferred transmission method for satellite broadcasting in Europe.
A method called C and a method called MUSE for high-definition television broadcasting in Japan have been proposed, but both adopt positive polarity synchronization, that is, a method in which the synchronization signal is included in the video signal amplitude. has been done. Since it is very difficult to separate the synchronizing signals individually in the amplitude direction with these positive polarity synchronizing signals, in the case of the MUSE signal, a specially shaped vertical synchronizing signal is inserted in the vertical retrace period. The phase synchronization between the input television signal and the synchronous oscillation circuit of the receiver is achieved by first extracting the vertical synchronizing signal and then extracting the horizontal synchronizing signal using the correlation between the scanning lines. A specific example of a vertical synchronization signal is a signal provided on two adjacent lines with opposite polarities so that a rectangular wave with several clock cycles is repeated for several tens of cycles for each frame of the image signal. Therefore, the probability of a pulse train or noise in an image signal component that approximates a frame synchronization pulse train having such a configuration is statistically very small, so that the timing of frame synchronization can be detected accurately. (Reference Document: Patent Publication No. 1982-221091 Clock Phase Lock System) The configuration of a synchronization circuit using frame pulses, which are vertical synchronization signals extracted as described above, will be explained in FIG. In the figure, 1 is a MUSE television signal input terminal, and 2 is an analog-to-digital converter (hereinafter referred to as A
/D), 3 is a digital signal output terminal,
4 is a frame pulse detection circuit according to the method described above;
6 is a phase difference detection circuit that uses the detected frame pulse as the first input and the internally generated internal frame pulse as the second input to detect whether there is a phase difference between the two.When a phase difference occurs, The configuration is such that one pulse is generated during that frame period. 6 counts the pulses generated by the phase detection circuit, and the number of counts is N2 (N2
is a positive integer), a control pulse is generated to close the next stage gate circuit. Reference numeral 7 denotes an AND gate circuit for the output of the N2 counter 6 and the detected frame pulse, which supplies the detected frame pulse to the next stage when the N2 counter counts N2. 8
is a frame counter which generates an internal frame pulse by frequency-dividing a clock from a voltage controlled oscillator, which will be described later, and is reset by a detected frame pulse obtained from the output of the AND gate. 9 is a voltage controlled oscillator (hereinafter referred to as V
The oscillation frequency is controlled by a control voltage applied from the outside by a control voltage applied externally, and the oscillation output is supplied to the frame counter 8 and A/D 2 as a clock. 10 is a phase comparison circuit that compares the phases of the detected frame pulse and the internal frame pulse, and outputs a down signal when the internal frame pulse is ahead of the detected frame pulse, and outputs an up signal when the internal frame pulse is ahead of the detected frame pulse;
11 is an amplifier down counter controlled by the up and down control signals supplied from the phase comparator circuit, and is appropriately locked by the amplifier and down control signals, for example, counts up and counts down with internal frame pulses, etc.; Output the count number. Reference numeral 12 denotes a digital-to-analog converter (hereinafter abbreviated as D/A) that converts the output data of the up-down counter into an analog value, that is, a voltage, and the output DC voltage is added to the control voltage of the VCO 9. 13 is the phase of the horizontal synchronization signal in the video signal and the A/D
14 is an integration circuit that integrates the horizontal phase error, and 15 converts the horizontal phase error integration output data into an analog value, that is, a voltage. In the D/A, this output DC voltage is added as a control voltage of the VCO 9 to the output voltage of the D/A 12 in an adder circuit 16 to control the oscillation frequency, that is, the sampling phase of the A/D. Note that the horizontal phase control circuits shown in 13 to 15 above constitute the original phase-locked loop, and 1
0 to 12 are circuits that serve as auxiliary loops for accelerating synchronization and widening the range.

Problems to be Solved by the Invention As explained at the beginning, positive polarity synchronized television signals are S/
Although this method is advantageous in terms of N, it requires various complicated circuits to detect the synchronization signal. Therefore, it takes some time for the receiver to synchronize with the input television signal.

Therefore, when the power is turned on or when changing channels, there is a risk that an out-of-sync screen may be displayed for a moment until the receiver retracts synchronization, and especially when the clamp is not applied, the screen brightness may increase more than necessary. It is conceivable that this may result in a very unsightly screen. Therefore, to determine whether or not the receiver is in the synchronization pull-in state, when the phase comparator circuit shown in Figure 2 10 outputs an up or down signal, it is used as a detection signal that is regarded as an out-of-synchronization state, and various controls are used. It is possible to do this. However, in the case of a playback signal from a recording/playback device such as a video tape recorder (hereinafter abbreviated as VTR), there is a signal loss period called dropout, and this period is usually a horizontal scanning period (hereinafter abbreviated as 1H). Compensation is performed by making up for it with the previous signal, but if the frame pulse signal period drops out, the compensation does not return it to its original state, and the phase comparator circuit of the MUSE decoder (Fig. 2, 10) detects that the frame pulse is delayed. It makes a judgment and generates an up signal.

Drops of frame pulses are usually not continuous, so if there is only one drop, there is no risk of losing synchronization, so there is no problem, but the above-mentioned out-of-synchronization detection signal may be generated and various controls may be disturbed.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a vertical synchronizing signal, that is, a detection frame pulse detected from an input signal, and a VCO
The phase difference between the internal vertical synchronization signal, that is, the internal frame pulse, created by frequency-dividing the oscillation output of A reset signal that resets frequency division, etc. for creating an internal frame pulse is used as the first unlock signal, and the phase of the internal frame pulse and the detected frame pulse are compared to determine whether up and down signals are being output. Detect it and use it as a second unlock signal,
When the receiver is powered on or when a channel is switched and the synchronization is restored, it is determined whether or not the synchronization is in the synchronization pull-in state based on the AND of the first and second unlock detection signals, and the synchronization is once triggered. To provide a television receiver characterized in that it has a third unlock detection signal which is configured to judge whether or not the synchronization pull-in state is based on only the first unlock detection signal after the lock has been inserted. It is in.

For production The principle of the present invention is shown in FIG. 1 and its operation will be explained.

FIG. 1 is a diagram in which a circuit according to the present invention is added to FIG. 2 explained in the prior art section, and the same blocks as in FIG. 2 are given the same numbers, and a detailed explanation thereof will be omitted. In FIG. 1, 2o is an inverter that inverts a reset signal for resetting the frame counter 8, and uses the inverted reset signal 21 as a first unlock detection signal. 22 controls the up/down counter 11;
This output 23 is used as a second unlock detection signal by a NOR gate circuit which takes the logical sum of the two control signals. That is, the detection signal of 21.23 becomes 0 when unlocked. 24 is a logic circuit that generates a third unlock detection signal 25 from the two unlock detection signals, and when the output 25 is 0, it is inverted to 1 when both inputs 21 and 23 become IK, and vice versa. When the output is 1, it is inverted to 0 when 21 becomes 0, regardless of the state of the input 23. When the third unlock detection signal obtained in the above manner is detected to be unlocked, that is, when it is 0, the pedestal of the blanking period of the output signal is forcibly increased to lower the brightness of the screen, or Alternatively, it can be used as a control signal to turn off the screen by blocking the output signal itself.

Example Next, a specific circuit example of the present invention is shown in FIG.

FIG. 3 is a concrete example of the logic circuit 24 shown in FIG.
23 is a first unlock detection signal input, 23 is a second unlock detection signal input, 31 is an AND gate circuit that takes a logical product, and 32 is an output of the AND gate circuit 31 and a D type flip-flop circuit to be described later. Takes the logical OR with the output O
The R gate circuit 33 is a D type flip-flop circuit which uses the output of the OR gate circuit 32 as data input;
Other inputs include a CLR terminal that directly uses the first unlock detection signal 21 as a clear signal, and an input terminal for a clock pulse (CK) 34 having an interval equal to or less than that of the vertical synchronization signal or frame pulse signal. and a Q output terminal which performs a logical operation on the three input signals and outputs a third unlock detection signal 26. When the input/output relationship according to this embodiment is summarized in a table, it can be seen in FIG. 4 that the necessary signals are obtained. As an example, it is preferable to use a horizontal synchronization signal as the clock signal 34 in FIG. 3.

As another example, the logic output shown in FIG. 4 can be realized by using a type 7 flip-flop for T- in place of the D-type flip-flop in FIG. If you replace the lip flop, use the AND gate 31 output as 1 input, invert the 21 input and input the same clock, you will get the same result without using the feedback circuit from the output and the OR gate 32. is obtained. In any case, if necessary, it is effective to perform initial setting by forcibly performing a clearing operation when the power is turned on.

Next, an embodiment will be described in which the output video signal is controlled using the third unlock detection signal according to the present invention. In FIG. 6, 4Q is the third unlock detection signal input terminal;
1 to 48 (44 to 48 are not shown) are 8-bit digital video signal data input terminals, in particular 41 is the most significant bit, and 42 to 48 are the other lower bits. 49～
58 (52 to 56 are not shown) is an AND gate circuit; 6
7 is an OR gate circuit, and 58 to 65 (61 to 65u, not shown) are data output terminals. Now, when the third unlock detection signal input terminal 40 is 1, that is, in a steady state, 41~
The digital data entered from 48 remains as it is from 58 to 65.
output to the output terminal. On the other hand, when unlocked, that is, when 40 is 0, the most significant bit of the data is forcibly set to 0 by the AND gate 49, and the most significant bit signal that has passed through the OR gate 57 is sent to one of the AND gate circuits 50 to 56. is added to the terminal. Therefore, if the most significant bit is 1, that is, if the video signal is at a level of 60% or higher, the data of the lower bits will be sent directly to the output terminals 69 to 65.
If the most significant bit is 0, that is, the video signal is 50
If the level is below 50, the AND gate outputs of 50 to 66 will all be 0, and the output data will also be 0. That is, when the unlock detection signal becomes 0, the DC level of the video signal is forcibly lowered by 60 degrees, and the video signal component below the pedestal level is cut off.

This means that the brightness has been reduced by 50%.

In the embodiment shown in Fig. 6, the brightness is only expressed as a percentage, but if you want to select an arbitrary brightness level, you can digitally subtract an arbitrary fixed value (DC level value) from the video data. If the subtraction result is a negative value (a value below the pedestal level), underflow processing can be performed to cut it.

Another embodiment in which the output video signal is controlled using the third unlock detection signal will be described with reference to FIG. 6th
In the figure, To is the third unlock detection signal input terminal,
71 to 78 (74 to 78 are not shown) are 8-bit digital video signal data input terminals, 79 to 86 (82 to 8
6 (not shown) is an AND circuit in which the third unlock detection signal is used as one input, and the video signal data is used as the other input.
The gate circuits 87 to 94 (90 to 94 are not shown) are video signal data output terminals.In the case of this embodiment, when the unlock detection signal is 0, all output data is 0, and otherwise it is output as is. By doing this, the image is erased when synchronization is lost.

As explained above, all of the embodiments in which the output video signal is controlled using the third unlock detection signal are performed by digital signal processing, but similar effects can be obtained by converting the output video signal into a digital signal and an analog signal. It is obvious that this can also be obtained by manipulation, and there is no particular technical difficulty, so a detailed explanation in this case will be omitted.

Effects of the Invention By using the third unlock detection signal according to the present invention, if only one vertical synchronization signal is lost due to dropout, for example, it will not be immediately determined that synchronization has been lost, and furthermore, the power supply This has the effect of providing an extremely high-quality screen without causing discomfort to the viewer by displaying the screen before the synchronization is completely retracted when turning on or switching channels. In particular, in the case of a method that lowers the brightness level when synchronization is lost, it is necessary to view the screen even when synchronization is lost on a broadcast monitor, etc., and there is no need to worry about damaging the receiver by unnecessarily raising the brightness level too high. It is highly effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the principle of the television receiver of the present invention, Fig. 2 is a block diagram of a conventional synchronous circuit, and Fig. 3 is a specific circuit diagram of the main parts of the television receiver of the present invention. , FIG. 4 is a diagram showing the relationship between input and output signals of the logic circuit of FIG. 3, and FIGS. 5 and 6 are circuit diagrams of essential parts of a television receiver according to another embodiment of the present invention. 1...MUSE TV input signal input terminal, 4
...Frame pulse detection circuit, 5...
Phase difference detection circuit, 6...N2 counter, 7...
....AND gate circuit, 8 ....frame counter, 10 ....phase comparison circuit, 11 ....
... Up/down counter, 21... First unlock detection signal, 22... OR gate circuit, 23... Second unlock detection signal, 24...
...Logic operation circuit, 26...Third unlock detection signal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) Detect the phase difference between the first vertical synchronization signal detected from the input television signal and the second vertical synchronization signal obtained by dividing the oscillation output of the internal oscillator using a frequency divider. A vertical synchronization circuit configured to reset the frequency divider with the first vertical synchronization signal when the transmission lock is equal to or higher than N_1 (N_1 is a positive integer) and continues for N_2 (N_2 is a positive integer) frames. The reset signal of the frequency divider is used as a first unlock detection signal, and the phases of the first vertical synchronization signal and the second vertical synchronization signal are compared to determine whether the second vertical synchronization signal is advanced. When there is a delay, a control signal is issued to lower the oscillation frequency of the internal oscillator, and conversely, when there is a delay, a control signal is issued to increase the oscillation frequency, and the two control signals are compared by the original horizontal synchronization signal phase comparison. The logical sum of the two control signals of the internal oscillator control circuit, which is added to the PLL control signal of the internal oscillator to quickly and precisely adjust synchronization pull-in, is used as a second unlock detection signal, and the power supply of the receiver is To restore synchronization after losing synchronization, such as when turning on or switching channels, it is determined whether the synchronization is in the synchronization pull-in state by the logical product of the first and second two unlock detection signals, and the synchronization is once pulled in. It is characterized by having a third unlock detection signal that is configured to later ignore the second unlock detection signal and determine whether or not the synchronization pull-in state is based only on the first unlock detection signal. television receiver. (2) The television receiver according to claim 1, wherein the brightness of the displayed image of the television is lowered when the third unlock detection signal indicates an out-of-synchronization state. (3) The television receiver according to claim 1, wherein the television display image is turned off when the third unlock detection signal indicates an out-of-synchronization state.