JP3240751B2 - PLL circuit and video display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit in which the time required for pulling in when the lock is released is reduced, and is particularly applied to a line lock type PLL circuit used in a television receiver. It is suitable.

[0002]

2. Description of the Related Art In a conventional television receiver capable of performing EDTV, field double speed processing (hereinafter, referred to as FF processing), aspect processing and other digital video processing, a line for generating a system clock for performing digital video processing is used. A lock type PLL circuit is used. The line lock method is a method of generating a system clock by multiplying the horizontal synchronization signal based on the horizontal synchronization signal, and separating the horizontal synchronization signal from the composite video signal in advance and inputting it as an input signal to a PLL circuit. I have.

FIG. 9 shows a conventional example of such a line lock type PLL circuit. In this figure, a composite synchronizing signal CSYNC is input to a field double speed timing controller 100, and a horizontal synchronizing signal HSYNC is output by a horizontal synchronizing signal separating circuit 101 in the controller 100.
C is separated and applied to the phase comparator 105 of the PLL circuit. The phase comparator 105 compares the phase of the reference signal REF with the phase of the horizontal synchronization signal HSYNC. The phase comparator 105 is configured as a switch that allows the reference signal REF to pass only during the period when the horizontal synchronization signal HSYNC is at the “L” level, and is passed. The reference signal REF is applied to a low-pass filter (LPF) as a phase comparison output.

[0004] The phase comparison output is smoothed by the LPF 106 to become a DC error voltage, and the voltage control oscillator (VC
O) 107. Then, the oscillation frequency of the VCO 107 is controlled by the error voltage, and is controlled so that the error voltage does not occur. The frequency signal generated by the VCO 107 controlled by the error voltage is frequency-divided by, for example, 1/1820 by the counter 102 and the decoder 103 in the field double speed timing controller 100, and this frequency signal is used as the reference signal REF by the phase comparator 105. Is input to

As described above, the reference signal REF passes through the phase comparator 105 and is output to the LPF 106 while the horizontal synchronization signal HSYNC is applied to the phase comparator 105. The PLL circuit thus configured operates to lower the signal frequency generated by the VCO 107 when the error voltage is low, and to increase the signal frequency generated by the VCO 107 when the error voltage is high.
Synchronized with the horizontal synchronization signal HSYNC, for example, 182
A system clock multiplied by 0 can be obtained.
The output of the LPF 106 is also applied as an error voltage to the PLL circuit of the deflection system via the buffer circuit 104.

[0006]

FIG. 10 shows operation waveforms of the PLL circuit shown in FIG. 3A shows the horizontal synchronization signal HSYNC separated by the horizontal synchronization separation circuit 101 and input to the phase comparator 105, and FIG. 3B shows the reference signal REF input to the phase comparator 105 and the VCO 107.
This is a frequency signal obtained by dividing the output into 1/1820. (C) shows the reference signal REF that has passed through the phase comparator 105 during the period when the horizontal synchronization signal HSYNC shown in (a) is at the “L” level, and becomes the phase comparison output of the phase comparator 105. (D) is the output of the LPF 106 that smoothes the phase comparison output shown in (c) into a DC error signal.

The first horizontal synchronizing signal H shown in FIG.
When SYNC is input, the PLL circuit is in a synchronized state, the area of the upper pulse and the area of the lower pulse of the output of the phase comparator 105 are equal, and the error voltage output from the LPF 106 becomes (d). Does not change as shown. When the next horizontal synchronization signal HSYNC is input, the PLL circuit
The output frequency of the CO 107 is shifted to the lower side. At this time, the output of the phase comparator 105 is larger for the upper pulse than for the lower pulse, and the error voltage output from the LPF 106 is (d). As shown. As a result, the output frequency of the VCO 107 is controlled to increase.

Also, when the third horizontal synchronizing signal HSYNC is input, the output frequency of the VCO 107 of the PLL circuit is shifted to the lower one. At this time, the output of the phase comparator 105 also has the lower pulse of the upper pulse. The pulse voltage becomes larger than the area of the pulse on the side, and the error voltage output from the LPF 106 becomes higher as shown in (d). Thereby, VCO
The output frequency of 107 is controlled to be higher,
It is made to synchronize with a horizontal synchronizing signal.

As described above, if the synchronization of the PLL circuit is shifted by one degree, it is impossible to synchronize the output signal with the input signal unless the control for matching the output frequency is performed several times. In particular, in the PLL circuit shown in FIG. 9, even if there is a period variation of the horizontal synchronizing signal, the falling edge of the reference signal REF causes the horizontal synchronizing signal HSYN to fall.
If the pulse width is within the pulse width of C, an error voltage proportional to the period variation is generated, so that the VCO 107 easily outputs the horizontal synchronization signal H.
SYNC can be followed.

However, once there is a period variation that completely unlocks the PLL circuit, the output of the phase comparator 105 saturates to "H" or "L" and VC
O107 can only change the frequency by a certain amount, so that it is necessary to return to the pull-in range with a period change of the reference signal REF that changes only by a certain amount. Therefore, in this case, it takes time to reach the pull-in range. In the case of a line-locked PLL circuit,
This is the main cause of image bending on the screen.

Such a large fluctuation of the cycle of the horizontal synchronizing signal HSYNC occurs, for example, when the characteristics of the recording system and the reproduction system do not match during reproduction of the VTR. In the worst case, the period of the head switch of the VTR is reduced. At the (starting point of the vertical synchronization signal), a discontinuous portion of HSYNC occurs, and H
SYNC (120% to 140%) occurs.

The operation waveform of the PLL circuit in this case is shown in FIG.
Shown in (A) of this figure is a horizontal synchronizing signal HSYNC reproduced by the VTR, and a synchronism discontinuity section (HSYNC having a length of about 140% of a normal state) occurs in an intermediate section. (B) shows a reference signal REF that follows the input horizontal synchronizing signal HSYNC, and (c) shows a phase comparison output of a phase comparator composed of the reference signal REF output during a period when the horizontal synchronizing signal is at the “L” level. It can be seen that the output is saturated at the "L" level at the start point A of the synchronization discontinuity period shown in FIG.

(D) is an error voltage output from the LPF. The error voltage greatly changes at the point A shown in (c), but changes after the point A because the phase comparison output is saturated. Although the rate is gradual and the starting point for displaying an image on the screen at point C shown in the figure, the PLL circuit has not reached the pull-in range at this point, and therefore, the PLL circuit has not yet reached the pull-in range. It can be seen that image bending occurs in several cycles of the horizontal period.

This image bending is caused by the fact that the lock of the PLL circuit is lost for each vertical synchronization signal.
In the conventional PLL circuit shown in (1), since the VCO can only change by a certain amount, it takes time to converge, and the image is curved at the top of the screen as shown in FIG. However, what is shown in FIG. 12 is a case where the field double speed process described later is performed, and since the double speed process is also performed in the vertical direction, the fluctuation on the write side affects the read side at a rate of 1/2 field, and Above, the normal field and the field where the image is curved are displayed as a double image.

To solve the problem, a method of injecting the error voltage of the PLL circuit into the error voltage of the PLL circuit of the deflection system and improving the error voltage is adopted, but this method is insufficient. In particular, in the case of a high-definition television receiver, when displaying the current broadcast of NTSC on a screen, a black frame signal is generally displayed on the left and right. Was. Accordingly, an object of the present invention is to reduce the time required to reach the pull-in range when the PLL circuit loses lock.

[0016]

In order to achieve the above object, a PLL circuit according to the present invention combines the falling edge of a reference signal with the rising and falling edges of an input horizontal synchronizing signal so that a lock is lost. The error voltage is increased by expanding the pulse width of the horizontal synchronizing signal.

[0017]

According to the present invention, when the PLL circuit loses lock, the increased error voltage is applied to the VCO, so that the frequency change of the VCO becomes large and the time required for pull-in can be reduced. Therefore, if such a PLL circuit is adopted as a line-locked PLL circuit in a high-definition television receiver, even if a video signal in which the cycle of the horizontal synchronizing signal fluctuates greatly is input, the upper part of the screen will not bend.

[0018]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In this figure, a composite synchronization signal C
SYNC is a field double speed timing controller 41
The horizontal synchronizing signal HSYNC is separated by the horizontal synchronizing signal separating circuit 51 in the controller 41 and applied to the TV terminal of the switch 53 and to the horizontal synchronizing signal extending circuit 52. The output of the horizontal synchronizing signal extension circuit 52 is applied to the VTR terminal of a switch 53, and this switch 53 is switched to the TV terminal side when receiving a television broadcast signal, and when a video signal from the VTR is input. Is switched to the VTR terminal side.

This is because the horizontal synchronizing signal extension section 52 has a horizontal synchronizing signal HSYNC and a reference signal REF as described later.
In the weak electric field, the horizontal synchronizing signal extension unit 52 may malfunction and the image may be disturbed by the noise, but the time axis of the horizontal synchronizing signal HSYNC is accurate, so that the PLL circuit is used. Is unlikely to be unlocked.

The horizontal synchronizing signal HSYNC output from the switch 53 is applied to a phase comparator 54. This phase comparator 54 has a reference signal REF and a horizontal synchronizing signal HSYN.
C to compare the phase with the horizontal synchronizing signal HSY.
NC is configured as a switch that passes the reference signal REF during the “L” level, and the passed reference signal REF is used as a phase comparison output by a first low-pass filter (LPF-LP).
1) applied to 55; The output smoothed by the low-pass filter 55 is further applied to a second low-pass filter (LPF-2) via a peak removal switch 56. Thus, the phase comparison output is smoothed to a DC error voltage and applied to the voltage controlled oscillator (VCO) 107.

The peak removing switch 56 is a switch 53 for removing a large AC component remaining even if a high-frequency component is removed to some extent by the first low-pass filter 55.
Output of the first low-pass filter 55 is blocked only during the period when the output of the first low-pass filter 55 is at the “L” level. The error voltage smoothed to DC in this manner is applied to the VCO 58, and the frequency of, for example, 1820 times the horizontal synchronization signal HSYNC is changed to the VCO 58.
58 will occur.

The frequency signal generated from the VCO 58 is frequency-divided by 1/1820 by the counter 102 and the decoder 103 in the field double speed timing controller 41, and the frequency-divided signal is used as the reference signal REF by the phase comparator 5
4 and the horizontal synchronization signal extension circuit 52. This reference signal REF is, as described above, the horizontal synchronization signal HSYNC.
Is applied to the phase comparator 54 and passes through the phase comparator 54 to be output to the first low-pass filter 55.

In the PLL circuit thus configured, when the error voltage is low, the VCO 58 operates to lower the generated signal frequency, and when the error voltage is high, the VCO 58 operates to increase the generated signal frequency. A clock synchronized with the synchronization signal HSYNC and multiplied by, for example, 1820 can be obtained. Horizontal synchronization signal HSYN
The frequency obtained by multiplying C by 1820 is about 28.6 MHz, which is eight times the color subcarrier frequency fsc.
Further, the output of the second low-pass filter 57 is also applied as an error voltage to the PLL circuit of the deflection system via the buffer circuit 59.

FIG. 2 shows an operation waveform diagram of the PLL circuit. 3A shows the waveform of the horizontal synchronizing signal HSYNC output from the switch 53, and FIG.
It is a waveform of a signal obtained by dividing the output of the VCO 58 as the EF. (C) shows the waveform of the phase comparison output signal output from the phase comparator 54. The waveform of the phase comparison output signal output from the switch 53 is the period during which the horizontal synchronization signal HSYNC applied from the switch 53 is at the “L” level.
It has a waveform that has passed the reference signal REF. (D)
Is an output signal waveform of the first low-pass filter 55,
This is a signal from which the high frequency component of the output of the phase comparator 54 has been removed.

FIG. 5E shows the waveform of the signal output from the peak removal switch 56, and the first low-pass signal during the period when the horizontal synchronizing signal HSYNC output from the switch 53 shown in FIG. This is a signal in which the output of the filter 55 is blocked. Further, (f) is the waveform of the error voltage signal output from the second low-pass filter 57,
The output of the peak elimination switch 56 is smoothed into a DC signal by the second low-pass filter 57.

FIG. 3 shows operation waveforms of the PLL circuit when the cycle of the horizontal synchronization signal HSYNC changes. (A) of this figure is the separated horizontal synchronization signal HSYNC. At the time of the section A in the middle, a synchronization discontinuous section during playback of the VTR (HSYNC having a length of about 140% of the normal state) occurs. (B) shows a reference signal REF that follows the input horizontal synchronization signal HSYNC, and it can be seen that the lock has been lost at the point A shown in (a).

(C) shows the output signal of the phase comparator 54, and the horizontal synchronizing signal HSY shown in (a) as shown by (a) in the horizontal synchronizing discontinuity period, as shown by the arrow B in the pulse width of the phase comparing output signal.
It can be seen that the pulse width is wider than the NC pulse width. This pulse width is a width from the falling edge of the reference signal REF shown in (b) to the rising edge of the horizontal synchronization signal HSYNC shown in (a).

(D) is the error voltage output from the second low-pass filter 57, and B is the error voltage shown in (c).
Since the error voltage greatly changes at the point of time and the phase comparison output increases, the rate of change becomes steep, and at the point D at which the image is displayed on the screen at the point PL,
Since the L circuit reaches the pull-in range as shown in (c), an image without image distortion is displayed on the screen.

FIG. 4 shows a detailed circuit of the horizontal synchronizing signal extension circuit. In this figure, a reference signal REF is inverted by a knot circuit 74 and supplied to a flip-flop (hereinafter, referred to as FF) 71 as a clock. The FF 71 operates to latch the signal applied to the D terminal at the rising edge of the clock. The reference signal REF inverted by the knot circuit 74 is further inverted by the knot circuit 75 and becomes the original reference signal REF, which is applied to the D terminal and the clear terminal (CLR) of the FF 72. Therefore,
The FF 72 is cleared when the reference signal REF is at "L" level.

On the other hand, the horizontal synchronizing signal HSYNC is
Is supplied to the input terminal of the NOR circuit 73 and inverted by the NOT circuit 76 and the FF 71
Is applied to the preset (PR) terminal. The inverted output XQ of the FF 71 and the Q output of the FF 72 are applied to the input terminals of the NOR circuit 73. Furthermore, FF
The Q output of 72 is applied to the D terminal of FF71.

FIG. 5 shows the operation waveforms of the horizontal synchronizing signal extension circuit shown in FIG. 4. FIG. 5A shows a case where the horizontal synchronizing signal HSYNC changes to a low frequency and the lock is lost. Since the falling edge of the reference signal REF precedes the falling edge of the horizontal synchronization signal HSYNC, the FF 71 latches the Q output of the FF 72 input to the D terminal by the falling edge of the reference signal REF. At this time, since the Q output of the FF 72 is in a cleared state, the FF 71 latches the “L” level, and the inverted output XQ of the FF 71 becomes “H” as shown in FIG.
And input to the NOR circuit 73. Therefore, the output of the NOR circuit 73 is inverted to “L” as shown in FIG.

Next, when the horizontal synchronizing signal HSYNC falls, the FF 71 is preset and inverted to "L". However, since the horizontal synchronizing signal HSYNC inverted by the knot circuit 76 is input to the NOR circuit 73. , Noah circuit 7
The output of No. 3 maintains the “L” level. The FF 72 operates at the rising edge of the clock.
2 does not work. Then, when the horizontal synchronization signal HSYNC is inverted and rises, the FF 72 operates to latch the reference signal REF applied to the D terminal, but the Q output of the FF 72 is still low because the reference signal REF is at the “L” level. Maintain the “L” level. However, since the output of the NOT circuit 76 is inverted to “L”, the output of the NOR circuit 73 is inverted to “H”.

As described above, the horizontal synchronizing signal H is set to a low frequency.
When the SYNC changes and the lock is released, the reference signal RE is output.
A horizontal synchronizing signal whose pulse width is extended from the falling edge of F to the rising edge of the horizontal synchronizing signal HSYNC is output. The output of the phase comparator 54 at this time is
Since the NOR circuit 73 outputs the reference signal REF during the “L” level period, the “L” level is output during that period as shown in “output of SW54” in the figure. This output has an expanded pulse width as compared with the output of the conventional phase comparator shown in the figure, so that the time from the loss of lock to the pull-in can be reduced as described above.

FIG. 5B shows a state in which the horizontal synchronization signal HSYNC is normally synchronized. In this case, the horizontal synchronizing signal HSYNC is inverted to be at “L” level, so that the FF 71 is preset, and the inverted output XQ is maintained at “L” level, but the output of the knot circuit 76 is at “H” level. Therefore, the output of the NOR circuit 73 is inverted to the “L” level. Next, when the reference signal REF falls, the FF 71 attempts to perform a latch operation. However, since the state where the preset signal is applied to the preset terminal continues, the FF 71 does not operate. Therefore, NOR circuit 73 maintains the “L” level.

When the horizontal synchronizing signal HSYNC rises, the output of the knot circuit 76 is inverted to "L".
The output of the NOR circuit 73 is inverted to “H”. At this time, FF
Since the D terminal of the FF 72 is at the “L” level, the FF 72
Maintain the “L” level. In this case, the output of the phase comparator 54 is the same as the output of the conventional phase comparator, and the accuracy as in the prior art is guaranteed.

FIG. 5C shows a case where the horizontal synchronizing signal changes to a high frequency and the lock is lost. In this case, when the horizontal synchronizing signal HSYNC falls, the output of the knot circuit 76 becomes “H” level, and the NOR circuit 7
3 is at the "L" level. When the rising edge of the horizontal synchronization signal HSYNC rises before the falling edge of the reference signal REF, the FF 72 latches the “H” level input to the D terminal by the rising edge of the horizontal synchronization signal HSYNC. For this reason,
Even if the output of the NOT circuit 76 is inverted to the “L” level, the output of the NOR circuit 73 maintains the “L” level.

Next, when the reference signal REF falls, F
F72 is cleared, the output Q is inverted to “L”, all inputs of the NOR circuit 73 are at “L” level, and the outputs are inverted to “H” level. Note that the FF 71 performs a latch operation at this time, but since the input of the D terminal is at the “H” level when the reference signal REF falls, the inverted output X
Q maintains the “L” level.

As described above, when the horizontal synchronizing signal HSYNC changes to a high frequency and loses lock, the horizontal synchronizing signal whose pulse width is expanded from the falling edge of the horizontal synchronizing signal HSYNC to the falling edge of the reference signal REF. A signal is output. At this time, since the reference signal REF is output while the NOR circuit 73 is at the “L” level, the output of the phase comparator 54 is at the “H” level as shown as “output of SW54” in FIG. You. This output is
Compared to the output pulse width of the conventional phase comparator shown in the figure, an output with an expanded pulse width is obtained, so that the time from loss of lock to pull-in can be reduced as described above. I can do it.

FIG. 6 shows a high-definition television receiver as an example of a television receiver equipped with the PLL circuit of the present invention. In this figure, 1 is a tuner unit, 2 is a video signal processing unit, and 3 is a digital signal processing unit that performs field double speed aspect conversion processing. A signal received by the tuner 1 or a composite video signal of the NTSC or PAL system input from an external video device is supplied to the video signal processing unit 2 via the input switching unit SW1, subjected to Y / C processing, etc., and subjected to digital signal processing. It is input to the unit 3.

NT output from digital signal processing unit 3
The SC or PAL video signal is supplied to the video signal processing unit 4 through the switching unit SW4, and is converted into R, G, and B signals as CR signals.
It is supplied to T7. Further, the horizontal synchronizing signal and the vertical synchronizing signal from the digital signal processing unit 3 are supplied to the deflection processing circuit 6 via the switching unit SW5, a deflection current is generated, and the deflection current is supplied to the deflection coil unit 8.

The input signal of the HD (High Definition) decoder or the signal received by the tuner 1 is transmitted to the switching unit SW3.
Is input to an HD decoder (e.g., a MUSE decoder) via an interface, and a decoded output from the HD decoder or an input signal from an HD video device is selected by an input switching unit SW2. The HD video signal is supplied to the video signal processing unit 4 via the switching unit SW4, and the horizontal and vertical synchronizing signals extracted from the HD video signal are supplied to the deflection processing circuit 6 via the switching unit SW5. Further, the digital signal processing unit 3
The error voltage of the line-locked PLL circuit that generates the system clock is applied to the deflection processing circuit 6 via the switching unit SW6.

FIG. 7 shows the digital processing unit 3 for performing the field double-speed aspect conversion processing in detail. In this figure, the luminance signal Y and the color difference signals RY, BY separated by the video signal processing unit are low-pass filters 10, 20, 30.
The high frequency is removed by the analog-digital converter (A / D
Converters) 11, 21, 31 convert the signals into digital signals. The converted luminance data and chrominance data are converted under the control of a write control signal (WriteControl).
For example, the field memories 12, 22, 32 are written by a write clock WCK1 of 4 fsc (about 14, 3 MHz).
Are written respectively. This field memory 12,
22 and 32 are read out by a clock WCK0 of 8 fsc (about 28, 6 MHz) having a frequency twice as high as that of the write clock WCK1, and become double-speed luminance data and color difference data.

Next, in the aspect conversion section, 3
In order to compress the data for 時間 hour, the signals are written into the line memories 13, 23 and 33 with the clock WCK0, respectively, and the line read control signal (Line Read Control) is read on the read side.
Under the control, the luminance data and the chrominance data are read and compressed by a 4/3 clock RCK. In a non-compression mode such as zoom or full, uncompressed luminance data is reproduced using the clock WCK0 in this reading operation. Next, these digital data are subjected to addition of a frame signal at the time of normal display and replacement processing of a blanking section by a time compression control section 42, and are sent to digital-analog converters (D / A converters) 14, 24 and 34. It becomes an analog signal. These analog signals are a luminance signal 2 and a color difference signal 2R-
Y, 2B-Y as low-pass filters 15, 25, 35
Is output via.

The system clock required for the above digital processing is created by the two PLL circuits 40 and 43 shown in FIG. One PLL circuit (PLLW) 40 for generating the write clock WCK0 receives the horizontal synchronization signal HSYNC separated from the composite synchronization signal CSYNC in the field double speed timing controller 41, and multiplies the horizontal synchronization signal HSYNC by 1820 to 8fsc (about 8 fsc). 28, 6 MHz) write clock W
Generates CK0. This clock WCK0 is supplied to the field double-speed timing controller 41, is divided by a counter and a decoder, and is divided into a 4 Wsc clock WCK1 and a 1/11820 reference signal REF.
Is created.

Next, the other PLL circuit (PLLR) 43 for generating the read clock RCK is supplied with the double frequency horizontal synchronizing signal 2HSYNC supplied from the field double speed timing controller 41 and multiplied by 1214 to 8fsc. 4/3 times the frequency (about 38, 1 MH
A read clock for z) is generated. This clock R
The CK is supplied to the time compression control unit 42, is used as the read clock RCK when the normal display mode is selected, and generates the reference signal Ref divided by 1/1214. The time compression control circuit 42 has a vertical synchronizing signal VSY for performing the double speed processing in the vertical direction.
NC is supplied.

FIG. 8 shows an image displayed on the screen when the field double speed aspect conversion process is performed. (A) of this figure is an image when an NTSC or PAL video is displayed in full, and the CRT of a high-definition television receiver is used.
Has an aspect ratio of 16: 9, so that the image is extended in the horizontal direction. (B) is a normal display,
The image has a black frame added to the remaining portions on both sides. (C) is a zoom display, in which a normal image is displayed on the entire screen in the horizontal direction by cutting the top and bottom of the screen in the vertical direction.

Although the application example of the present invention has been described, the PLL circuit of the present invention can be applied not only to an HD television receiver such as a high definition television, but also to a video processing device using a line lock PLL circuit. Can be applied. Further, even when the video processing circuit is constituted by a dedicated LSI, by attaching the PLL circuit of the present invention to this LSI externally, the time required for pull-in even if the lock is released can be reduced. When the signal input to the PLL circuit is a thin pulse signal, the present invention can be applied not only to the video processing apparatus.

[0048]

Since the present invention is configured as described above, when the lock is lost, the pulse width of the input signal is expanded in accordance with the amount of shift between the input signal and the reference signal REF, and the section for turning on the phase comparator is provided. The spreading and the saturation of the error voltage are prevented. Therefore, an error voltage corresponding to the degree of the deviation is obtained, and the pull-in operation is performed quickly. As a result, the time required for the convergence of the error voltage is greatly reduced, and when applied to a video processing apparatus, the image bending at the time of discontinuous synchronization during VTR reproduction can be improved.

For example, when applied to an HD television receiver of the type which performs field double-speed aspect conversion processing, the lock range of static characteristics is about 1.6 times or more , and the pull-in range is about
It can be improved by 1.3 times or more . In addition, the convergence time corresponding to the improvement of the image bending of about 50% or more can be achieved in the dynamic characteristics, and the same amount can be improved on the screen. The PLL circuit of the present invention is a dedicated LSI for video processing.
It is possible to build a small and inexpensive circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit according to the present invention.

FIG. 2 is an operation waveform diagram of the PLL circuit of the present invention.

FIG. 3 is an operation waveform diagram of the PLL circuit of the present invention when the lock is released.

FIG. 4 is a detailed horizontal synchronizing signal extension circuit.

FIG. 5 is an operation waveform diagram of the horizontal synchronization signal extension circuit.

FIG. 6 is a system diagram of a high-vision receiver.

FIG. 7 is a block diagram of a digital processing unit that performs field double-speed aspect conversion processing.

FIG. 8 is a diagram showing a screen on which field double-speed aspect conversion processing has been performed.

FIG. 9 is a block diagram of a conventional PLL circuit.

FIG. 10 is an operation waveform diagram of a conventional PLL circuit.

FIG. 11 is an operation waveform diagram of the conventional PLL circuit when the lock is released.

FIG. 12 is a diagram showing a screen on which image bending has occurred.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 tuner 2 video signal processing unit 3 digital processing unit for performing field double-speed aspect conversion processing 4 video signal processing unit 5 MUSE decoder 6 deflection processing circuit 7 CRT 8 deflection coil 10, 20, 30 low-pass filter 11, 21, 31 A / D converter 12, 22, 32 Field memory 13, 23, 33 Line memory 14, 24, 34 D / A converter 15, 25, 35 Low-pass filter 40, 43 PLL circuit 41 Field double-speed timing controller 42 Time compression Control circuit 51, 101 Horizontal synchronization signal separation circuit 52 Horizontal synchronization signal extension circuit 53 TV / VTR selection switch 54, 105 Phase comparator 55, 57, 106 Low-pass filter 56 Peak removal switch 58, 107 VCO 59, 104 Buffer 60 , 102 Counter 6 1,103 decoder 71,72 flip-flop 73 NOR circuit 74,75,76 knot circuit SW1, SW2, SW3, SW4, SW5, SW6 switching unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L 7/10 H03L 7/08 H04N 5/06 H04N 7/01

Claims (3)

(57) [Claims] 1. A when applied input signal is in one level,
A phase comparator that is controlled by the input signal and passes a reference signal; a low-pass filter that smoothes the output of the phase comparator; and a voltage-controlled oscillator that oscillates at a frequency corresponding to the output level of the low-pass filter And a frequency divider for dividing the output of the voltage controlled oscillator to generate the reference signal as a rectangular wave , wherein the output signal obtained by multiplying the frequency of the input signal is obtained from the voltage controlled oscillator. In the circuit, when the edge of the reference signal precedes the leading edge of the input signal, a pulse having a width from the edge of the reference signal to the leading edge of the input signal is added to the input signal, and When the edge precedes the edge of the reference signal, a digital signal having an input signal width for adding a pulse having a width from the trailing edge of the input signal to the edge of the reference signal to the input signal.
And a pulse width obtained as an output of the digital extension circuit.
A PLL circuit characterized in that an applied input signal is applied to the phase comparator . Wherein the low-pass filter is separated into two, the input signal is one that is output from the extension circuit therebetween Les
2. The PLL circuit according to claim 1, further comprising a peak signal removing unit that blocks a signal from the preceding low-pass filter during the period of the bell . 3. The horizontal synchronizing signal separated from the video signal
When the level is higher, the reference signal is controlled by the horizontal synchronization signal.
, A low-pass filter for smoothing the output of the phase comparator , and oscillation at a frequency corresponding to the output level of the low-pass filter
And a frequency- divided output of the voltage-controlled oscillator.
A frequency divider for generating a reference signal, and an edge of the reference signal being earlier than a leading edge of the horizontal synchronization signal.
When performing a horizontal synchronization signal from the edge of the reference signal
A pulse having a width up to the leading edge of is added to the horizontal synchronization signal,
The trailing edge of the horizontal sync signal is ahead of the edge of the reference signal
The horizontal sync signal from the trailing edge of the horizontal sync signal.
A pulse with a width up to the edge of the reference signal is used as the horizontal synchronization signal.
A digital extension circuit having a horizontal synchronization signal width to be added, and a pulse width obtained as an output of the digital extension circuit.
Applying the applied horizontal synchronization signal to the phase comparator.
The output signal obtained by multiplying the frequency of the horizontal synchronization signal by
Is obtained from the above voltage controlled oscillator.
Provided, based on the output signal from the PLL circuit, the video
Generate multiple clocks for digital processing of signals
A video display device .