JPS61281694A - Pll circuit - Google Patents

Abstract

PURPOSE:To obtain a stable circuit without step out by providing a pulse shaping circuit to compress so that the pulse width of a vertical synchronizing pulse in a composite synchronizing signal may be almost equal to the pulse width of the horizontal synchronizing pulse, and impressing the output signal of said pulse shaping circuit through a 1/2 H killer circuit to a phase comparing circuit. CONSTITUTION:Into an input terminal 2, the composite synchronizing signal, which includes a horizontal synchronizing pulse A of the prescribed pulse width shows in the figure (a), an equal pulse B of the pulse width narrower than the horizontal synchronizing pulse and a vertical synchronizing pulse C of the pulse width wider than the horizontal synchronizing pulse, is impressed. The composite synchronizing signal is shaped by a pulse shaping circuit 1, and at the output edge of said pulse shaping circuit 1, the pulse string of the pulse with an almost constant pulse width as shown in the figure (b) is obtained. The pulse obtained at the output of a 1/2 H killer circuit 4 is impressed to a phase comparing circuit 7, and the phase is compared with the output of a frequency dividing circuit 6 shown in the figure (c). The oscillating frequency and the phase of a VCO 5 are controller, and the output signal of 320 H synchronized to the horizontal synchronizing pulse is obtained at an output terminal 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a PLL (phase locked loop) circuit suitable for use in low frequency conversion of chroma signals in a VTR (video tape recorder). In particular, it is intended to prevent synchronization of the PLL circuit caused by equivalent pulses and vertical synchronization pulses that have different pulse widths from the horizontal synchronization pulses. Figure 7-24, page 95 of ``rNHK Home Video Technology'' published by Japan Publishing Association, shows a PL for obtaining an output signal synchronized with a composite sync signal consisting of a horizontal sync pulse, an equivalent pulse, and a vertical sync pulse.
An L circuit h'' is described.The PLL circuit has a VC
0 (voltage controlled oscillator), a frequency dividing circuit that divides the output signal of the VCO, and a phase comparison circuit that compares the composite synchronization signal with the output signal of the frequency dividing circuit and generates an error signal. By applying the error signal to the ■Co, the oscillation frequency and phase of the VCO are made to match the frequency and phase of the horizontal synchronization pulse in the composite synchronization signal.

e→ Problems to be Solved by the Invention However, the composite synchronization signal may include an equivalent pulse having a narrower pulse width than the horizontal synchronization pulse and a vertical synchronization pulse having a wider pulse width than the horizontal synchronization pulse. Therefore, when the VCO is phase-locked to the horizontal synchronization pulse, when the equivalent pulse or the vertical synchronization pulse is applied to the phase comparison circuit, an error signal is generated from the phase comparison circuit, and the oscillation frequency and There was a drawback that the phase changed. For example, as shown in FIG.
When a phase comparison is made between the composite synchronization signal consisting of O and the signal shown in Figure 3 (b) obtained by frequency dividing the output signal of the VCO, the signal shown in Figure 3 (/→) is the output of the phase comparator circuit. However, the positive and negative signals obtained for the horizontal synchronizing pulse (5) become zero by passing through a low-pass filter, so they do not become error signals, but the signal obtained for the equivalent pulse 03) (Bl is a negative error signal) Since the signal obtained with respect to the vertical synchronization pulse (Q (q is a positive error signal), there was a risk that the PLL circuit would become out of synchronization.

By the way, if a circuit that combines a differentiating circuit and a slicer of a predetermined level is used, it is possible to compress the pulse width of a wide pulse width. , the pulse width of the vertical synchronizing pulse can be made approximately equal to the pulse width of the horizontal synchronizing pulse. However, even if the circuit described above is used, it is not possible to extend the pulse width of the equivalent pulse, and the risk of the PLL circuit becoming out of synchronization still remains.

B) Means for solving the problem The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points. A pulse shaping circuit is provided that expands the pulse width of the vertical synchronizing pulse in the composite synchronizing signal so that it is equal to the pulse width of the horizontal synchronizing pulse, and compresses the pulse width of the vertical synchronizing pulse so that it becomes approximately equal to the pulse width of the horizontal synchronizing pulse, and the output signal of the pulse shaping circuit is
-The pulse is applied to the phase comparator circuit through the H killer circuit, and the starting point is characterized by (e) Effect: According to the present invention, the pulse width of the pulse applied to the phase comparator circuit is made substantially constant. Therefore, the PLL circuit can operate normally without malfunction.

(F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention, in which (1) shows an input terminal (2) to which a composite synchronization signal is applied and a clock terminal (3) to which a clock pulse is applied. (4) is a "-H killer circuit that deletes a part of the equivalent pulse contained in the output signal of 11"; (5) is a pulse shaping circuit that effectively divides the 320H oscillation frequency. The frequency dividing circuit (7) is a phase comparison circuit that compares the phase of the output signal of the TH Kifu circuit (4) with the phase of the output signal of the frequency dividing circuit (6) and generates an error signal.

and (8) converts the output signal of the phase comparator (7) to the V
This is a loop filter for applying to CO(5).

The input terminal (2) receives a horizontal synchronizing pulse (8) having a predetermined pulse width as shown in FIG. A composite synchronization signal including a vertical synchronization pulse (q) having a pulse width wider than the synchronization pulse is applied.The composite synchronization signal is shaped by a pulse shaping circuit fil, and is sent to the output terminal of the pulse shaping circuit (1). In this case, a pulse train of pulses having a substantially constant pulse width as shown in FIG. 4(b) is obtained.

The output signal of the pulse shaping circuit (1) is applied to the lH killer circuit (4), where one equivalent pulse is removed. Therefore, I
At the output end of the n-killer circuit (4), only pulses having a substantially constant pulse width with the same period of 1/2H are generated. Said 1/2
The pulse obtained at the output of the H killer circuit (4) is applied to a phase comparator circuit (7), and its phase is compared with the output signal of the frequency divider circuit (6) shown in FIG. (7) means that the output signal of the TH Kifu circuit (4) is rH
At J, the output signal of the frequency dividing circuit (6) is rLJO output r
The output signal of the ``-H killer circuit (4) is rH.
When the output signal of the frequency dividing circuit (6) is rHJ at J, the output "
Since the output signal "0" is generated at other times, the output signal of the phase comparator circuit (7) is as shown in FIG. 4). The output signal of is passed through the loop filter (8) as an error signal to the VCO (
5), the oscillation frequency and phase of the VCO (51) are controlled, and an output signal of 320H synchronized with the horizontal synchronizing pulse is obtained at the output terminal (9).

The pulse shaping circuit +1> is as shown in FIG.
11 and a first AND gate which is the AND of the ζ output of the first flip-flop circuit 9 and the clock pulse applied to the clock terminal α2 (131 and the clock obtained at the output terminal of the first AND gate α). a counter α (a) for counting pulses and a first decoder Kasumi that generates an output signal when the count of the counter a4 reaches a first predetermined value;
a second decoder tte that generates an output signal when the count of the counter α4 reaches a second predetermined value; and a second AND gate αη that generates a set signal in response to the input pulse and the output signal of the first decoder α9. , a second flip-flop circuit α second using the output signal of the second AND gate αη as a set signal and an output signal of the second decoder (161) as a reset signal; Or game H1 and 5 that takes OR with ζ output
A third AND gate (A) which takes an AND between the output signal of the OR gate (1j) and the ζ output of the first flip-flop circuit (111); It also has a NOR gate that generates the reset signal tx% of the counter α4.

When the horizontal synchronizing pulse shown in FIG. 4(a) is applied to the input terminal (lω), the 17th lip-flop (1
1 is sected and the ζ output becomes "H".

The 27th Rikupu 70 Tsubu circuit a sand has been reset,
Since the output of the first flip-flop circuit αD becomes rHJ, the output of the third AND gate becomes rHJ, and the output signal becomes rHJ. When the ζ output of the first flip-flop circuit 01) rises simultaneously with the horizontal synchronizing pulse, it becomes rHJ.

A clock pulse is applied to the counter (14 VC) through the first AND gate α, and counting of the counter α4 is started. When the count of the color/return 0 progresses and reaches a first predetermined value, the first decoder An output signal is generated from α.

The generation of the output signal from the first decoder is set at a time earlier than the falling edge of the horizontal synchronizing signal and later than the falling edge of the equivalent pulse.
When the output signal 9 is generated, the output of the second AND gate aη becomes rHJ.

The 27th lip-flop circuit a barrel is set. Therefore, the ζ output of the 27th lip-flop circuit αυ is “L”.
However, since the horizontal synchronization signal still exists, the output of the OR gate α value continues to be "H", and the state of the output terminal (21) does not change. More time has passed.

When the horizontal synchronization signal falls, the OR gate (output 6 of 19
ZrLJ, and the output of the third AND gate ■ also becomes rLJ, so the output signal diagram shown in Figure 4 (B) is obtained at the output terminal Qυ in response to the horizontal synchronizing pulse (A) in Figure 4 (A). It will be done. When a certain amount of time has elapsed since the fall of the horizontal synchronizing signal and the value of the counter I reaches a second predetermined value, an output signal is generated from the second decoder side.

The first and second flip-flop circuits (1B and 0SA) are reset, and the circuit of FIG. 2 returns to its initial state.

Next, when the equivalent pulse fB) in FIG. 4(a) is applied to the input terminal, the first flip-flop circuit 9 is set at the rising edge of the pulse fB), and when the ζ output becomes "H", the second flip-flop circuit 9 is set. Flip-flop circuit (1 dark house reset,
Since the ζ output is 6ZrHJ.

In response to the rise of the equivalent pulse, the output terminal Q1) becomes rH.
It becomes J. After that, even if the equivalent pulse falls, the second
7 Rip-flop circuit α117)ζ output maintains rHJ, and the output of OR gate a also maintains rHJ, so
The output signal obtained at the output terminal Qυ also maintains "H".

When the ζ output of the 17th lip-flop circuit α9 reaches rHJ, the counter α starts counting, and when the value of the counter α reaches the first predetermined value, the first decoder a9 outputs rHJ.
Although the output occurs.

At that point, the human power signal is rLJ, so the second
The AND gate (181 does not generate an output, and the second flip-flop circuit α is not set. The counter (14
When the count of 1 progresses and reaches the second predetermined value, the rHJ output is generated from the second decoder αe, and the first flip-flop circuit 0D is reset, so its ζ output becomes rLJ, and the third AND gate ■ The output of
As soon as the output signal (Bl) shown in FIG. 4(B) is obtained, the vertical synchronizing pulse (C) in FIG. 4(A) is applied to the input terminal (Il). The decoder αD is set, the ζ output becomes rHJ, and the output terminal 3υ becomes rHJ as in the case of 1 equivalent pulse 03).Then, the count of the counter α advances, and the rHJ output is generated from the first decoder α9. Then, the second AND gate α
η is selected and the ζ output of the 27th lip-flop circuit 08 becomes rLJ, but since the input signal maintains the "H" state, the state of the output signal does not change. The value along the counter α reaches the second predetermined value, and the output of the second decoder αe becomes r
When HJ is reached, the first and second flip-flop circuits aυ
and α is reset, and the ζ output of the 17th lip 70 cup circuit αB becomes rLJ, so the output signal also becomes rLJ.
become. Therefore, the output signal (C) shown in Figure 4 (B) is output to the output terminal Qυ in response to the vertical synchronizing pulse (O in Figure 4 A).
b'-obtained. Therefore, by using the pulse shaping circuit shown in Fig. 2, an equivalent pulse with a narrower pulse width than the horizontal sync pulse and a vertical sync pulse with a wider pulse width than the horizontal sync pulse can be made to have approximately the same pulse width as the horizontal sync pulse. I can do it.

FIG. 5 shows a specific circuit example of the phase comparator circuit (7) in FIG. the first input terminal to which c
! 3 is the output signal (
A second input terminal to which the waveform shown in FIG. 4 (b) is applied.

c24 is a Nant gate, @ is an inverter, @ is an AND gate 5 @ is a P-channel FET, @ is an N-channel FE
T and 4 are output terminals. Now the first input terminal is “L”
'', if the second input terminal is rHJ, the P-channel FET@ is turned off, the N-channel FET@ is turned on, and the output terminal becomes rLJ. Also, the first input terminal (
C) is "H".

If the second input terminal is "H", P channel FzTnb: on, N channel FET @ is off, and output terminal (2!I becomes rHJ. In other cases, P channel FET Both the (G) Effects of the Invention As described above, according to the present invention, it is possible to generate an output signal that is correctly synchronized with the horizontal synchronization signal in the composite synchronization signal. P.L.
Can provide L circuit. In particular, since the PLL circuit is not adversely affected by the equivalent pulse or the vertical synchronization signal, the present invention can provide a stable PLL circuit that does not lose synchronization.

Furthermore, as in the embodiment, if the falling edge of the horizontal synchronizing pulse is not affected by the quantization error of the counter, the stability of the PLL circuit can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the pulse shaping circuit, and FIG.
A) to (/ are characteristic diagrams for explaining the conventional circuit, FIG. 4 (A) to) are characteristic diagrams for explaining the present invention,
and FIG. 5 is a circuit diagram showing a specific circuit example of the phase comparison circuit of FIG. 1. Explanation of main drawing numbers (1)...Pulse shaping circuit, (5)...VCOl
(Power...phase comparison circuit, (8)...loop filter. Applicant: Sanyo Electric Co., Ltd. and one other representative, patent attorney: Yasuo Sano Figure 1 Figure 3 A B C Figure 4 AB C

Claims (1)

[Claims] (1) An input terminal to which a composite synchronization signal is applied, and the pulse width of the equivalent pulse in the composite synchronization signal is expanded to be approximately equal to the pulse width of the horizontal synchronization pulse, and the pulse width of the vertical synchronization pulse in the composite synchronization signal is A pulse shaping circuit that compresses the pulse width to be approximately equal to the pulse width of the horizontal synchronizing pulse, a 1/2H killer circuit connected to the output end of the pulse shaping circuit, a VCO, and an oscillation output signal of the VCO. a frequency dividing circuit that divides the frequency, a phase comparison circuit that compares the phases of the output signal of the 1/2H killer circuit and the output signal of the frequency dividing circuit and generates an error signal, and applies the error signal to the VCO. 1. A PLL circuit, comprising: a loop filter for controlling the synchronization, and an output signal synchronized with a horizontal synchronization pulse in the composite synchronization signal is obtained at an output end of the VCO.