JPH0681044B2 - Video signal frequency converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video signal frequency conversion device, and can be applied to a device for processing a video signal such as a video tape recorder (VTR).

[Background technology and its problems]

For example, in a VTR, an AFC (automatic frequency control) circuit is used to stabilize the frequency of a signal used when processing a video signal. The basic configuration is that the frequency output of the VCO circuit (voltage controlled oscillator) is divided by a frequency divider, the divided output is compared with the phase of the frequency signal to be stabilized, and the VCO circuit oscillates according to the deviation. The frequency is controlled so that the deviation becomes 0, and the VC
The oscillation output of the O circuit is sent out as a stabilized frequency output signal.

By the way, since a device such as a VTR has electric circuit components formed on an IC, it is desirable that the AFC circuit also has a configuration suitable for use as an IC.

[Object of the Invention]

The present invention has been made in consideration of the above points, and an object of the present invention is to provide a frequency conversion device for a video signal, which is suitable for IC and has high AFC accuracy.

[Outline of Invention]

In order to achieve such an object, in the present invention, the oscillation frequency output signal is divided to divide one cycle period of the horizontal synchronizing signal into a plurality of time windows, and the rising edge of the horizontal synchronizing signal with respect to the reference position of the predetermined time window is divided. A correction signal is formed according to the amount of phase shift, and a first pulse having a positive or negative signal level is generated in synchronization with the horizontal synchronization signal and is synchronized with the oscillation frequency output signal of the VCO circuit. Then, a second pulse having a negative or positive signal level is generated, a control signal for the VCO circuit is formed by sequentially using the first and second pulses, and the phase of the horizontal synchronizing signal is the oscillation frequency output of the VCO circuit. When the phase advances from the reference phase of the signal, the pulse width of the first pulse is expanded according to the phase advance amount, and when the phase of the horizontal synchronizing signal lags the reference phase of the oscillation frequency output signal of the VCO circuit, the phase delay So as to enlarge the pulse width of the second pulse in accordance with.

〔Example〕

The present invention will be described in detail below with reference to the drawings as an embodiment when the present invention is applied to an AFC circuit used for a color signal system in a VTR recording circuit. In FIG. 1, the carrier color signal S1 (frequency f _C ) obtained from the input video signal through the ACC circuit (automatic chroma level control circuit) is converted into the low frequency conversion color signal S3 (frequency) by the carrier signal S2 in the frequency conversion circuit 1. f _S ), and the low-frequency converted color signal S3 is separately recorded on the tape together with the luminance signal.

In the carrier frequency conversion circuit 4, the carrier signal S2 is
The oscillation output S4 of the crystal oscillator 2 of frequency f _C is divided into 1/8 frequency divider circuit 3
Frequency output signal S5 (frequency
It is obtained by frequency conversion by f _s ′) and is given after phase inversion in the PI circuit 6. By the way, this carrier frequency conversion operation is performed so as to reduce the disturbance caused by the intermodulation distortion with the FM luminance signal, which appears in the reproduced luminance signal, by the interleave effect, and the oscillation output S6 of the VCO circuit 5 (frequency 378f _H ) is divided by the 1/8 frequency divider circuit 3 to obtain the frequency f _S ′ of the frequency signal S5. Try to be.

Here, the frequency output signal S6 of the VCO circuit 5 must have a frequency f _H, that is, exactly the same as 378 times the frequency of the horizontal synchronizing signal, and therefore the frequency control circuit 10 having the following configuration is used.
Is configured. That is, the frequency control circuit 10 divides the frequency output signal S6 of the VCO circuit 5 by the 47 frequency divider 11 composed of a variable frequency divider, and the frequency division output S7 is divided by the AFC circuit 12 in the horizontal synchronizing signal HSYNC (frequency f _H ) compared to.
The AFC error signal S8 of the AFC circuit 12 controls the voltage conversion circuit 14 of the charge pump circuit configuration by driving the AFC current source 13 and controlling its output current signal S9, and the output voltage of this voltage conversion circuit 14 is controlled. V _C is given to the VCO circuit 5 as a control signal.

Here, the 47 frequency divider 11 counts the pulses of the frequency output signal S6 of the VCO circuit 5 for eight cycles as shown in FIG. 2 (A), and outputs it as a time division output S7 as shown in FIG. 2 (B). The first output pulse M1 is generated, and subsequently the pulse of the output signal S6 is counted for 10 cycles as shown in FIG. 3 (A).
As shown in FIG. 3 (B), the second pulse M2 is generated, and subsequently, the pulse of the frequency output signal S6 is repeatedly counted for 8 cycles as shown in FIG. 2 (A). And the third to 47th pulses M3 to M47 are generated. Thus, the 47 frequency divider 11 counts the frequency output signal S6 of 8 × 46 cycles during the period in which 46 pulses M1, M3 to M47 excluding the second pulse M2 are output, and also the second pulse M6. When the output signal S6 is transmitted, the output signal S6 for 10 × 1 cycles is counted, and thus, the divided output S7 obtained by dividing (8 × 46 + 10 × 1) = 378 is obtained. Thus, the period of the 47 pulses M1 to M47 corresponding to each period of the divided output S7 becomes the period of the horizontal synchronizing signal HSYNC, that is, 1H.

Pulses M1 to M47 obtained in this way (Fig. 4 (C1)
~ (C47)) are given to the AFC circuit 12 as 47 parallel line signals.

The output pulse M2 for 10 cycles of the frequency output S6 as described above with reference to FIG. 3 is configured as the second frequency-divided output because it is VC for processing the television signal of the NTSC system.
The oscillation frequency of the O circuit 5 in order to select the 378f _H, VC in the case of processing a television signal of CCIR system instead this
Since it is necessary to select the oscillation frequency of the O circuit 5 at 375 f _H , the output signal S6 for 7 cycles is obtained as the second frequency-divided output (corresponding to FIG. 3), and thus the divided signal is obtained. The frequency divider 11 has a function as a variable frequency divider.

Thus, each period section of the frequency division output S7 of the frequency divider 11 is shown in FIG.
As shown in (A), it means that one period section 1H of the horizontal synchronizing signal HSYNC is provided with time windows M1T to M47T corresponding to the output pulses M1 to M47. AFC circuit 12 has this time window M1T
-M47T is used to generate a AFC error signal S8 in accordance with the time difference between the rising time of the horizontal synchronizing signal HSYNC and the predetermined time window, paying attention to where the rising time of the horizontal synchronizing signal HSYNC occurs in the windows M1T to M47T. It has the configuration of FIG. That is, the AFC circuit 12 has a decoder 20 that receives the frequency-divided output S7 of the frequency divider 11. As shown in FIG. 6 (A), the decoder 20 uses the horizontal synchronization signal HSYNC (FIG. 6 (B)) at this time t ₀ with reference to the start time t ₀ of the time window M24T in the time window of the frequency-divided output S7. When the rising edge of occurs, it is determined that there is no AFC error, and on the other hand, if the rising edge of the horizontal synchronization signal HSYNC does not occur at the time window before or after the time window t ₀ , the corresponding determination is made. The time data TDT having the content according to the judgment result is sent to the shift register 21 and the horizontal synchronization signal HSYN
A predetermined polarity switching signal PCH is sent to the polarity sequence switching circuit 22 for the time window in which the rising of C has occurred and the time window subsequent thereto.

First, when the rising of the horizontal synchronizing signal occurs at the reference time t ₀ as described above with reference to FIG.
As shown in FIG. 6 (C24A), the polarity sequence switching is performed for the polarity switching circuit 22 so that a positive pulse is generated in the time window M24T and a negative pulse is generated in the subsequent time window M25T. Send signal PCH. Practically, this polarity sequence switching signal PCH designates the positive polarity by the logic "H" when the 24th pulse M24 is given from the frequency divider 11, and then the 25th pulse M25 is specified. When it arrives, it is designed as a logic "L" to designate the negative polarity. The horizontal synchronizing signal HSYNC is given to the polarity switching circuit 22, and when this signal HSYNC rises to the logic "H", the polarity switching circuit 22 outputs a predetermined voltage value of the polarity designated by the polarity sequence switching signal PCH (for example, A voltage signal VV of ± 2.5 V) is applied to the output control circuit 23.

At the same time, the decoder 20 outputs the horizontal synchronization signal HSYNC at the reference point t _0.
Based on the determination that it has risen in step 2, the 2-bit logic "H" time data TDT is applied to the shift register 21, and thus the logic "H" is applied to the output terminal until the shift register 21 shifts only twice. The output control signal SC is generated and given to the output control circuit 23. At this time, the output control circuit 23 is turned on under the condition that the output control signal SC is logic "H", and the voltage signal VV sent from the polarity switching circuit 22.
To be transmitted as an AFC error signal S8.

Here, the shift register 21 receives the horizontal synchronizing signal HSYNC as a latch signal, and when the horizontal synchronizing signal HSYNC rises to the logic "H", the rise causes the time data TDT to be fetched inside and latched. Along with this, the shift register 21 is a frequency divider.
Clock pulse generated every time the time window changes from 11
When the time data TDT is latched by the shift operation by CLK, the output becomes the section logic "H" of the same number of time windows as the number of bits of the time data TDT counted from the time window at the time of the latch. Sends the control signal SC. Therefore, in the case of FIG. 6 (C24A), since the 2-bit time data TDT has been latched in the shift register 21, the output control circuit from the start time of the time window M24T to the end time of the next time window M25T.
23 will be controlled to the on state.

As described above, since the output control circuit 23 controlled to be in the ON state in the time windows M24T and M25T is supplied with the voltage signal VV that sequentially becomes positive and negative as described above, the time window is eventually output as the AFC error signal S8. A positive pulse will be obtained in M24T and a negative pulse will be obtained in the following time window M25T.

The voltage conversion circuit 14 includes a capacitor C1, a resistor R1 and a capacitor.
Composed of a charge pump consisting of a parallel circuit with a series circuit of C2, the AFC current source 13 supplies a charging current to the capacitors C1 and C2 when the AFC error signal S8 is positive and a discharging current to the capacitors C1 and C2 when the AFC error signal S8 is negative. Further, when the value is “0”, the charging / discharging current is not passed. Therefore, as shown in FIG. 6 (C24A), when the pulse widths of the positive pulse and the negative pulse are equal, the amount of current flowing into the capacitors C1 and C2 and the capacitor C1
And the amount of current flowing out of C2 are equal to each other, the charging voltage of the capacitors C1 and C2 is 0 as a whole.

Thus, when the rising edge of the horizontal synchronizing signal HSYNC coincides with the reference time t ₀ , the decoder 20 receives time data such that the positive pulse section and the negative pulse section are equal to each other as shown in FIG. 6 (C24A). Since the TDT and the polarity order switching signal PCH are sent out, the AFC error signal S8 has the result that the charging voltage of the voltage conversion circuit 14 is set to 0, whereby the VCO circuit 5
The oscillation frequency of (FIG. 1) is not changed and controlled, and its value is maintained. On the other hand, if the rising edge of the horizontal synchronization signal HSYNC deviates to a time point before the reference time point t ₀ , the decoder 20 responds to this by expanding the positive pulse width in accordance with the deviation amount, and the time data TDT And a polarity order switching signal PCH. That is, as shown in FIG. 6 (C23), if the rising edge of the horizontal synchronizing signal HSYNC advances to the time window M23T by the time T1, the decoder 20 changes the polarity to positive, positive, or negative corresponding to the time windows M23T, M24T, and M25T. Polarity change signal PCH
And the time data of logic "H" of 3 bits
The TDT is latched in the shift register 21. Accordingly, the shift register 21 causes the output control circuit 23 to output the AFC error signal S8 in which the positive pulse width is expanded by the time T1 from the rising timing of the horizontal synchronizing signal HSYNC, and thus the voltage V _C of the voltage conversion circuit 14 is changed. It rises by the amount corresponding to this positive pulse section T1. At this time, the VCO circuit 5 is controlled so that the oscillation frequency becomes high, whereby the phase of the frequency-divided output S7 of the frequency divider 11 advances, and the start time t ₀ of the time window M24T is the horizontal synchronization signal HS.
It will coincide with the rise of YNC. Thus, Fig. 6 (C
24A), the frequency control circuit 10
Becomes stable as a whole.

Next, when the rising timing of the horizontal synchronization signal HSYNC as shown in FIG. 6 (C22) is the advanced by time T2 with respect to time t ₀ to enter a time window M22T, decoder 20 time window M2
Positive, negative, positive, and positive polarity sequence switching signals PCH are sequentially sent to the polarity switching circuit 22 for 2T, M23T, M24T, and M25T, and 4-bit time data TDT of logic "H" is sent to the shift register 21. Send out. Thus, the positive pulse width of the AFC error signal S8 is the time after the rising edge of the horizontal synchronizing signal HSYNC in the time window M22T, and the time windows M24T and M25T.
For, the time width of the negative pulse is the time width of the time window M23T. Therefore, as a whole, the time width of the positive-direction pulse of the AFC error signal S8 is expanded by the amount T2 that the horizontal synchronization signal HSYNC has advanced from the time point t ₀ , and the voltage V of the voltage conversion circuit 14 is expanded by this expansion amount. _C
Is controlled so that the frequency of the VCO circuit 5 is increased by this amount, and the time point t ₀ of the frequency-divided output S7 of the frequency divider 11 is locked to the rising edge of the horizontal synchronizing signal HSYNC.

Further, as shown in FIG. 6 (C21), when the rising edge of the horizontal synchronizing signal HSYNC occurs in the time window M21T, the decoder 20 causes the time window M21T to correspond to the time T3 from the time t ₀ to the occurrence time.
Polarity switching circuit 2 for polarity order switching signal PCH designating positive, negative, positive, positive, positive polarity corresponding to M22T, M23T, M24T, M25T
It is given to 2 and time data T of logic "H" of 5 bits
The DT is latched in the shift register 21. Therefore, in this case, the voltage V _{C of the} voltage conversion circuit 14 is equal to the advanced time T3.
Will rise.

Similarly, as shown in Fig. 6 (C20), the time window M20T
When the phase of the horizontal synchronization signal HSYNC advances to the time T
The time width of the pulse in the positive direction is expanded by the amount corresponding to 4, so that the voltage V _C of the voltage conversion circuit 14 is increased.

In this way, when the phase of the horizontal synchronizing signal HSYNC advances from the reference time point t ₀ , the time width of the positive pulse of the AFC error signal S8 is expanded by the time width corresponding to the advanced time, whereby the voltage V of the voltage conversion circuit 14 is increased. _C rises, so that the oscillation frequency of the VCO circuit 5 is locked to the advanced phase.

On the other hand, when the phase of the horizontal synchronizing signal HSYNC lags behind the reference time t ₀ and the rising of the horizontal synchronizing signal HSYNC occurs during the section of the time window M24T, as shown in FIG. 6 (C24B), the decoder 20 causes the sixth Since the polarity order switching signal PCH and time data TDT similar to those described above with reference to the figure (C24A) are transmitted, AF
The time width of the negative pulse of the C error signal S8 becomes wider than the time width of the positive pulse by the time T01 corresponding to the phase delay, and accordingly the capacitor C1 of the voltage conversion circuit 14 and
Since the charging current amount of C2 decreases, the voltage V _C decreases. Therefore, at this time, the VCO circuit 5 (FIG. 1) is controlled so that its oscillation frequency becomes lower, and as a result, the divider 11
Divided output reference time point t ₀ phase delay of S7 is horizontal synchronizing signal
It will be locked at the rising timing of HSYNC.

Further, as shown in FIG. 6 (C25), if the rising timing of the horizontal synchronizing signal HSYNC occurs in the section of the time window M25T, and the rising is delayed by the time T02 with respect to the reference time point t ₀ , then the decoder 20 Is the time window M25T, M26T, M27T,
The polarity sequence switching signal PCH for designating positive, positive, negative, negative and negative polarities for M28T and M29T respectively is transmitted, and 5 bit logic "H" time data TDT corresponding to these 5 time windows. The shift register 21 is latched. Therefore, the AFC error signal S8 is the horizontal synchronization signal HSY in the time window M25T.
Positive pulse occurs during the time period after the rising edge of NC,
Further, a positive pulse having a time width of the time window M26T is generated, and a negative pulse having a time width of the time windows M27T, M28T, and M29T is generated.
As a result, the AFC error signal S8 as a whole means that the negative pulse is expanded by the time width of the time T02 when the rising timing of the horizontal synchronizing signal HSYNC is delayed from the reference time point t ₀ , and accordingly, the voltage is increased. The voltage V _C of the conversion circuit 14 is the time width T0
Therefore, the oscillation frequency of the VCO circuit 5 is controlled to be lowered by this amount. Therefore, also in this case, the frequency control circuit 10 can lock the phase of the horizontal synchronizing signal HSYNC to the phase of the oscillation output signal S6 of the VCO circuit 5.

Further, as shown in FIG. 6 (C26), when the rising timing of the horizontal synchronizing signal HSYNC is further delayed and occurs in the section of the time window M26T, the negative pulse section is expanded by the delayed time T03. The decoder 20 causes the time windows M26T, M27T, M28T, M29T, to generate the AFC error signal S8.
A polarity sequence switching signal PCH designating positive, positive, negative, negative, negative and negative polarities is sequentially sent to M30T and M31T, and 6-bit "H" time data TDT corresponding to the number of windows concerned.
To the shift register 21. Thus, in this case as well, the voltage V _C of the voltage conversion circuit 14 decreases from the reference time point t ₀ by an amount corresponding to the time delay T03 of the horizontal synchronizing signal HSYNC, which causes the VCO circuit 5 to reduce its oscillation frequency by that amount. By lowering it, the phase of the oscillation output signal S6 is locked to the phase of the horizontal synchronizing signal HSYNC.

Similarly, if the rising phase of the horizontal synchronizing signal HSYNC is further delayed, the decoder 20 generates the polarity order switching signal PCH and time data TDT corresponding to which time window the rising timing occurs, As a result, the time width of the negative pulse of the AFC error signal S8 is expanded by the amount of the phase delay, and accordingly, the oscillation frequency of the VCO circuit 5 is controlled to be lowered.

According to the above configuration, if the rising phase of the horizontal synchronizing signal HSYNC is advanced or delayed with respect to the reference time t ₀ of the oscillation frequency output signal S6 of the VCO circuit 5, it corresponds to this advance amount or delay amount. The AFC error signal S8 is formed such that the positive pulse or the negative pulse is expanded by the time width of the positive pulse or the negative pulse, which has a magnitude corresponding to the time width of the difference between the time widths of the positive pulse and the negative pulse. By applying the control voltage to the VCO circuit 5, the phase of the oscillation frequency output signal S6 of the VCO circuit 5 can be locked to the phase of the horizontal synchronizing signal HSYNC.

In the above description, the polarity order switching signal PCH specifies the positive polarity when the logic is "H" and the negative polarity when the logic is "L" for each time window. Is not limited to the polarity, and a positive signal level or a negative signal level may be designated. For example, when the output of the decoder 20 is a logic "H", +5 [V] is designated, and when the output is a logic "L", 0 [V] is designated, and when the output control circuit 23 is turned off, an AFC error signal is designated. The signal level of S8 may be +2.5 [V]. In short A
It suffices that the signal level of the FC error signal S8 takes three signal levels depending on whether the phase is advanced or delayed to form the first pulse and the second pulse that rise from the central signal level.

〔The invention's effect〕

As described above, according to the present invention, the pulse widths of the two pulses are expanded in accordance with the phase delay amount or the lead amount of the horizontal synchronizing signal and the oscillation frequency output signal of the VCO circuit according to the lead amount or the delay amount. By doing so, it is possible to form an AFC error signal by digital processing,
As a result, it is possible to easily obtain a frequency conversion device for a video signal, which is suitable for an IC and has a high phase lock accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal frequency conversion device according to the present invention, FIGS. 2 to 4 are signal waveform diagrams showing signals of respective parts thereof, and FIG. 5 is an AFC circuit of FIG. FIG. 6 is a block diagram showing the detailed configuration of FIG. 6, and FIG. 6 is a signal waveform diagram showing signals of respective parts thereof. 10 ... Frequency control circuit, 11 ... Divider, 12 ... AFC circuit, 13 ... AFC current source, 14 ... Voltage conversion circuit, 15 ... VCO
Circuit, 20 …… Decoder, 21 …… Shift register, 22 ……
Polarity switching circuit, 23 ... Output control circuit.

Claims (1)

[Claims] 1. A VCO circuit is controlled based on a horizontal synchronizing signal separated from an input video signal, and a carrier color signal in the input video signal is frequency-converted by an oscillation frequency output signal of the VCO circuit. In the frequency converter, the oscillation frequency output signal is divided to divide one cycle period of the horizontal synchronizing signal into a plurality of time windows, and the rising phase of the horizontal synchronizing signal and the positions of the plurality of time windows are divided. Compare
A correction signal forming circuit for forming a correction signal having a signal level corresponding to the deviation amount when the rising phase of the horizontal synchronizing signal deviates from the reference position of the predetermined time window of the frequency division output; The signal forming circuit generates a first pulse having a positive or negative signal level in synchronization with the horizontal synchronizing signal, and a first pulse having a negative or positive signal level in synchronization with the oscillation frequency output signal. Means for generating two pulses, and sequentially using the first and second pulses to the VCO circuit, when the phase of the horizontal synchronizing signal leads the reference phase of the oscillation frequency output signal. The pulse width of the first pulse is expanded based on the width of the time window so that the difference between the total pulse width of the pulse and the total pulse width of the second pulse matches the phase advance amount, and Horizontal sync signal When the phase is delayed from the reference phase of the oscillation frequency output signal, the difference between the total pulse width of the first pulse and the total pulse width of the second pulse matches the phase delay amount. And a control signal forming means for expanding the pulse width of the pulse based on the width of the time window.