JPS62151272U - - Google Patents
Info
- Publication number
- JPS62151272U JPS62151272U JP4046886U JP4046886U JPS62151272U JP S62151272 U JPS62151272 U JP S62151272U JP 4046886 U JP4046886 U JP 4046886U JP 4046886 U JP4046886 U JP 4046886U JP S62151272 U JPS62151272 U JP S62151272U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- horizontal
- delayed
- horizontal synchronization
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008929 regeneration Effects 0.000 claims description 2
- 238000011069 regeneration method Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 claims 4
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図の各部の信号波形図、第３図は第１図
の実施例の要部の詳細回路図、第４図は直流分再
生回路の概略構成図、第５図は従来例を説明する
ための信号波形図である。
４……同期分離回路、５……遅延回路、６……
クランプパルス形成回路。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a signal waveform diagram of each part in Figure 1, Figure 3 is a detailed circuit diagram of the main part of the embodiment in Figure 1, Figure 4 is a schematic configuration diagram of the DC component regeneration circuit, and Figure 5 is the conventional example. It is a signal waveform diagram for explanation. 4...Synchronization separation circuit, 5...Delay circuit, 6...
Clamp pulse forming circuit.
Claims (1)
遅延水平同期信号として出力する遅延回路と、 この遅延水平同期信号、前記水平同期信号およ
び水平ブランキングパルスに基づいて、水平ブラ
ンキングパルスの期間内において、遅延水平同期
信号および水平同期信号の期間と、それ以外の残
余の期間とで異なるレベルの波形を有するクラン
プパルスを形成出力するクランプパルス形成回路
とを備えることを特徴とする直流分再生回路。[Claims for Utility Model Registration] A delay circuit that delays a horizontal synchronization signal from a synchronization separation circuit and outputs the delayed horizontal synchronization signal as a delayed horizontal synchronization signal; Based on the delayed horizontal synchronization signal, the horizontal synchronization signal, and the horizontal blanking pulse, The present invention includes a clamp pulse forming circuit that forms and outputs a clamp pulse having a waveform of a different level in the period of the delayed horizontal synchronizing signal and the horizontal synchronizing signal and in the remaining period within the period of the horizontal blanking pulse. Characteristic DC component regeneration circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046886U JPS62151272U (en) | 1986-03-18 | 1986-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046886U JPS62151272U (en) | 1986-03-18 | 1986-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62151272U true JPS62151272U (en) | 1987-09-25 |
Family
ID=30854577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4046886U Pending JPS62151272U (en) | 1986-03-18 | 1986-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62151272U (en) |
-
1986
- 1986-03-18 JP JP4046886U patent/JPS62151272U/ja active Pending
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