JPS6395367U - - Google Patents

Info

Publication number
JPS6395367U
JPS6395367U JP18888986U JP18888986U JPS6395367U JP S6395367 U JPS6395367 U JP S6395367U JP 18888986 U JP18888986 U JP 18888986U JP 18888986 U JP18888986 U JP 18888986U JP S6395367 U JPS6395367 U JP S6395367U
Authority
JP
Japan
Prior art keywords
video signal
signal input
detection circuit
peak detection
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18888986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18888986U priority Critical patent/JPS6395367U/ja
Publication of JPS6395367U publication Critical patent/JPS6395367U/ja
Pending legal-status Critical Current

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Landscapes

  • Synchronizing For Television (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本考案の実施例を示し、第
1図は回路図、第2図は波形図、第3図および第
4図は従来の同期分離回路を示し、第3図は回路
図、第4図は波形図である。 1……ピーク検波回路、2……能動素子、3…
…能動素子の制御端、IN……映像信号入力端、
A……同期分離部。
Figures 1 and 2 show an embodiment of the present invention, Figure 1 is a circuit diagram, Figure 2 is a waveform diagram, Figures 3 and 4 are conventional synchronous separation circuits, and Figure 3 is a circuit diagram. The circuit diagram and FIG. 4 are waveform diagrams. 1...Peak detection circuit, 2...Active element, 3...
...Control terminal of active element, IN...Video signal input terminal,
A...Synchronization separation section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号入力端から入力される映像信号の同期
側ピークを検波するためのピーク検波回路と、映
像信号入力端から入力される映像信号のスライス
レベルを可変的に設定するための能動素子とを備
え、前記ピーク検波回路の出力端が前記能動素子
の制御端に接続され、前記ピーク検波回路からの
信号によりスライスレベルを変調するように構成
されていることを特徴とする同期分離回路。
Equipped with a peak detection circuit for detecting the synchronization side peak of the video signal input from the video signal input terminal, and an active element for variably setting the slice level of the video signal input from the video signal input terminal. . A synchronization separation circuit characterized in that an output end of the peak detection circuit is connected to a control end of the active element, and the slice level is modulated by a signal from the peak detection circuit.
JP18888986U 1986-12-08 1986-12-08 Pending JPS6395367U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18888986U JPS6395367U (en) 1986-12-08 1986-12-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18888986U JPS6395367U (en) 1986-12-08 1986-12-08

Publications (1)

Publication Number Publication Date
JPS6395367U true JPS6395367U (en) 1988-06-20

Family

ID=31140677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18888986U Pending JPS6395367U (en) 1986-12-08 1986-12-08

Country Status (1)

Country Link
JP (1) JPS6395367U (en)

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