JPS6340071U - - Google Patents
Info
- Publication number
- JPS6340071U JPS6340071U JP13240086U JP13240086U JPS6340071U JP S6340071 U JPS6340071 U JP S6340071U JP 13240086 U JP13240086 U JP 13240086U JP 13240086 U JP13240086 U JP 13240086U JP S6340071 U JPS6340071 U JP S6340071U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- slice
- sync chip
- video signal
- chip level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 238000000926 separation method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Picture Signal Circuits (AREA)
Description
第１図はこの考案が同期分離回路に適用された
一例のブロツク図、第２図はこの考案の一実施例
の接続図、第３図はこの考案の一実施例の説明に
用いる波形図、第４図はこの考案の一実施例の効
果を示す波形図、第５図は従来の同期分離回路の
一例のブロツク図、第６図は従来の同期分離回路
の一例の説明に用いる波形図である。
図面における主要な符号の説明、３：スライス
回路、４：シンクチツプレベル検出回路、５：積
分回路、６：クランプ回路。
Fig. 1 is a block diagram of an example of this invention applied to a synchronous separation circuit, Fig. 2 is a connection diagram of an embodiment of this invention, and Fig. 3 is a waveform diagram used to explain an embodiment of this invention. FIG. 4 is a waveform diagram showing the effect of an embodiment of this invention, FIG. 5 is a block diagram of an example of a conventional synchronous separation circuit, and FIG. 6 is a waveform diagram used to explain an example of a conventional synchronous separation circuit. be. Explanation of main symbols in the drawings: 3: slice circuit, 4: sync chip level detection circuit, 5: integration circuit, 6: clamp circuit.
Claims (1)
スライス回路の出力からシンクチツプレベルを検
出し、上記スライス回路で検出されたシンクチツ
プレベルを所定の時定数の積分回路で平滑して上
記スライス回路に対する所定のスライスレベルを
設定し、上記入力ビデオ信号中のシンクチツプレ
ベルよりも黒レベル側のノイズを上記スライス回
路で上記検出されたシンクチツプレベルに固定す
るようにした雑音除去回路。 An input video signal is supplied to a slice circuit, a sync chip level is detected from the output of the slice circuit, and the sync chip level detected by the slice circuit is smoothed by an integrating circuit with a predetermined time constant to obtain a predetermined value for the slice circuit. The noise removal circuit sets a slice level of the input video signal and fixes the noise on the black level side of the sync chip level in the input video signal to the sync chip level detected by the slice circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13240086U JPS6340071U (en) | 1986-08-29 | 1986-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13240086U JPS6340071U (en) | 1986-08-29 | 1986-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340071U true JPS6340071U (en) | 1988-03-15 |
Family
ID=31031751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13240086U Pending JPS6340071U (en) | 1986-08-29 | 1986-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340071U (en) |
-
1986
- 1986-08-29 JP JP13240086U patent/JPS6340071U/ja active Pending
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