JPS62198596U - - Google Patents
Info
- Publication number
- JPS62198596U JPS62198596U JP8749186U JP8749186U JPS62198596U JP S62198596 U JPS62198596 U JP S62198596U JP 8749186 U JP8749186 U JP 8749186U JP 8749186 U JP8749186 U JP 8749186U JP S62198596 U JPS62198596 U JP S62198596U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- memory
- access
- given
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
Description
第１図は本考案を実施したメモリ・アクセス制
御装置を表わす構成ブロツク図、第２，３図は本
考案を実施したメモリ・アクセス制御装置の動作
を表わすタイムチヤートである。
１０…メモリ・アクセス制御装置ＣＮＴ、１１
…同期化回路、１２…監視タイマ、１３…制御回
路、１４…クロツク発生回路、２０…メモリＭＥ
Ｍ。
FIG. 1 is a block diagram showing the structure of a memory access control device embodying the present invention, and FIGS. 2 and 3 are time charts showing the operation of the memory access control device embodying the present invention. 10...Memory access control device CNT, 11
...Synchronization circuit, 12...Monitoring timer, 13...Control circuit, 14...Clock generation circuit, 20...Memory ME
M.
Claims (1)
ート・メモリに対して２つのアクセス要求を受信
し、メモリ・アクセス信号を出力するメモリ・ア
クセス制御装置において、前記２つのアクセス要
求信号のうち優先アクセス要求信号が与えられた
場合は先着優先方式によりメモリ制御信号を出力
し、非優先アクセス要求信号が与えられた場合は
一定時間優先アクセス要求が与えられるかどうか
監視する監視タイマ部からの監視終了信号により
メモリ制御信号を出力する制御回路を有すること
を特徴とするメモリ・アクセス制御装置。 In a memory access control device that receives two access requests to a two-port memory having two different sets of access ports and outputs a memory access signal, a priority access request among the two access request signals is provided. When a signal is given, a memory control signal is output on a first-come, first-served basis, and when a non-priority access request signal is given, a monitoring end signal from a monitoring timer section that monitors whether a priority access request is given for a certain period of time is used. A memory access control device comprising a control circuit that outputs a memory control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749186U JPH067519Y2 (en) | 1986-06-09 | 1986-06-09 | Memory access controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749186U JPH067519Y2 (en) | 1986-06-09 | 1986-06-09 | Memory access controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62198596U true JPS62198596U (en) | 1987-12-17 |
| JPH067519Y2 JPH067519Y2 (en) | 1994-02-23 |
Family
ID=30944752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8749186U Expired - Lifetime JPH067519Y2 (en) | 1986-06-09 | 1986-06-09 | Memory access controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067519Y2 (en) |
-
1986
- 1986-06-09 JP JP8749186U patent/JPH067519Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH067519Y2 (en) | 1994-02-23 |
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