JPH0783323B2 - Demultiplexing converter - Google Patents

Description

The present invention relates to a device for demultiplexing and converting a plurality of digital signals having various speeds, and a programmable demultiplexing and converting device capable of selecting several demultiplexing conversion rules. Or a high-performance demultiplexing / conversion device in which the demultiplexing / conversion rule can be arbitrarily set by external control.

[Prior Art] FIG. 3 is a block diagram of a conventional demultiplexing and converting apparatus. In the figure, 1 is a low-speed interface signal receiving circuit,
Reference numeral 2 is a multiplex conversion circuit, 3 is a high speed interface signal transmission circuit, 4 is a high speed interface signal reception circuit, 5 is a separation conversion circuit, and 6 is a low speed interface signal transmission circuit.

The conventional demultiplexing / conversion device demultiplexes a plurality of low speed interface signals into one high speed interface signal and demultiplexes one high speed interface signal into a plurality of low speed interface signals. That is, each low-speed interface signal is sequentially interleaved in byte units or bit units, and fixedly multiplex-converted into one high-speed interface signal, and one low-speed interface signal is interleaved in byte units or bit units. This is a fixed separation and conversion into an interface signal.

[Problems to be Solved by the Invention] In the above-described conventional demultiplexing / conversion device, the high-speed interface signal received by the high-speed interface signal receiving circuit 4 is transmitted from the low-speed interface signal transmitting circuit 6 as a low-speed interface signal, and the low-speed interface signal is transmitted at low speed. The low speed interface signal received by the interface signal receiving circuit 1 is transmitted from the high speed interface transmitting circuit 3 as a high speed interface signal. Therefore, when the high-speed interface signal received by the high-speed interface receiving circuit 4 is transmitted from the high-speed interface signal transmitting circuit 3, the low-speed interface transmitting circuit 6 and the low-speed interface signal receiving circuit 1 are required, which results in cost increase. There was a problem.

Further, in the case of transmitting the low speed interface signals received by the plurality of low speed interface signal receiving circuits 1 as the high speed interface signals, the conventional demultiplexing / conversion apparatus uses only one fixedly determined high speed interface signal transmitting circuit 3. When the high-speed interface signal received by one high-speed interface signal receiving circuit 4 is transmitted as the low-speed interface signal, on the contrary, it can be transmitted only from a plurality of fixed low-speed interface signal transmitting circuits 6. There was also a problem.

[Means for Solving the Problem] In order to solve such a problem, the demultiplexing / conversion device according to the present invention is provided between a low speed interface and a high speed interface, and N × according to the read control content.
CCITT is provided between the first time slot converting means for converting time slots in units of 64 kb / s and one or more high speed interfaces according to the read control content.
A second time slot converting means for converting a time slot in units of a tributary unit TU-M defined by Recommendation G.708 or TTC standard JT-G708, etc. and first and second time slot converting means are selected. And selection means.

Further, the second time slot converting means is commonly provided between the high speed interfaces of the first and second demultiplexing / conversion devices.

[Operation] The first time slot conversion means converts the time slot in units of N × 64 kb / s according to the read control content.
As a result, it is possible to arbitrarily perform demultiplexing conversion between various low-speed interface signals and a plurality of high-speed interface signals, and set paths between low-speed interfaces. The second time slot conversion means converts the time slot in units of the tributary unit TU-M according to the read control content. As a result, a path can be set between the high speed interfaces.

Further, the second time slot conversion means performs time slot conversion of the high speed interface signal between the first and second demultiplexing conversion devices. As a result, the second time slot conversion means can be shared between the two demultiplexing conversion devices.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the demultiplexing and converting apparatus according to the present invention. In the figure, 7 is a low-speed interface signal receiving circuit, 8, 10, 12, 15, and 17 are speed conversion circuits, 9 is a time switch (first time slot conversion means) in units of N × 64 kb / s, and 11 is a selection. Circuit, 13 is a high speed interface signal transmitting circuit, 14 is a high speed interface signal receiving circuit, 16 is an 8KHZ phase synchronization circuit, 18 is a low speed interface signal transmitting circuit, 19 is a tributary unit TU-M
It is a time switch (second time slot conversion means) in units of (hereinafter referred to as TU-11).

The present invention provides a first means for using the time switch 9 when performing multiplex conversion from a low speed interface signal to a high speed interface signal and when performing separation conversion from a high speed interface signal to a low speed interface signal, and outputting from a high speed interface signal to a high speed interface signal. The second means for using the time switch 19 in the case of outputting, the third means for using the time switch 9 in the case of outputting from the low speed interface signal to the low speed interface signal, and A fourth method of using the time switch 19 when outputting to the high speed interface signal of the demultiplexing converter and when outputting from the high speed interface signal of the other demultiplexing converter to the high speed interface signal of one demultiplexing converter. It is composed of steps.

Next, the details of the configuration and operation of each of the first to fourth means will be described.

The first means is a low speed interface signal receiving circuit 7,
Speed conversion circuit 8,10,12,15,17, time switch 9, selection circuit
11, a high speed interface signal transmitting circuit 13, a high speed interface signal receiving circuit 14, an 8khz phase synchronization circuit 16 and a low speed interface signal transmitting circuit 18.

Next, this operation will be described. First, the low speed interface signal receiving circuit 7 receives the low speed interface signal, and the speed conversion circuit 8 converts the speed of the received signal. Although not shown, the low-speed interface signal reception circuit 7 or the speed conversion circuit 8 has an 8KHZ phase synchronization circuit for the low-speed interface signal, and the received low-speed interface signal is 8KHZ phase-synchronized by this circuit. Is taken. The signals whose phases have been matched and whose speeds have been converted are subjected to time slot exchange by the time switch 9.

The time-slot exchanged signal is subjected to speed conversion by the speed conversion circuit 10 and further selected by the selection circuit 11. The speed of the signal selected by the selection circuit 11 is converted by the speed conversion circuit 12, and is further transmitted from the high speed interface signal transmission circuit 13 as a high speed interface signal.

On the other hand, when the high speed interface signal receiving circuit 14 receives the high speed interface signal, the high speed interface signal receiving circuit 14 sends the received signal to the speed converting circuit 15 for speed conversion. Then, this speed-converted signal is sent to the 8KHZ phase synchronization circuit 16
, Phase matching is performed, and time switch 9 performs time slot exchange. In this way, this time slot exchanged signal is subjected to speed conversion by the speed conversion circuit 17, and is further transmitted from the low speed interface signal transmission circuit 18 as a low speed interface signal.

Thus, in the first means, the low-speed interface signal received by the low-speed interface signal receiving circuit 7 is N × 64 by using the time switch 9 of N × 64 kb / s unit.
By changing the content of the read control (hereinafter referred to as CM) of the time switch 9 in units of kb / s, multiplexing from any signal position of the high speed interface signal to any signal position of the low speed interface signal in units of N × 64 kb / s It can be converted and transmitted from any high-speed interface signal transmission circuit 13 as a high-speed interface signal.

The high-speed interface signal received by the high-speed interface signal receiving circuit 14 is changed from the CM content of the time switch 9 to an arbitrary signal of the low-speed interface signal from an arbitrary signal position of the high-speed interface signal in N × 64 kb / s unit. The low-speed interface signal can be transmitted from any arbitrary low-speed interface signal transmission circuit 18 by separating and converting into a position.

Next, the second means is the selection circuit 11 and the speed conversion circuits 12 and 1.
5, composed of a high speed interface signal transmitting circuit 13, a high speed interface signal receiving circuit 14 and a time switch 19.

Next, this operation will be described. First, the high-speed interface signal receiving circuit 14 receives a high-speed interface signal and sends the received signal to the speed conversion circuit 15 to convert the speed. Then, the speed-converted signal is TU
−11 units of time switch 19 exchanges time slots,
Further, it is selected in the selection circuit 11. In this way, the selected signal is subjected to speed conversion by the speed conversion circuit 12 and further transmitted from the high speed interface signal transmission circuit 13 as a high speed interface signal.

In this way, in the second means, the high-speed interface signal received by the high-speed interface signal receiving circuit 14 is transferred to the TU-11 by using the time switch 19 for each TU-11.
By changing the CM content of the unit time switch 19, the path (connection) of the TU-11 unit is set to an arbitrary signal position of the high speed interface signal to be transmitted from the arbitrary signal position of the received high speed interface signal, As a result, the high speed interface signal to be transmitted can be transmitted from any high speed interface signal transmission circuit 13.

Next, the third means is a low speed interface signal receiving circuit 7, speed converting circuits 8 and 17, a time switch 9, and a selecting circuit 11.
And a low speed interface signal transmission circuit 18.

Next, this operation will be described. First, the low speed interface signal receiving circuit 7 receives the low speed interface signal, and sends this received signal to the speed converting circuit 8 to convert the speed. Further, as described above, the low-speed interface signal receiving circuit 7 or the speed converting circuit 8 has an 8 kHz phase synchronizing circuit for the low-speed interface signal, where the received signal is 8 kHz phase-synchronized. This phase-matched and speed-converted signal is N × 64 kb / s
Time-slots are exchanged by the unit time switch 9, and the signals exchanged by the time-slots are transmitted to the speed conversion circuit.
The speed is converted at 17. In this way, the speed-converted signal is transmitted from the low-speed interface signal transmission circuit 18 as a low-speed interface signal.

Thus, in the third means, the low-speed interface signal received by the low-speed interface signal receiving circuit 7 is N × 64 by using the time switch 9 of N × 64 kb / s unit.
By changing the CM content of the time switch 9 in units of kb / s, a path in units of N × 64 kb / s is set to an arbitrary signal position of the low speed interface signal to be transmitted from an arbitrary signal position of the received low speed interface signal. And as a result,
The low speed interface signal to be transmitted can be transmitted from any low speed interface signal transmission circuit 18.

Next, FIG. 2 is a block diagram showing another embodiment of the demultiplexing and converting apparatus of the present invention. In the figure, 30 and 40 are
It is a demultiplexing converter.

Next, the configuration and operation of the fourth means will be described with reference to FIG. In the demultiplexing and converting apparatus 30, the fourth means is composed of a selecting circuit 11, speed converting circuits 12 and 15, a high speed interface signal transmitting circuit 13, a high speed interface signal receiving circuit 14, and a time switch 19, and
Similarly in the demultiplexing and converting device 40, the selection circuit 11,
It is composed of speed conversion circuits 12 and 15, a high speed interface signal transmission circuit 13, a high speed interface signal reception circuit 14, and a time switch 19.

Next, this operation will be described. First, the demultiplexing conversion device 30
The high-speed interface signal receiving circuit 14 receives the high-speed interface signal, and this received signal is the speed conversion circuit.
The speed is converted at 15. Then, the speed-converted signal is transmitted to the demultiplexing / converting device 40.

On the other hand, in the demultiplexing / converting device 40, the signal transmitted from the demultiplexing / converting device 30 is received, and this signal is transmitted to the TU.
The time switch 19 of -11 units is used for time slot exchange, and the signal for which the time slot exchange has been performed is selected by the selection circuit 11. Then, the speed conversion circuit 12 outputs the selected signal.
The speed is converted by and is further transmitted from the high speed interface signal transmission circuit 13 as a high speed interface signal.

Thus, in the fourth means, the demultiplexing conversion device
By connecting 30, 40, by changing the CM content of the time switch 19 of the TU-11 unit in the demultiplexing converter 40 the high-speed interface signal received by the high-speed interface signal receiving circuit 14 in the demultiplexing converter 30. Demultiplexing converter
A path of TU-11 unit is set at an arbitrary signal position of the high speed interface signal to be transmitted in the demultiplexing conversion device 40 from an arbitrary signal position of the high speed interface signal received at 40, and as a result, from the demultiplexing conversion device 40. The high-speed interface signal to be transmitted can be transmitted from any high-speed interface signal transmission circuit 13 in the demultiplexing / conversion device 40.

On the contrary, the high-speed interface signal received by the high-speed interface signal receiving circuit 14 in the demultiplexing / converting device 40 is transmitted to the demultiplexing / converting device 30. Then, by changing the CM contents of the time switch 19 in units of TU-11 in the demultiplexing / converting device 30, the demultiplexing / converting device 30 transmits from any signal position of the high-speed interface signal received by the demultiplexing / converting device 30. A TU-11 unit path is set at an arbitrary signal position of the high-speed interface signal to be transmitted, and as a result, the high-speed interface signal to be transmitted from the demultiplexing conversion device 30 is an arbitrary high-speed interface signal in the demultiplexing conversion device 30. The transmission circuit 13 can transmit.

As described above, the conventional demultiplexing / conversion apparatus has only the function of performing a large amount of demultiplexing / conversion, but the demultiplexing / conversion apparatus of the present invention has N × 64.
A time switch 9 of kb / s unit is provided, and by changing the CM content of the time switch 9 of N × 64 kb / s unit, demultiplexing conversion between various low speed interface signals and a plurality of high speed interface signals can be performed. It can be arbitrarily performed in units of × 64 kb / s, and a path can be set in units of N × 64 kb / s between low-speed interface signals.

Further, the demultiplexing and converting apparatus of the present invention is provided with a time switch 19 of TU-11 unit, and by changing the CM content of the time switch 19 of TU-11 unit, TU-11 unit is provided between high-speed interface signals. You can set the path.

[Effects of the Invention] As is apparent from the above description, according to the demultiplexing / converting device of the present invention, the first time slot converting means is capable of performing time conversion in units of N × 64 kb / s according to the content of the read control. Since the second time slot converting means converts the time slot in units of the tributary unit TU-M according to the read control content, the second time slot converting means converts between various low speed interface signals and a plurality of high speed interface signals. When demultiplexing and converting is not fixed and can be freely performed, and the path between low-speed interface signals and the path between high-speed interface signals can be set, and high-speed interface signals are output from high-speed interface signals. In addition, there is an effect that a transmission / reception circuit for low-speed interface signals becomes unnecessary.

Further, since the second time slot converting means is made to perform the time slot conversion of the high speed interface signal between the first and second demultiplexing converters,
There is an effect that the second time slot conversion means can be shared between the two demultiplexing / converting devices, and the demultiplexing / converting device can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a demultiplexing / conversion apparatus according to the present invention, FIG. 2 is a block diagram showing another embodiment of this apparatus, and FIG. 3 is a block diagram of a conventional demultiplexing / conversion apparatus. Is. 7: Low-speed interface signal receiving circuit, 8,10,12,1
5,17 …… Speed conversion circuit, 9 …… N × 64 kb / s unit time switch, 11 …… Selection circuit, 13 …… High speed interface signal transmission circuit, 14 …… High speed interface signal reception circuit, 16 …… 8KHZ Phase synchronization circuit, 18 ... Low speed interface signal transmission circuit, 19 ... TU-11 unit time switch,
30,40 …… Multi-demultiplex converter.

Claims (2)

[Claims] 1. A demultiplexing / conversion device that multiplex-converts a plurality of low-speed interface signals into one or a plurality of high-speed interface signals and separates and converts from one or a plurality of high-speed interface signals into a plurality of low-speed interface signals. A first time slot conversion means provided between the interface and the high speed interface for converting time slots in units of N × 64 kb / s according to the read control content; and a read provided between one or more high speed interfaces. However, the tributary unit TU-M specified in CCITT Recommendation G.708 or TTC standard JT-G708 etc. according to the control contents.
A demultiplexing / conversion device comprising: a second time slot converting means for converting a time slot in units; and a selecting means for selecting the first and second time slot converting means. 2. A demultiplexing and converting device according to claim 1 is provided.
And a second demultiplexing / conversion device shared between the high-speed interfaces of the first and second demultiplexing / conversion devices.