JP2000092014A - Lsi for isdn interface control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a used channel in H0 channels from being fixed, to eliminate the need of an external circuit and to cope with the plural pieces of H0 channel communication by one piece. SOLUTION: Frame memories 15 and 16 are alternately switched to a write mode and a read mode, a memory address register 14 successively instructs an address destination for writing B channel data 71 to the frame memory in the write mode and a start time slot column setting register 12 outputs a write start address to the memory address register 14. The memory address register 13 successively instructs the address destination for reading the previously stored B channel data from the frame memory in the read mode, a selector 17 connects the memory address register 14 when the frame memory 15 is in the write mode and connects the memory address register 13 when the frame memory 15 is in the read mode and the selector 18 also performs a similar operation to the frame memory 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI for controlling an ISDN interface, and more particularly to a connection between an ISDN primary rate interface line and a data communication device connected to the ISDN primary rate interface line. And I
ISD used for transfer control of channel data between SDN primary rate interface line and data communication device
The present invention relates to an N interface control LSI.

[0002]

2. Description of the Related Art Conventionally, a data communication device is connected to an ISDN primary rate interface line, and an information channel B and a signal channel are provided between the ISDN primary rate interface line and the data communication device. When data is transferred using the D channel, the ISD
An ISDN interface control LSI is connected between the N primary rate interface line and the data communication device;
Input / output control such as multiplexing and demultiplexing of B channel data and D channel data with the ISDN primary rate interface line is performed.

[0003] An LSI for controlling an ISDN interface connected between an ISDN primary rate interface line and a data communication device is composed of serial data input from the ISDN primary rate interface line and B channel data. Means for separating and outputting B channel data and D channel data input from the data communication device into serial data, and ISDN
Means for outputting to the primary rate interface line.

In the ISDN primary rate interface line, a total of 24 information and signal channels of B channel (64 kbps) and D channel (64 kbps) can be provided, but the ISDN primary rate interface is used. As a channel type in a line, there is a channel having a capacity corresponding to a plurality of these channels, that is, an H channel having a higher channel speed than the B channel and the D channel, in addition to the B channel and the D channel described above. The ITU-T I.411, for example, includes interfaces for six B channels.
Speed is 384 kbps (384 kbps = 64 kbp)
s × 6) H ₀ channels are defined, and the H ₀ channel can be provided with six consecutive B channels or D channels. In addition, the interface
Speed is 1,536 kbps (1,536 kbps = 6
There is also H ₁ channel of 4 kbps × 24). In the H ₁ channel, 24 as B-channel or D channel
Although channels can be provided, 23 channels are usually used as B channels and the remaining one channel is used as D channel.

[0005] Five B channels and one D channel
ISDN communication using the H ₀ channel to channel internal
When the connection is performed between the primary rate interface line and the data communication device, an ISDN interface control LSI is connected between the ISDN primary rate interface line and the data communication device, and the ISDN primary rate interface is connected. In the transmission to the communication line, the B channel data of the information channel and the D channel data of the signal channel transmitted from the data communication device are combined in synchronization with the clock of the ISDN primary rate interface line, and the serial data is synthesized. Generate Further, in order to send the serial data to the ISDN primary rate interface line, a multi-frame synchronization signal and a control bit for communication control are added, and one frame is assembled to be sent to the ISDN as a frame signal. When receiving from the ISDN primary rate interface line, a predetermined B channel is selected from the serial data of 24 channels of the ISDN primary rate interface line in synchronization with the clock of the ISDN primary rate interface line. The data and the D-channel data are separated and taken out, and transmitted to the data communication device as predetermined B-channel data and D-channel data in synchronization with the clock of the data communication device.

As described above, in the LSI for controlling the ISDN interface, the input / output control processing for the B channel data and the D channel data transmitted and received between the data communication device and the ISDN is performed. B-channel data and D-channel data transmitted / received to / from the ISDN primary rate interface line are each composed of 8 bits.

[0007] For example, in the transmission by H ₀ channel consists of B channels and one channel of the D channel 5 channels sent from the data communication device to ISDN, initially, each B channel for five consecutive channels sequentially 1 Eight bits are transmitted serially for each channel, and finally eight bits of the D channel are transmitted. The transmission of the channel data of the B channel and the D channel is described in Japanese Patent Laid-Open No. 6-6467.
As shown in the publication, predetermined time slots are allocated to the B channel and the D channel from among the 24 time slots of the ISDN primary rate interface line. When a predetermined time slot is assigned to each channel, each channel is transmitted at the timing of the assigned time slot. When the data communication device receives the B channel and the D channel from the ISDN primary rate interface line, the data is transmitted in the time slot to which each channel is allocated in the same manner as in the case of transmission. Each channel is taken out.

[0008] Thus, while LSI for ISDN interface control is used in the case of transmitting and receiving channel data using the H ₀ channel between the communication device and the ISDN, conventional ISDN interface control for LS
In the case of performing communication using the H ₀ channel in I, there is a problem that the used channel must be used fixedly.

When the communication control of the B channel and the D channel in the H ₀ channel is performed by the conventional LSI for controlling the ISDN interface, the B channel and the D channel are controlled by using an external circuit in addition to the LSI for controlling the ISDN interface. It is necessary to control the LSI by extracting and synthesizing data, and thus there is a problem that many hardware circuits must be used.

Further, in the case that performs communication using multiple the H ₀ channel, in order to perform communication control of B channels and D channels in the H ₀ channel, the IS
There is also a problem that a circuit must be configured using a plurality of LSIs for controlling the DN interface.

[0011]

The above-mentioned conventional ISD
The N interface control LSI, when communicating the H ₀ channel ISDN interface control LSI has the disadvantage that it is necessary to use a used channel fixedly.

An ISDN interface control LS
Besides I, used by adding to the ISDN interface control LSI, H ₀ de B-channels and D channels in the channel - an external circuit for synthesizing extracts motor control is required, this order Has the disadvantage that many hardware circuits are required.

When communication is performed using a plurality of H ₀ channels, a plurality of ISDN interface control LSIs are used to control the communication of the B and D channels in each H ₀ channel. It has the disadvantage that it must be done.

An object of the present invention, be used as a communication control circuit for H ₀ channel communication, H ₀ not used channels in the channel fixedly, de B-channel and D-channel - to extract data many external circuits without the need for synthesizing controlled Te, also to provide an ISDN interface control LSI can respond as a communication control circuit for a plurality of H ₀ channel communications with one.

[0015]

According to a first aspect of the present invention, there is provided an LSI for controlling an ISDN interface between an ISDN primary rate interface line and a data communication device connected to the ISDN primary rate interface line. And an ISDN interface control LSI for controlling the transfer of channel data between the ISDN primary rate interface line and the data communication device, the plurality of LSIs being set for transferring the channel data. An input terminal for inputting the channel data transferred in the specified time slot from the data communication device, wherein an arbitrary time slot used for transferring the channel data can be designated from the time slots; and Transfer the channel data transferred to the data communication device And it is configured to include an output terminal for power.

An LSI for controlling an ISDN interface according to a second aspect of the present invention is the same as the LSI for controlling an ISDN interface according to the first aspect of the invention, including a plurality of the input terminals and the plurality of output terminals.

The ISDN interface control LSI according to a third invention is the ISDN interface control LSI according to the second invention, wherein one of the plurality of input terminals and output terminals is one of the ISDN primary group speed interface. Input and output terminals for the transfer of channel data of the D channel defined by the
The rest is configured as an input terminal and an output terminal for transferring channel data of the B channel defined by the ISDN primary rate interface line.

According to a fourth aspect of the present invention, there is provided the ISDN interface controlling LSI according to the first aspect of the present invention, wherein (A) an optional setting signal used for transferring the channel data by an external setting signal as an initial setting. A first register for designating a time slot of the data communication device, and writing data for sequentially writing one frame of channel data of the channel data from the data communication device in the write mode in accordance with an address corresponding to the time slot designated by the register. In the operation and the read mode, a first pair of frame memories for alternately performing a read operation for reading the channel data for the one frame written in the write mode, and alternately from the first pair of frame memories. The read data communication device A channel transmission frame aligner for multiplexing and outputting the channel data, and (B) a second register for designating an arbitrary time slot used for transfer of the channel data by an external setting signal as an initial setting. And a write operation for sequentially writing one frame of the channel data of the channel data from the ISDN primary rate interface line in a write mode in accordance with an address corresponding to a time slot designated by the register, and in a read mode. A second pair of frame memories for alternately performing a read operation of reading the one frame of channel data written in the write mode, and the ISDN primary read alternately from the second pair of frame memories From the group speed interface line Serial channel data channel received frame and outputs the multiplexed - Muaraina,
It is comprised including.

The ISDN interface controlling LSI according to a fifth aspect of the present invention is the LSI for controlling the ISDN interface according to the fourth aspect of the present invention, wherein the plurality of channel transmitting frame aligners and the plurality of channel receiving frame aligners are provided. One of the channel transmit frame aligner and the channel receive frame aligner
Are a channel transmission frame aligner and a channel reception frame aligner for transferring channel data of the D channel defined by the ISDN primary rate interface line, and the rest are the ISDN primary rate interface lines. Are configured as a channel transmission frame aligner and a channel reception frame aligner for transferring channel data of the B channel defined by

The LSI for controlling an ISDN interface according to a sixth aspect of the present invention is the LSI for controlling an ISDN interface according to a fifth aspect of the present invention, further comprising: an output of a channel transmission frame aligner for transferring channel data of the B channel; The output of the channel transmission frame aligner for transferring the channel data of the D channel is combined with the output of the I-channel as the channel data from the data communication device.
Combining means for sending out to the SDN primary rate interface line, an output of a channel receiving frame aligner for transferring the channel data of the B channel, and
A synthesizing means for synthesizing an output of a channel receiving frame aligner for transferring channel data of a channel and transmitting the channel data from the ISDN primary rate interface line to the data communication device. Be composed.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an ISDN interface control LSI according to the present invention.

The LSI for controlling the ISDN interface according to the present embodiment shown in FIG. 1 has a data transmission device side (hereinafter referred to as a device side) of 512 kbps which has been input.
(512 kbps = 64 kbps × 8) The B channel data 61 synchronized with the device side clock is changed to 1,536 kbps on the ISDN line side (hereinafter referred to as line side).
(1,536 kbps = 64 kbps × 24) The B channel transmission frame aligner 1 which synchronizes with the line clock and transmits the data as serial data to the line in a predetermined time slot allocated to the B channel to the line. A D-channel transmission frame aligner 2 for synchronizing the D-channel data 62, which has been synchronized with the device-side clock of 512 kbps up to the line-side clock of 1,536 kbps, and transmitting it as serial data in a predetermined D-channel time slot; The B-channel data and the D-channel data synchronized with the clock are combined into one data frame.
A channel combining unit 3 assembled as a frame, and a multi-frame for synchronizing a control bit for communication control and a frame with the data frame assembled by the channel combining unit 3.
System synchronization signal and CRC for detecting error bits
(Circular redundancy chec
k: a cyclic redundancy check) a transmission control unit 4 for adding and checking a check bit to form and output a one-frame data signal to be output to the line side, and a frame-structured data signal formed by the transmission control unit 4 5 for outputting serial data 63 to the line side, a receiver 6 for receiving serial data 64 from the line side, and a control bit extracted from the serial data 64 input by the receiver 6 from the line side to obtain a multi-frame. A frame synchronization is detected by detecting a synchronizing signal, and an error check is executed by using a CRC check bit to separate only a data portion composed of B channel data and D channel data from the frame. Receiving control unit 7 for outputting the separated data portion, and receiving control unit 7
And a channel separation unit 8 for separating and outputting the data portion input from the unit into B-channel data and D-channel data, and B-channel data output from the channel separation unit 8.
B synchronized with the line-side clock of 1,536 kbps
The channel data is synchronized with the 512 kbps clock on the device side, a B-channel reception frame aligner 9 for transmitting to the device as B-channel data 65 in a predetermined time slot of the B-channel, and a D-channel data output from the channel separation unit 8. And the D-channel data synchronized with the line side clock is transferred to the device side at 512 kbp.
and a D-channel reception frame aligner 10 which synchronizes with the s clock and transmits the B-channel data 66 to the device in a predetermined time slot of the B-channel on the device side.

Next, the operation will be described.

First, B-channel data 61 is sent from the device side.
The operation when receiving the D channel data 62 and outputting it as serial data 63 to the line side will be described.

Here, a case will be described where the number of B-channel data transmitted and received between the device side and the line side is eight, and the number of D-channel data is one.

In FIG. 1, B channel data 61 and D of eight channels in which assigned time slots are consecutive are shown.
When the D channel data 62 of channel 1 is input from the device side to the B channel transmission frame aligner 1 and the D channel transmission frame aligner 2, respectively, the B channel transmission frame aligner 1 The B channel data 61 synchronized with the device side is synchronized with the line side, and the D channel transmission frame aligner 2
The input D-channel data 62, which has been synchronized with the apparatus side, is synchronized with the line side.

The B-channel data 61 and the D-channel data 62 synchronized with the line side are sent to the channel synthesizing unit 3, where they are assembled as one data frame. The data frame assembled from the B channel data and the D channel data is sent from the channel combining section 3 to the transmission control section 4, where the control bits, multi-frame synchronization signal bits, and CRC check are performed. Bits are added to form a frame signal output to the line side.

The constructed frame signal is sent from the transmission control unit 4 to the driver 5 and output as serial data 63 to the line side.

Next, the operation when receiving the serial data 64 from the line side and outputting the B channel data 65 and the D channel data 66 to the apparatus side will be described.

The serial data 64 input from the line side to the receiver 6 is sent from the receiver 6 to the reception control unit 7. The reception control unit 7 extracts a control bit for communication control from the input serial data 64, detects a multi-frame synchronization signal bit, and performs frame synchronization.
The reception control unit 7 further performs an error check using the CRC check bit, and outputs a data portion composed of B channel data and D channel data to the channel separation unit 8.

The channel separation unit 8 converts the data portion input from the reception control unit 7 into B channel data and D channel data.
Then, the B channel data is sent to the B channel receiving frame aligner 9 and the D channel data is sent to the D channel receiving frame aligner 10, respectively. The B-channel receiving frame aligner 9 and the D-channel receiving frame aligner 10 synchronize the input B-channel data and the D-channel data, which have been synchronized with the line side, with the apparatus side, respectively. The D channel data 66 is output to the device.

The operation of the LSI for controlling the ISDN interface according to the present invention shown in FIG. 1 has been described above. Next, the B-channel transmission frame aligners 1 and D shown in FIG.
The circuit operation of the channel transmission frame aligner used in the channel transmission frame aligner 2 will be described.

FIG. 2 is a block diagram showing a circuit configuration of a channel transmission frame aligner used as the B-channel transmission frame aligner 1 and the D-channel transmission frame aligner 2 of FIG. FIG. 3 is a timing chart showing an example of the circuit operation of the channel transmission frame aligner shown in FIG.

The channel transmission frame aligner shown in FIG. 2 has a total of 24 B channels and 1 D channel of the ISDN primary rate interface line.
For each time slot for the channel, as shown in FIG.
The time slot of the time slot allocated to the channel data 71 input from the device in the write mode is configured so that 8 bits constituting the channel data of each time slot can be sequentially stored at a designated address. An address number corresponding to the number is given, and channel data 7 is provided at the address destination of the address number.
1 is sequentially written in synchronization with a 512 kbps device-side clock 76 supplied from the outside. In the read mode, the channel data 73 output to the line side is supplied with an address number indicating the read destination and the ISDN primary group speed interface. 1 and 53 of the line side clock 72 of the
Frame memory 15 for reading sequentially in synchronization with 6 kbps
Similarly to the frame memory 15, each of the 24 time slots is configured so that 8 bits constituting the channel data of each time slot can be sequentially stored at a designated address. The order of the time slot numbers assigned to the slots and the order of the address numbers are set in a predetermined correspondence relationship. When the frame memory 15 is in the write mode, it operates in the read mode, and the frame memory 15 operates in the read mode. In this case, the operation in the write mode is controlled so that the operation in the write mode and the read mode are alternately repeated with the frame memory 15 so as to operate in the write mode. The time slot number of the time slot allocated to the channel data 71 Given the address number of the write sequence synchronization channel data 71 to the device-side clock 76 to the address destination of the address number, at the time of reading mode, the channel data 74 to be output to the line side,
A frame memory 16 which is provided with an address number indicating a reading destination and is sequentially read in synchronization with the line clock 72;
Each time a write frame pulse (WFP) signal 75 is input from the device side, it is connected to the frame memory 15 or 16 in the write mode and is transmitted in the first time slot at the start of writing. An address number indicating the write destination of the first bit of data is designated, and thereafter, the operation of writing channel data 71 input from the device side to the frame memory 15 or the frame memory 16 is performed in synchronization with the device side clock. Memory address register 14 for sequentially advancing the write destination address number of channel data 71 and outputting it to frame memory 15 or frame memory 16;
Each time the P signal 75 is input from the device side, the frame memory 15 is held in the previous read mode and held until then.
Alternatively, the address number output to the frame memory 16 is
Each time the WFP signal 75 is input from the apparatus side, it is reset to the first address number at the start of reading by the new WFP signal 75, and is connected to the frame memory 15 or 16 in the reading mode,
In order to sequentially read the channel data stored at each address of the frame memory 15 or the frame memory 16 as the channel data 73 or the channel data 74 output from the frame memory 15 or the frame memory 16 to the line side, A memory address register 13 for sequentially designating and outputting an address number corresponding to a time slot allocated to the channel data in synchronization with the line-side clock 72, and a frame memory 1 in a write mode
5 or the time slot allocated to the first channel data of the channel data 71 when the operation of writing the channel data 71 input from the apparatus side to the frame memory 16 is designated as the start time slot, Each time a WFP signal 75 is input from the device side,
A start time slot designation register 12 that outputs a start time slot number designation signal 77 indicating the number of the start time slot to the memory address register 14, and when switching from the write mode to the read mode or switching to the mode in the opposite direction. When the selector 17 alternately selects the memory address register 13 and the memory address register 14 and switches to connect to the frame memory 15, and when the selector 17 selects the memory address register 14 and connects to the frame memory 15, When the memory address register 13 is selected and connected to the frame memory 16, and when the selector 17 selects the memory address register 13 and connected to the frame memory 15, the memory address register 14 is selected and stored in the frame memory 16. To connect Similarly to the selector 17, the selector 18 alternately selects the memory address register 13 and the memory address register 14 and switches and connects the memory address register 13 and the memory address register 14 to the frame memory 16, the channel data 73 read from the frame memory 15, and the frame. Multiplexer 19 for time-division multiplexing with the channel data 74 read from the memory 16
A first-in first-out memory (FIFO) which receives the output from the multiplexing unit 19 in which channel data 73 and channel data 74 are multiplexed, processes the data to synchronize with the line side, and outputs it as serial data. (Memory) 20 and a control unit 11 for controlling the writing and reading operations of the channel data to and from the frame memory 15 and the frame memory 16.

Next, the operation of the channel transmission frame aligner will be described.

A case where the channel transmission frame aligner shown in FIG. 2 transfers channel data of eight B channels from the apparatus side to the line side will be described below.

In order to transfer the channel data of eight channels from the device side to the line side, the time slots (first time slot to 24th time slot) for a total of 24 channels of the ISDN primary rate interface line are required. Of these, it is necessary to set which time slot to use, but here, a description will be given assuming that a total of eight time slots from the ninth time slot to the sixteenth time slot are used.

First, the first ninth time slot number of the eight time slots to be used is input to and set in the start time slot specification register 12 by a start time slot number specification signal 77 output from the apparatus side.

When eight consecutive time slots from the ninth time slot to the sixteenth time slot are used, it is necessary to use the 512 kbps apparatus side clock 76 for the write operation.

Next, when a WFP signal 75, which is supplied from the apparatus and indicates the head of the frame of the B channel data, is input to the memory address register 14, the WFP signal 75
The memory address register 14 inputs the start time slot number (ninth time slot) set in the start time slot designation register 12 at the timing of the rising edge of the first time slot. Set the address number to store the bit. At the same time, at the timing of the rising edge of the WFP signal 75, the address number designated and held by the memory address register 13 during the immediately preceding read operation is reset. The WFP signal 75 is also input to the control unit 11.

Next, the control section 11, to which the WFP signal 75 has been input, sends out a control signal 79 to control the selectors 17 and 18, and the selector 17 selects the memory address register 14 and stores it in the frame memory 15. Connecting.
The memory address register 14 outputs an address number for storing the first bit of the B-channel data transferred in the ninth time slot to the frame memory 15, and the frame memory 15 having received the address number outputs the address to the control unit 11
Is controlled by the control signal 79 from the controller, and the channel data 7 input from the device side is stored in the address indicated by the address number.
The first bit of the first data, that is, the first bit of the B channel data of the first B channel among the eight B channels is written. Thereafter, in synchronization with the device side clock, the remaining channel data of the channel data 71 input from the device side, that is, from the second bit of the first B channel data to the eighth bit of the last B channel data, are sequentially
Data is written to successive addresses following the address where the first data is written.

On the other hand, the selector 1 controlled by the control unit 11
8 selects the memory address register 13 and connects it to the frame memory 16. Memory address register 13
Is in a state in which the address number is reset at the rising timing of the WFP signal 75 and the address number for storing the first bit of the B channel transferred by the first time slot of the 24 time slots is specified. Has become. The memory address register 13 outputs this address number to the frame memory 16, and the frame memory 16 having received the address number is controlled by a control signal 79 from the control unit 11, and outputs the address output from the memory address register 13. From the address indicated by the number, the B channel data input from the device stored in the immediately preceding write mode is read as channel data 74, but the B channel data used for transfer of the B channel data from the device is used. Since the time slot is from the ninth time slot to the sixteenth time slot, there is no data to be read, and the memory address register 1
After the storage address number of the first bit of the third to ninth time slots is output, the bits of the B channel data stored at the address indicated by the address number are sent to the multiplexing unit 19 as read channel data 74. be able to.

In the above operation, the device specified by
Eight 8-bit B-channel data are sequentially written at consecutive addresses on the frame memory 15 corresponding to eight consecutive time slots from the ninth time slot to the sixteenth time slot, for a total of 64 bits. Will be. At the same time, in the frame memory 16,
Data is sequentially read from the addresses corresponding to the 24 time slots on the frame memory 16, and the addresses (24 × 8) corresponding to the 24 time slots are read out.
= 192 addresses) include 64 addresses having the same address number as the address of the 64-bit write destination to the frame memory 15 described above. In the mode, the frame memory 16 also stores 12 addresses other than the above 64 addresses.
Since channel data from the device side is not written in 8 (192-64 = 128) addresses,
128 in consecutive addresses of 4 time slots
The read operation is performed in a state where the channel data to be read is not stored in the individual addresses.

As described above, the frame memory 15 stores the channel data of eight channels transmitted from the apparatus in the write mode in each of the designated ninth to sixteenth time slots. Are written to all the addresses of the frame memory 15 corresponding to the frame memory 16 while the frame memory 16 in the read mode state is written.
In this case, data is read from all addresses corresponding to 24 time slots and sent to the multiplexing unit 19 as channel data 73. When the next WFP 75 is sent from the device side, the frame memory 15 Are in the read mode state, and the operation of the frame memory 16 in the write mode state is performed under the control of the control unit 11.

At the rising edge of the next WFP signal 75 supplied from the device, the contents of the start time slot designation register 12 are stored in the memory address register 1
4 again, and at the same time, the address number of the memory address register 13 is reset at the rising timing of the WFP signal 75. Next, under the control of a control signal 79 from the control unit 11, the selector 18 selects and connects the memory address register 14 to the frame memory 16, and the memory address register 14 is transferred from the start time slot designation register 12. Based on the specified start time slot number, that is, the ninth time slot number, the address number at which the first bit of the channel data of the start time slot is stored is output to the frame memory 16 as the storage destination address of the first bit of the channel data. Then, the first bit of the B channel data allocated to the ninth time slot, which is the first data of the channel data 71 of the next frame, input from the apparatus side, is written into this address. Thereafter, the remaining data of the channel data 71 input from the device side, from the second bit of the B channel data to which the ninth time slot is allocated to the eighth bit of the B channel data to which the sixteenth time slot is allocated Are sequentially written to successive addresses.

Further, under the control of the control unit 11, the selector 17 selects and connects the memory address register 13 to the frame memory 15, and the memory address register 1
3 sends to the frame memory 15 the address number for storing the first bit of the B channel data to which the first time slot is allocated. From the address indicated by the address number output from the memory address register 13 to the frame memory 15, the channel data input from the device side and stored in the immediately preceding write mode is read, and the read channel data is The data is transmitted to the multiplexing unit 19 as channel data 74.

As described above, the frame memory 15 and the frame memory 15
By repeating the operation of writing channel data from the device side alternately and reading data to be sent to the line side when one is writing channel data input from the device side, Channel data for eight B channels transmitted from the device side can be transferred to the line side as channel data of eight consecutive channels designated in advance among 24 channels of the ISDN primary rate interface line. it can.

FIG. 3 is a timing chart showing an example of the circuit operation of the channel transmission frame aligner shown in FIG. Next, the operation will be described with reference to the timing chart shown in FIG.

FIG. 3A shows a WFP.
(2) shows a line-side clock 72 of 1,536 kbps. (3) indicates the time slot number corresponding to the channel data and the bit number of the time slot read out from the address indicated by the memory address register 13 in synchronization with the line clock 72, and "T" indicates the time slot. "B" means a bit. Then, the first two digits “2” of the number “TB248”
"4" indicates the time slot number, and the last digit "8"
Indicates the number of the bit constituting the channel data transmitted in the time slot. Therefore, "TB24
"8" indicates the eighth bit of the channel data of the 24th time slot. (4) is 512 kbps
(5) shows the device-side clock 76 at the address indicated by the memory address register 14.
Shows the time slot number corresponding to the channel data and the bit number of the time slot, which are written in synchronization with. The meanings of “T” and “B” and the meaning given to the numbers are the same as in (3).

As shown in FIG. 3A, after the WFP rises, the memory address register 13 specifies the first bit (TB011) of the channel data of the first time slot in synchronization with the line clock 72. In the next clock, the second bit (TB012) of the channel data of the first time slot is designated. Further, the memory address register 14 stores the 512 kbps supplied from the device side.
The first clock (TB091) of the ninth time slot channel data is designated by the device side clock 76, and the second bit (TB092) of the ninth time slot channel data is designated by the next clock.

The address sequentially specified by the memory address register 13 is a total of 192 (24 × 8 = 192) bits of channel data from the first time slot to the 24th time slot each composed of 8 bits. Are sequentially read from the frame memory 16. The memory address register 14 stores a total of 64 (8 × 8 = 64) bits from the first bit of the channel data of the ninth time slot to the eighth bit of the channel data of the sixteenth time slot. 15 are sequentially designated as storage addresses.
The data is sequentially written to the frame memory 15. As described above, the addresses are designated by the memory address registers 13 and 14, and are used to transfer the first B channel of one frame input from the apparatus side to the frame memory 15 during one frame period. From the first bit of the time slot channel data to the eighth bit of the time slot channel data used for the transfer of the eighth B channel,
That is, from the first bit of the channel data of the ninth time slot to the eighth bit of the channel data of the sixteenth time slot.
Is written to the frame memory 1
From 6 onward, the data from the first bit of the ninth time slot channel data written to the frame memory 16 to the eighth bit of the sixteenth time slot channel data written in the frame memory 16 at the time of the write operation in the immediately preceding frame. Including
A total of 192 bits (24 × 8 = 192) of data from the first bit of the channel data of the first time slot to the eighth bit of the channel data of the twenty-fourth time slot are read.

It should be noted that, of the data read out here, the channels of the other time slots excluding the data from the first bit of the channel data of the ninth time slot to the eighth bit of the channel data of the sixteenth time slot The data is not subjected to communication processing of the channel transmission frame aligner for the purpose of transferring channel data for eight B channels, and in the write mode of the frame memory 15 and the frame memory 16, nothing is performed. Since no data has been written, an address number is specified by the memory address register 13 in the read mode, and a read operation is performed from the address destination, but no data is read.

The ninth data read from the frame memory 16
1st bit to 1st bit of channel data of time slot
The data of 24 time slots including the data up to the 8th bit of the channel data of 6 time slots is transmitted to the multiplexing section 19 as channel data, and is passed through the multiplexing section 19 for first-in first-out. Memory 20
Is input to The first-in first-out memory 20 stores channel data 73 and channel data 74
The output from the multiplexing unit 19 in which the data is multiplexed is input and processed so as to be synchronized with the line side clock.
Output as 8.

Further, in the next one frame period, the write mode and the read mode of the frame memory 15 and the frame memory 16 are switched, and the channel data of the ninth to sixteenth time slots is stored in the frame memory 16. The channel data of the first to twenty-fourth time slots written in the previous one frame period is read out from the frame memory 15.

As described above, the first time slot number of the time slot sequence allocated to the B channel data to be transferred is designated from the device side, and the writing and reading of the frame memory are alternately performed for each frame. By switching the operation mode (see FIG. 3B), data transfer from the device side to the line side can be performed. FIG.
In (b), (6) shows a WFP of a plurality of frames. (7) indicates a write or read time slot for the frame memory 15. (8) shows the access status to the frame 15. (9) indicates a read or write time slot for the frame memory 16. (10) indicates the status of access to the frame 16.

Next, the circuit operation of the channel receiving frame aligner used in the B channel receiving frame aligner 9 and the D channel receiving frame aligner 10 of FIG. 1 will be described.

FIG. 4 is a block diagram showing a circuit configuration of a channel receiving frame aligner used as the B channel receiving frame aligner 9 and the D channel receiving frame aligner 10 of FIG. FIG. 5 is a timing chart showing an example of the circuit operation of the channel reception frame aligner shown in FIG.

The channel reception frame aligner shown in FIG. 4 is similar to the transmission frame aligner shown in FIG.
8 bits constituting channel data of each time slot are sequentially stored in designated addresses for every 24 time slots of 23 channels of B channel and 1 channel of D channel of the N primary speed interface line. As shown in FIG. 6, the order of the time slot numbers assigned to the 24 time slots and the order of the address numbers are set in a predetermined correspondence relationship. The serial data 84 input from the side is sequentially written in synchronization with the line clock 72 supplied from the outside, and in the read mode, the channel data 85 output to the device side is given an address number indicating the read destination. A frame memory 45 for sequentially reading out in synchronization with the device-side clock 76; The same configuration as the Li 45, frame -
When the memory 45 is in the read mode, it is controlled to operate in the write mode, so that the write and read operations are alternately repeated with the frame memory 45. In the read mode, the channel data output to the device is controlled. A frame memory 46 for sequentially reading the data 86 in synchronization with the clock 76 on the apparatus side, and a frame memory 45 or a frame memory 46 in the read mode each time a read frame pulse (RFP) signal 81 is inputted from the apparatus side. , And designates an address number indicating the reading destination of the first bit of the channel data of the first time slot at the start of reading, and thereafter, from the frame memory 45 or the frame memory 46 in synchronization with the device side clock. Read channel data 85 or channel data 86 Each time work is carried out, by sequentially advancing the read destination address number of the channel data 85 or the channel data 86 frame - frame memory 45 or frame -
Memory address register 44 for outputting to memory 46
Whenever the RFP signal 81 is input from the apparatus side, the address number output to the frame memory 45 or the frame memory 46 in the immediately preceding write mode, which has been held until then, is started to be written by the new RFP signal 81. Each time the RFP signal 81 is input from the apparatus side, it is connected to the frame memory 45 or the frame memory 46 in the write mode, and is connected to the frame memory 45 or the frame memory 46. In order to write serial data 84 input from the line side into the frame memory 45 or the frame memory 46,
A memory address register 43 for sequentially designating and outputting an address number corresponding to the serial data 84 to the frame memory 45 or the frame memory 46 in synchronization with the line side clock 72, and a frame memory 45 or a frame in the read mode. The time slot allocated to the first channel data of the channel data 85 and the channel data 86 when the operation of reading the channel data 85 and the channel data 86 to the apparatus side from the memory 46 is designated as a start time slot; The time slot number is specified in advance by the device, and the RFP
Each time the signal 81 is input from the device side, the start time slot designation register 42 for outputting the start time slot number designation signal 77 indicating the number of the start time slot to the memory address register 44, and the selector 17 shown in FIG. When switching from the write mode to the read mode or switching to the mode in the opposite direction, the memory address registers 43 and 4
4 is alternately selected and switched to the frame memory 45 for connection. When the selector 47 selects the memory address register 44 and connects to the frame memory 45, the memory address register 43 is selected and the frame is selected. −
When the selector 47 selects the memory address register 43 and connects to the frame memory 45, the selector 47 selects the memory address register 44 and selects the frame address.
Like the selector 47, the selector 48 alternately selects the memory address register 43 and the memory address register 44 to switch to and connect to the frame memory 46, and the data read from the frame memory 45. Channel data 85 and frame memory 46
A multiplexing unit 49 for time-division multiplexing the channel data 86 read out from the multiplexor, and serial data 83 from the line side are input to the frame memory 45 or the frame memory 46.
A first-in / first-out memory (FIFO memory) 50 for outputting serial data 84 to the controller, and a control unit 41 for controlling writing and reading of channel data to and from the frame memory 45 and the frame memory 46. You.

Next, the operation of the channel reception frame aligner will be described.

The channel receiving frame aligner shown in FIG.
A case where channel data of a channel is received by the device will be described below.

In FIG. 4, first, as in the case of the channel transmission frame aligner of FIG. 2, the time slot number of the start time slot is initially set in the start time slot specification register 42, and the start time slot number specification signal 77 is provided. Is set by Next, when a read lead frame pulse (RFP) signal 81 indicating the beginning of a frame is input to the start time slot designation register 42, the rising timing of the RFP signal 81 causes
The memory address register 44 inputs the start time slot number (ninth time slot) set in the start time slot designation register 42 and stores the first bit of the B channel data received from the line side by the ninth time slot. Set the address number to be used. RFP at the same time
At the timing of the rise of the signal 81, the address number designated by the memory address register 43 at the time of the immediately preceding write operation and held as it is is reset. Further, the RFP signal 81 is also input to the control unit 41.

Control unit 41 receiving RFP signal 81
Controls the selector 47 and the selector 48, and the selector 47 selects the memory address register 43 and
Connected to the memory 45. The control unit 41 sends a control signal 89 to the memory address register 43 connected to the frame memory 45 to control the memory address register 43, so that the memory address register 43 outputs an address number for writing serial data 84 to the frame memory 45. I do. The frame memory 45 enters the write mode in response to the control signal 89 from the control section 41, and writes the serial data 84 according to the address number from the memory address register 43. Also, a selector 48 controlled by the control unit 41 selects the memory address register 44 and connects it to the frame memory 46, and the memory address register 44
Outputs an address number of an address for reading from the frame memory 46 to the frame memory 46. The frame memory 46 receives the control signal 89 from the control unit 41, enters a read mode, reads the channel data 86 according to the address number from the memory address register 44, and reads the channel data 86 read from the frame memory 46. The data 86 is sent to the multiplexer 49.

When the above operation is completed, the control unit 41
Sends a control signal 89 for setting the read mode to the frame memory 45 and a control signal 89 for setting the write mode to the frame memory 46.
The serial data 84 is written into the frame memory 46, and channel data 86 data is read from the frame memory 45 and sent to the multiplexing unit 49.

As described above, the frame memory 15 and the frame memory 16 alternately write the serial data 84 from the line side, and when one of them is writing the serial data 84 input from the line side, The other is channel data 85 or channel data 86 to be transmitted to the device side.
Is repeated from the frame memory 45 and the frame memory 46 alternately.
The channel data 85 and the channel data 86 sent to 9 are multiplexed by the multiplexing unit 49 and sent to the device side as channel data 87. In other words, of the 24 channels of the ISDN primary rate interface line transmitted from the line side, 8 consecutive continuous channels specified in advance.
Channel data of the channel B is transferred to the device side.

FIG. 5 is a timing chart showing an example of the circuit operation of the channel receiving frame aligner shown in FIG. Next, the operation will be described with reference to the timing chart shown in FIG.

(1) of FIG. 5A shows the RFP.
(2) shows the line side clock 72. (3) shows the time slot number corresponding to the channel data and the bit number of the time slot, which are written in the address indicated by the memory address register 43 in synchronization with the line clock 72. (4) shows the device-side clock 76, and (5) shows the time slot number corresponding to the channel data and the channel of the time slot read out from the address indicated by the memory address register 44 in synchronization with the device-side clock 76. Indicates the bit number of the data.

In FIG. 5B, (6) shows RFP of a plurality of frames. (7) is a frame memory 4
5 shows a write or read time slot for 5. (8) shows the state of access to the frame 45.
(9) indicates a read or write time slot for the frame memory 46. (10) indicates the status of access to the frame 46.

As shown in FIG. 5A, after the RFP rises, the memory address register 43 specifies the first bit (TB011) of the channel data of the first time slot at the first line clock on the frame. In the next clock, the second bit (TB012) of the channel data of the first time slot is specified. Further, the memory address register 44 stores the first bit (TB09) of the channel data of the ninth time slot at the first device-side clock of the frame.
1) is specified, and the second clock specifies the second bit (TB092) of the channel data of the ninth time slot. Addressing is performed in this manner, channel data of 24 time slots is written in the frame memory 45 during one frame period, and channel data of 8 time slots is written from the frame memory 46. Data is read. The channel data read from the frame memory 46 is output via the multiplexing unit 49.

As shown in FIG. 5B, in the next one frame period, the channel data of 24 time slots is written in the frame memory 46, and the previous one frame is written from the frame memory 45. The channel data of nine time slots is read from the data written during the program period. By alternately switching the frame memories in this manner, it is possible to transfer channel data from the line side to the device side.

In the above description, the operation of transmitting and receiving B-channel data by the channel transmission frame aligner of FIG. 2 and the channel reception frame aligner of FIG. 4 has been described. The transmission and reception of channel data of the D channel can be performed in the same manner as in the case of the B channel by the mu aligner and the channel receiving frame aligner of FIG. However, the last time slot of the 24 time slots is usually used as the time slot for D-channel data.

In the above description, the case where the channel transmission frame aligner and the channel reception frame aligner for the B and D channels shown in FIG. Is one LSI for controlling ISDN interface,
By providing a channel transmit frame aligner and a channel receive frame aligner for multiple channels,
A plurality of H ₀ channels can be configured by one, and a circuit configuration when configuring a plurality of H ₀ channels can be simplified.

[0073]

As described above, the ISDN of the present invention is
The interface control LSI can designate an arbitrary time slot to be used for the transfer of channel data from a plurality of time slots set for the transfer of the channel data, and performs communication of the channel data transferred in the designated time slot. An input terminal for inputting from the device,
And by providing an output terminal for outputting the channel data to the data communication device to be transferred in the time slot, it is used as a circuit for controlling the H ₀ channel communications, for configuring the H ₀ channel, H ₀ There is an effect that the used channel can be used efficiently without the used channel among the channels being fixed.

The channel data sent from the data communication device and the channel data received by the data communication device are once written alternately into a pair of frame memories,
Further, since it is configured to alternately read, multiplex, and output the data, there is no need for a large number of external circuits for extracting, combining, and controlling the data of the above-mentioned used channels. This has the effect that the number of hardware circuits used as external circuits of the LSI can be significantly reduced.

[0075] Further, the input terminal for inputting a channel data from the data communication device, and data communication by a plurality providing that the output terminal for outputting the channel data to the device, is possible to configure multiple H ₀ channel 1 Can,
This has the effect of simplifying the circuit configuration when configuring a plurality of H ₀ channels.

[Brief description of the drawings]

FIG. 1 is an LSI for controlling an ISDN interface according to the present invention.
It is a block diagram showing one embodiment of.

FIG. 2 is a block diagram showing a circuit configuration of a channel transmission frame aligner used for an ISDN interface control LSI of the present embodiment.

FIG. 3 is a timing chart showing an example of a circuit operation of the channel transmission frame aligner shown in FIG. 2;

FIG. 4 is a block diagram showing a circuit configuration of a channel reception frame aligner used in the ISDN interface control LSI of the present embodiment.

5 is a timing chart showing an example of a circuit operation of the channel reception frame aligner shown in FIG.

FIG. 6 is an explanatory diagram showing a state of writing channel data of each time slot to a frame memory.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 B channel transmission frame aligner 2 D channel transmission frame aligner 3 channel synthesis unit 4 transmission control unit 5 driver 6 receiver 7 reception control unit 8 channel separation unit 9 B channel reception frame aligner 10 D channel reception frame aligner 11 control unit 12 start time Slot designation register 13, 14 Memory address register 15, 16 Frame memory 17, 18 Selector 19 Multiplexing unit 20 First-in first-out memory (FIFO memory) 41 Control unit 42 Start time slot designation register 43, 44 Memory address register 45 , 46 Frame memory 47, 48 Selector 49 Multiplexer 50 First-in first-out memory (FIFO memory) 61 B-channel data 62 D-channel data 6 3, 64 serial data 65 B channel data 66 D channel data 71 channel data 72 line side clock 73, 74 channel data 75 WFP signal 76 device side clock 77 start time slot number designation signal 78 serial data 79 control signal 81 RFP signal 83, 84 Serial data 85, 86 Channel data 87 Channel data 89 Control signal

Claims (6)

[Claims] 1. An ISDN connected between an ISDN primary rate interface line and a data communication device connected to the ISDN primary rate interface line.
ISDN for controlling transfer of channel data between a primary rate interface line and the data communication device
In the interface control LSI, an arbitrary time slot used for the transfer of the channel data can be designated from a plurality of time slots set for the transfer of the channel data, and the channel transferred in the designated time slot can be designated. An input terminal for inputting data from the data communication device, and an output terminal for outputting the channel data transferred in the time slot to the data communication device.
LSI for controlling SDN interface. 2. The ISDN interface control LSI according to claim 1, further comprising a plurality of said input terminals and a plurality of said output terminals. 3. The ISDN interface control LSI according to claim 2, wherein one of each of said plurality of input terminals and output terminals is defined by said ISDN primary rate interface line. And an input terminal and an output terminal for transferring channel data of the B channel defined by the ISDN primary rate interface line. LSI for controlling the ISDN interface. 4. The ISDN interface control LSI according to claim 1, wherein: (A) a first register for designating an arbitrary time slot used for transfer of the channel data by an external setting signal as an initial setting. And a write operation for sequentially writing one frame of channel data of the channel data from the data communication device in the write mode in accordance with an address corresponding to the time slot specified by the register, and a write operation in the write mode in the read mode. A first pair of frame memories for alternately performing a read operation for reading the channel data for the one frame, and the channel from the data communication device alternately read from the first pair of frame memories. Channel transmission for multiplexing and outputting data (B) A second register for designating an arbitrary time slot used for transfer of the channel data by an external setting signal as an initial setting, and a time slot designated by the register. A write operation for sequentially writing one frame of the channel data of the channel data from the ISDN primary rate interface line in the write mode in accordance with the address to be written, and a channel for the one frame written in the write mode in the read mode A second pair of frame memories for alternately performing a read operation for reading data, and the channel data from the ISDN primary rate interface line alternately read from the second pair of frame memories. Multiplexed channel output frame Muaraina, ISDN interface control LSI, characterized in that it comprises a. 5. The LSI for controlling an ISDN interface according to claim 4, further comprising a plurality of said channel transmission frame aligners and a plurality of channel reception frame aligners, wherein said plurality of said channel transmission frame aligners and said plurality of channel reception frame aligners are provided. Among them, one is a channel transmission frame aligner and a channel reception frame aligner for transferring channel data of the D channel defined by the ISDN primary rate interface line, and the rest are the ISDN primary rate rates. An IS characterized by a channel transmission frame aligner and a channel reception frame aligner for transferring channel data of a B channel defined by an interface line.
LSI for controlling the DN interface. 6. The ISDN interface control LSI according to claim 5, wherein an output of a channel transmission frame aligner for transferring channel data of said B channel and a channel transmission for transferring channel data of said D channel. The output of the frame aligner is combined with the IS as the channel data from the data communication device.
Combining means for transmitting to the DN primary rate interface line, output of a channel receiving frame aligner for transferring the channel data of the B channel, and channel receiving for transferring the channel data of the D channel LS for controlling an ISDN interface, comprising combining means for combining the output of a frame aligner and sending out the channel data from the ISDN primary rate interface line to the data communication device.
I.