JPH0447818A - Signal conversion circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of a written data signal by providing signal generators for generating timing signals read out from plural dual port RAM. CONSTITUTION:According to a write timing signal T1, a multiple data signal D1 to be inputted synchronously with a timing signal S1 is written into RAM 1, RAM 2 and RAM 3. Next, according to read timing signals T2-1, T2-2 and T2-3, data signals D2, D3 and D4 to be inputted synchronously with a timing signal S2 are read from the RAM 1, RAM 2 and RAM 3. The data signal string D2 can be read from the RAM 1 in short delay time theta2 within one frame from the T1, the data signal string D3 can be read from the RAM 2 in delay time theta3 from the T1, and the data signal string D4 can be read from the RAM 3 in delay time theta4 from the T1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal conversion circuit, and particularly to a signal conversion circuit that converts an input signal in which a plurality of data signal sequences are time-division multiplexed in one frame into The present invention relates to a signal conversion circuit that outputs a plurality of output data signal sequences in parallel regardless of the relationship.

[Conventional technology]

A conventional signal conversion circuit of this type is shown in a block diagram in FIG. 3, and the arrangement and timing of a data signal train is shown in a timing chart in FIG. As shown in FIG. 4, the timetable multiplexed data signal D1 input now is
Assume that three pieces of data 1, data 2, and data 3 are serially arranged in a frame. The conventional circuit shown in FIG. 3 converts such multiple data signal D1 into data 1, 2, 3
RAM 7 that writes and reads each time,
A signal generator 8 generates a write timing signal T1 to the RAM 7 for each frame head based on an externally input timing signal s1 that determines the frame head of the multiplexed data signal D1, and three parallel output data signals. Column D
2. D3. ．． Based on the externally input timing signal s2 that determines the beginning of D4, that is, the beginning of data 1,
A signal generator 9 that generates a read signal T2 from the RAM 7, a shift circuit 10, 11, 12 that sequentially shifts the read data signal in units of data 1, 2, 3, and a parallel output data signal string D2. D3. It is composed of a signal processing circuit 6 that processes D4 in three groups.

Next, the timing of signal conversion in the conventional example will be explained with reference to FIG. The multiplexed data signal D1, which is input in synchronization with the timing signal S1, is sequentially written from data 1 to data 3 into the RAM 1 by the write timing signal T1.

Next, data is read from the RAM 7 using a read timing signal T2 that is synchronized with the timing signal S2. At this time, the difference θ in the positional relationship between the write and read timing signals Tl and T2 is determined under control conditions that allow writing and reading in the RAM 7. When the data 3 is temporarily stored in the shift circuit 10, the data signal string D4 (
Data 3), data signal string D3 (data 2), and data signal string D2 (data 1) are output in parallel with their heads almost aligned as shown in FIG. Using this procedure, each frame is divided into three groups, from the data 1 group to the data 3 group, and output in parallel.

[Problem to be solved by the invention]

The conventional signal conversion circuit described above has one RAM, and in digital signal processing, when data is converted into a signal, there are always constraints on the delay time θ for writing to and reading from the RAM. The disadvantage is that the timing is inevitably delayed, resulting in a delay of about 1.5 to 2 frames. As the number of data signal sequences increases and the data becomes longer, the number of shift circuits increases, the circuit scale becomes larger, and the delay time to the signal processing circuit also increases.

[Means to solve the problem]

The signal conversion circuit of the present invention includes a plurality of dual-baud RAMs that write and read a plurality of data multiplexed into an input multiplexed data signal for each data, and a plurality of dual-port RAMs. It has a first signal generating means for generating a common write signal for writing signals, and a second signal generating means for generating a read signal for reading data written from each of the dual port RAMs.

〔Example〕

Next, the present invention will be explained with reference to the drawings. The block diagram of FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of the present embodiment when converting a multiplexed data signal obtained by multiplexing three data signals into three groups of data signal sequences. This is a timing chart. The embodiment shown in FIG. 1 includes RAMI, 2.3, which is a dual-baud RAM for writing and reading the multiplexed data signal D1, similar to the conventional example, and RAMI, 2.3, which is a dual-baud RAM that writes and reads the multiplexed data signal D1, and a timing signal S1 that determines the beginning of data 1 of the multiplexed data signal. 3, a signal generator 4 that generates a write timing signal T1, and three data signal strings D2. D3.
The timing signal S2 and the timing signal S1 that determine the beginning of the RAMI, 2.3 and 2.3 are respectively read out signals T2-1°T2-2. It is composed of a signal generator 5 that generates T2-3 and a signal processing circuit 6. Here, the dual port RAM is a RAM that has separate input ports for input data signals and output ports for output data signals, and can perform writing and reading simultaneously.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. The multiplexed data signal D1, which is input in synchronization with the timing signal S1, is written into the RAM by the timing signal T1.
I, RAM2. Write to RAM3. Next, data signal D2. which is output in synchronization with timing signal S2. D.B., D.
4 as the timing signal T2-1. T2-2. T2
-3 causes RAMI, RAM2. Read from RAM3. Here, RAMI, RAM2.3 is a dual port RAM, so regardless of the positional relationship between timing signals SL and S2, RAMI, RAM2. It is possible to write and read data in RAM3. Note that each data 1, 2, and 3 in the multiplexed data signal D1 is R
AM 1.

2.3 are written at the same time. Further, the read timing signal T2-1. T2-2. T2-3 is RAMI, 2.
3, data signal string D2 (data 1) is read out from RAM1 with a short delay time θ2 within one frame from T1, and data signal string D3 (data 2) is read out from RAM2 from T1. It is possible to read the data signal sequence D4 (data 3) from the RAM 3 with a delay time θ3 from T1 with a delay time θ4.

That is, the delay time θ2. θ3. θ4 is signal processing circuit 6
The data can be read within an arbitrary delay time depending on the processing request. According to this configuration, as shown in FIG. 2, data 1 in the multiplexed data signal is output to the data signal string D2 at least one frame earlier than in the conventional circuit configuration.

In other words, the data delay for one frame is eliminated. Furthermore, even if the length of data in the multiplexed data signal changes, there is no need to change the circuit configuration, and the read timing signal T2-1. T2-2. Just change T2-3.

〔Effect of the invention〕

As explained above, the present invention uses a plurality of dual-port RAMs, and each RAM has a signal generator that generates a read timing signal, thereby reducing the delay time of a written data signal. It has the effect of Further, even if the configuration or length of the data signal changes, there is no need to increase the circuit scale or change the circuit, and the effect can be achieved with the same circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of this embodiment, FIG. 3 is a block diagram of a conventional signal conversion circuit, and FIG. 4 is a time chart of a conventional example. 1.2.3...Dual port) RAM, 4.5...
Signal generator, 6... Signal processing circuit, 7... RAM,
8.9...Signal generator, 10.11.12...Shift circuit.

Claims (1)

[Claims] a plurality of dual port RAMs for writing and reading a plurality of data multiplexed into an input multiplexed data signal for each data; and a plurality of dual port R
A first signal generating means for generating a common write signal for writing a data signal into the AM, and a second signal generating means for generating a read signal for reading data written from each of the dual port RAMs. Characteristic signal conversion circuit.