JP2765887B2 - Data multiplexing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplexing method, and more particularly to a data multiplexing method for multiplexing arbitrary data in an arbitrary time slot in a digital data interconnect device.

[Conventional technology]

2. Description of the Related Art In a case where arbitrary data is multiplexed with input data and output by a time-division multiplexing type data interconnection device or the like, a method of switching between input data and arbitrary data at desired timing is often used. Usually this arbitrary data is
It is stored in a memory in advance, and can be rewritten or prepared as needed.

FIG. 4 is a block diagram showing an example of a conventional interconnection data multiplexing method. In FIG. 4, input data is alternately supplied to a first data memory 202 and a second data memory 203 by a switch 201 for each frame, and an address signal supplied from a binary counter 208 via a selector 206 or a selector 207. Is written sequentially.

For example, input data supplied from the switch 201 in a certain frame time is sequentially written to the first data memory 202 by an address signal generated by the binary counter 208 and given through the selector 207. on the other hand,
At the same time, the second data memory 203 is controlled by the address signal given through the selector 206 in accordance with the interconnection data stored in the address memory 209, which is an interconnection control memory in advance, from the second data memory 203 at the time of the immediately preceding frame. Reads the written input data. At this time, the selector 204 selects data from the data memory 203. By repeating the above operation for each frame, the input data becomes the interconnected (line edited) output data. Thereafter, the output data is multiplexed with arbitrary data stored in the multiplex data memory 210 by the selector 205 and output. That is, the multiplexed data is output by selecting the selector 205 to the multiplexed data memory 210 at the timing synchronized with the binary counter 208 and at the timing of multiplexing any required data. The multiplexing timing is based on a multiplexing control signal generated from an insertion timing generation circuit 211 to which the insertion time slot stored in the insertion time slot memory 212 and the output of the binary counter 208 are input.

[Problems to be solved by the invention]

In the conventional data multiplexing method described above, a multiplexed data memory for storing arbitrary data, an insertion time slot memory for storing a time slot for multiplexing the data, and a timing at which the time slot passes through the selector 205 Therefore, an insertion timing generating circuit for operating the selector is required. For this reason, there is a disadvantage that the apparatus is often forced to be large and expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data multiplexing system which eliminates the above-mentioned drawbacks and realizes a compact and low-cost device.

[Means for solving the problem]

The data multiplexing method according to the present invention includes: a first and a second data memory having a two-sided configuration for sequentially storing input data alternately supplied for each frame by a switch; On the other hand, when reading data from the first or second data memory at a time when writing of the input data is not performed, the data is stored in the address memory so that the data can be read in a desired order. Interconnect data arranged such that time slots interconnect with each other; and data read from the second data memory when the switch is selecting the first data memory side. When the data memory side is selected, the data read from the first data memory is alternately selected. From the address memory in which multiplex control signal data and multiplex data are stored at predetermined bit positions of independent bits in the same address, according to the state of the stored bits of the multiplex control signal data. , And a second selector for selecting the multiplexed data or the data output from the first selector.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of use of an address memory, and FIG. 3 is a timing chart for explaining the operation of the embodiment.

The data multiplexing method shown in FIG. 1 includes a switch 101 for alternately supplying input data for each frame, and a first and second switch having two surfaces for storing input data alternately supplied for each frame by the switch. Data memory 102,103
A binary counter 108; an address memory 109 for storing interconnection data, multiplexed control signal data and multiplexed data for enabling data to be read from the memories 102 and 103 in an arbitrary order; an output of the binary counter 108 and an address memory 109. 2: 1 selectors 106 and 107 for switching the read signal from the first data memory and a first data memory 1
2: 1 selector for switching read data from 02 and read data from the second data memory 103
104, and a two-to-one selector 105 that is controlled by the multiplex control signal data stored in the address memory 109 and switches between multiplexed data stored at the same address and data from the data memories 102 and 103. .

Figure 2 is an example of using the address memory 109, the address has a 16-bit D ₁₅ to D _0, 1 bit D ₁₅ is a multiplexing control signal data. Bit D ₁₅ is, if "0" without multiplexing, indicating that multiplexing if "1". Address 0H, bit D ₁₅ of 1H is "0", in this case bit D ₁₂
Interconnect data is stored in the to D _0. Bit D ₁₅ of the address 2H is "1", multiple data is stored in the bit D ₇ to D ₀ at the same address. In FIG. 2, the bits marked with a cross may be “0” or “1”.

The above example of the use of the address memory 109 is as follows.
Time slots 0H and 1H depending on the data stored in H
This is an example of interconnecting 8-bit data and multiplexing data of "10101010" in time slot 2H. Here, when multiplexing certain data with input data, the data read from the address memory 109 at the multiplexing timing is arbitrary. Therefore, as the address 2H address memory of FIG. 2, with the required multiplex data into the data of the address (D ₇ ~D _0), the multiplexing control signal data for selecting and outputting the multiplexed data itself (D ₁₅ )
Is added to the same address,
5 allows arbitrary data to be multiplexed on output data.

Next, the operation of the embodiment of FIG. 1 will be described with reference to the timing chart of FIG.

The input data is alternately supplied to the first address memory 102 and the second data memory 103 by the switch 101 for each frame. FIG. 3A shows the frame numbers F0 and F
, And FIG. 3 (e) shows input data f0, f1, f
2, f3... The selectors 106 and 107 select the output (FIG. 3 (b)) of the binary counter 108 and use it as an address signal. With this address signal, input data is sequentially written to the first and second data memories 102 and 103.

According to the timing chart of FIG. 3, the input data f1 supplied from the switch 101 at the time of the frame number F1
Is supplied to the first data memory 102 by an address signal generated by the binary counter 108 and supplied through the selector 107.
Are written sequentially. FIG. 3D shows the switching signal of the selector 107. On the other hand, during the time of the same frame number F1, the second data memory 103 is controlled by the address signal given through the selector 106 in accordance with the interconnection data previously stored in the address memory 109, and the time of the frame number F0 The input data f0 written in is read. At this time, the selector 104 selects the data f0 from the second data memory 103. FIG. 3C shows a switching signal of the selectors 104 and 106.

By repeating the above operation for each frame, the input data becomes the interconnected (line-edited) output data. FIG. 3 (f) shows the output of the selector 104, that is, the interconnected output data. The output data is
The signal is input to one input of the selector 105.

Required multiplexed data is read from the address memory 109 and input to the other input of the selector 105. At the same time, a multiplex control signal (FIG. 3 (g)) for selecting and outputting the multiplex data from the same address in the address memory 109 is
It is input as a signal for controlling switching of the selector 105. The selector 105 selects the address memory 109 based on the multiplexing control signal and multiplexes the multiplexed data with the output data. FIG. 3 (h) shows output data, and hatched portions indicate multiplexed data.

〔The invention's effect〕

As described above, in the present invention, by adding one bit as multiplex control signal data to the address memory,
Arbitrary data can be multiplexed with input data. In particular, the present invention is applied to a case where a large amount of data is multiplexed and the speed is high, which is effective in reducing the number of memory ICs used and reducing the size of the device.

[Brief description of the drawings]

 FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of use of an address memory, FIG. 3 is a timing chart for explaining the operation of the embodiment, and FIG. It is a block diagram. 101, 201 ... Switch 102,202 ... First data memory 103,203 ... Second data memory 104,204,105,205,106,206,107,207 ... Selector 108,208 ... Binary counter 109,209 ... Address memory 210 ... Multiple data memory 211 ... Insertion time slot memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/00-3/26 H04L 5/22-5/26

Claims (1)

(57) [Claims] 1. A two-sided first and second data memory for sequentially storing input data alternately supplied for each frame by a switch; and a first and second data memory. When reading data from the first or second data memory at a time when writing of the input data is not performed,
Interconnect data arranged such that time slots are interconnected in an address memory so that data can be read in a desired order; and said second data when said switch selects the first data memory side. A first selector for alternately selecting data read from the data memory of the first data memory and data read from the first data memory when the switch selects the second data memory. At a predetermined bit position in an independent bit in the same address, from the address memory in which the multiplex control signal data and the multiplex data are respectively stored, according to the state of the bit stored in the multiplex control signal data, And a second selector for selecting multiplexed data or data output from the first selector. Data multiplexing scheme to be.