JP2906851B2 - Time-division multiplex audio transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplex audio transmitting apparatus for transmitting a plurality of audio data to time slots designated by a time-division multiplex communication path.

[0002]

2. Description of the Related Art Due to the recent development of PCM technology and LSI technology, a voice transmitting device for transmitting a voice signal directly stores voice data to be transmitted as digital data of a PCM code in a memory, and transmits the data at a transmission timing. In addition, a method of sequentially reading and transmitting the data has been used. When a plurality of messages are transmitted by the voice transmission device, the voice transmission device is assigned to correspond to the message, data is set, and a transmission time slot is connected to a communication path for transmission.

[0003]

In this conventional voice transmitting device, a voice transmitting device is required for each transmission message.
In addition, since a multiplexing device for connecting to a time-division communication path requires a switch to make an arbitrary connection, a large amount of hardware is required to transmit data to a large number of lines. was there.

[0004]

According to the present invention, there is provided a time-division multiplexed audio transmitting apparatus, comprising: a control device for instructing data editing and transmission; a memory for storing audio signal data to be transmitted; Means for writing in accordance with an instruction from the control device, and 125 μS for providing a time slot position for time-division multiplexing and transmitting an audio signal.
A period time slot counter, a register for holding transmission control information for each time slot, a transmission flag in the register, a head address of the audio signal data on the memory, and a transmission address based on an instruction from the control device. Setting means for setting the number of bytes and setting the transmission byte number to "0"; first reading means for reading information from the register for each time slot in synchronization with the output of the time slot counter; An adder for adding the head address and the transmission byte number in the read information to calculate an address of the transmission data on the memory; and reading the audio signal data from the memory using the output of the adder as an address. Second reading means, sending means for sending the read data to a time-division communication path, A comparator that operates only when the sending flag of the information read from the register is “1”, compares the sending byte number with the sending byte number, and outputs a match signal when the numbers match. A resetting means is provided for setting the sending flag to "0" when the output signal matches, and adding 1 to the sending byte number when not matching, and setting the register again.

Further, another time-division multiplex audio transmitting apparatus of the present invention includes a hardware queue corresponding to each of the transmission time slots, and writes transmission information from the control device to the hardware queue and reads out transmission information from the register. If the sending flag of the received data is "0", the hardware queue corresponding to each time slot is checked, and if the data exists in the hardware queue, the data is read out and set in the register. Features.

[0006]

[0007]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a time division multiplexed audio transmitting apparatus according to the present invention, FIG. 2 is a diagram showing an example of a data structure corresponding to an address of a register in FIG. 1, and FIG.
FIG. 4 is a block diagram showing a second embodiment of the time-division multiplexed voice transmitting apparatus according to the present invention.

As shown in FIG. 1, an m-multiplexed time-division multiplexed voice transmitting apparatus according to the first embodiment has a control unit (hereinafter referred to as CTL) 1.
, A time slot counter (hereinafter referred to as CNT) 2, a register data selector (hereinafter referred to as RDS) 3, a register address selector (hereinafter referred to as RAS) 4, and a memory (hereinafter referred to as ME).
M) 5 and a memory address selector (hereinafter MAS) 6
, A register (hereinafter REG) 7, a parallel / serial converter (hereinafter P / S) 8, an adder (hereinafter ADD) 9,
11 and a comparator (hereinafter referred to as CMP) 10.

Next, the operation of the first embodiment will be described. The digitized audio data is edited by the CTL 1 and written into the MEM 5. The MAS 6 switches between a data write / read address from the CTL 1 and a data transmission address. The data written on MEM5 is shown in FIG.
As shown in the figure, the first data is a
One byte is written, and its transmission time is a1 × 125 μS
It is. Similarly, a plurality of data a2 bytes on MEM5,
Ａa5 bytes are written to addresses A2, ＡA5, respectively. The timing at which data is time-division multiplexed and transmitted is given by CNT2. CNT2 counts from 0 to m-1 during 125 [mu] S. Transmission is instructed for each time slot, and is performed by writing transmission control information (transmitting flag, head address, transmission byte number, transmission byte number) from CTL1 to REG7.

The data set in REG7 has the configuration shown in FIG. 2. When the first data of register address 0 is transmitted, "1" is set in the transmission flag, the head address A1 of the audio signal data, and the transmission data. Set the number of bytes a1,
Set 0 to the transmission byte number. RAS4 is CNT2 which gives the timing of writing from CTL1 and sending data.
Select the output of RDS3 changes the output data of REG7 by ADD9 and CMP11 and CT
One of the data at the time of setting from L1 is selected. Data is transmitted in the following procedure for each time slot.

The output of CNT2 is REG through RAS4.
7, and data corresponding to the address is output from REG7. When outputting the first data, REG7
ADD11 adds the start address A1 of the transmission data from the transmission data and the transmission byte number 0, and outputs the ME through the MAS6.
M5. ME based on given address
The data read from M5 is serial-converted by P / S8 and output to the time division multiplex communication path.

If the data being read from the REG 7 is "1" in the data transmission flag, the ADD 9 adds 1 to the transmission byte number, and the CMP 10 compares the transmission data byte number a1 with the transmission byte number 0. And
If they match, the sending flag is set to "0", and writing to REG7 is performed via RDS3. If they do not match, writing is performed directly to REG7 via RDS3. If the sending flag is "0", nothing is executed. Therefore, the transmission byte number is repeated by adding 1 to the transmission byte number until the transmission byte number matches the transmission data byte number.
The read address of MEM5 is given by the output of MEM5.
Byte data is transmitted in the designated time slot.

Next, in the second embodiment shown in FIG.
TL101, CNT102, RDS103, 104, R
AS105, MEM111, MAS112, REG11
0, P / S117, ADD114, 116, CMP11
5 are CTLs 1 and C of the same name in the first embodiment, respectively.
NT2, RDS3, RAS4, MEM5, MAS6, R
EG7, P / S8, ADD9, 11, and CMP10 have the same functions. The second embodiment is different from the first embodiment in that hardware queues (hereinafter Q
UE) 106 and 107, a hardware queue output selector (hereinafter QSL) 108, an output ready signal selector (hereinafter RDY) 109, and a register write control circuit (hereinafter WRC) 113.

The description of the sending operation in the second embodiment is the same as that of the first embodiment, but the following procedure is added.
When the CTL 101 instructs transmission in the first time slot, the input ready signal of the QUE 106 is confirmed and data is written. The format of the data is the same as that in the case of writing to the REG 110, but writing is possible only for the capacity of the QUE. When data exists in the QUE 106, an output ready signal is output. Output ready signal is RDY
At 109, selection is made for each time slot based on the signal from the CNT. The output of REG110 is ADD114
And to the WRC 113 via the CMP 115. The signal from RDY109 is ready for output and REG1
If the transmitting flag of the output of No. 10 is “0”, QUE
RDS103 and RDS1
04 to REG110.

The RDS 103 is controlled by the output of the WRC 113. When the transmission flag of the output of the REG 110 is “1” and when there is no data in the QUE 106, the output of the REG 110 is set to the ADD 104 and the CMP 1
The operation is continued by being rewritten via 15. Therefore, when a plurality of data are set in the QUEs 106 and 107, the data is sequentially taken out from the QUEs 106 and 107, set in the REG 110, and transmitted.

In each of the first and second embodiments, the adaptive difference PCM signal data is stored
According to the present embodiment, it is possible to read and transmit data of the number of bits corresponding to the period of 25 μS.
Memory can be saved .

[0017]

As described above, according to the present invention, in a time division multiplex audio transmitting apparatus for sequentially reading out and storing data edited and stored in a memory, the audio signal data to be transmitted is stored in the memory, Give slot position 1
In synchronization with the output of the time slot counter having a period of 25 μS, the transmission control information (transmission flag, head address, transmission byte number, transmission byte number) for each time slot held in the register is used to store the transmission data on the memory. By calculating the address and performing transmission completion control, it is possible to transmit the data edited and stored in the memory to the time slot specified by the instruction from the control device for the specified time. This has the effect of realizing higher capacity and larger capacity.

The time-division multiplex audio transmitting apparatus has a hardware queue corresponding to each transmission time slot, writes transmission control information in the hardware queue according to an instruction from the control device, and transmits data read from the register. When the middle flag is "0", the hardware queue corresponding to each time slot is checked, and if there is data in the hardware queue, this is read out and set in a register, thereby connecting and transmitting a plurality of messages. In this case, there is an effect that control of the control device becomes very simple.

[0019]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a time-division multiplex audio transmission apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of a data configuration corresponding to an address of a register in FIG. 1;

FIG. 3 is a diagram illustrating an example of a data configuration on a memory in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the time-division multiplex audio transmitting apparatus according to the present invention.

[Explanation of symbols]

1,101 Controller (CTL) 2,102 Time slot counter (CNT) 3,103,104 Register data selector (RD)
S) 4,105 Register address selector (RAS) 5,111 Memory (MEM) 6,112 Memory address selector (MAS) 7,110 Register (REG) 8,117 Parallel / serial converter (P / S) 9,11 , 114, 116 Adder (ADD) 10, 115 Comparator (CMP) 106, 107 Hardware queue (QUE) 108 Hardware queue output selector (QSL) 109 Output ready signal selector (RDY) 113 Register write control circuit (WRC) )

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-24797 (JP, A) JP-A-63-222570 (JP, A) JP-A-57-15559 (JP, A) JP-A-2- 294137 (JP, A) JP-A-1-162036 (JP, A) (58) Fields studied (Int. Cl. ⁶ , DB name) H04Q 11/04

Claims (2)

(57) [Claims] A controller for instructing data editing and transmission; a memory for storing audio signal data to be transmitted;
Writing means for writing the audio signal data into the memory in accordance with the instruction of the control device; and 125 μm for providing a time slot position for time-division multiplexing and transmitting the audio signal.
A time slot counter of S period, a register for holding transmission control information for each time slot, a transmission flag in the register based on an instruction from the control device, and a start address of the audio signal data on the memory; Set the number of transmission bytes and set the transmission byte number to "0"
Setting means for setting information, first reading means for reading information from the register for each time slot in synchronization with the output of the time slot counter, and the head address and the transmission byte in the information read from the register. An adder for adding an address to calculate the address of the transmission data on the memory; second reading means for reading the audio signal data from the memory using the output of the adder as an address; A transmitting means for transmitting to the communication path, operating only when the transmitting flag of the information read from the register is "1", comparing the transmitted byte number with the transmitted byte number, and outputting a match signal The output flag is set to "0" when the output signal matches the output comparator, and when the output signal does not match, the output signal is set to "0". Division multiplexing the audio delivery device when anda resetting means for setting to 1 the addition to the register again sending byte number. 2. A hardware queue corresponding to each of the transmission time slots, transmission information is written from the control device to the hardware queue, and the transmission flag of data read from the register is “0”. 2. The time-division multiplexed audio transmission according to claim 1, wherein in said case, said hardware queue corresponding to each of said time slots is checked, and if data exists in said hardware queue, said data is read out and set in said register. apparatus.