JPH0662479A - Time-division multiplexed sound sending device - Google Patents

Abstract

PURPOSE:To send plural audio data to designated time slots of a time-division multiplexer channel. CONSTITUTION:When the output of a time slot counter (CNT) 2 is given to a register (REG) 7 through a register address selector (RAG) 4, data corresponding to the address is outputted. A head address A1 of first sent data from the REG 7 and sent byte number O are added by an adder ADD 11, and the result is given to a memory (MEM) 5 through a memory address selector (MAS) 6. Data read out from the MEM 5 is converted to serial data by parallel/serial converter (P/S) 8 and is outputted to the time-division multiplexer channel. When a sending flag in data read out from the REG 7 is '1', one is added to the sent byte number by an ADD 9, and a CMP 10 compares a number a1 of sent data bytes and sent byte number 0 with each other, and the sending flag is set to '0' and is written in the REG 7 through a register data selector (RDS) 3 in the case of coincidence, but the sending flag is written as it is in the case of noncoincidence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex voice transmitting apparatus for transmitting a plurality of voice data to respective time slots designated by a time division multiplex communication channel.

[0002]

2. Description of the Related Art Due to the recent development of PCM technology and development of LSI technology, a voice transmitting apparatus for transmitting a voice signal directly stores voice data to be transmitted as digital data of PCM code in a memory, and outputs it at a transmission timing. In addition, a method of sequentially reading and sending has been used. When a plurality of messages are sent by this voice sending device, the voice sending device is assigned corresponding to the message, data is set, and the call is connected to the sending time slot for sending.

[0003]

This conventional voice transmitting apparatus requires a voice transmitting apparatus for each outgoing message,
In addition, since a switch is required in order for the multiplexer for connecting to the time division speech path to make an arbitrary connection, the amount of hardware increases in order to send data to a large number of lines. was there.

[0004]

SUMMARY OF THE INVENTION A time division multiplex voice transmission apparatus of the present invention includes a control unit for instructing data editing and transmission, a memory for storing voice signal data to be transmitted, and the voice signal data in the memory. And a time slot position for time-division-multiplexing and transmitting a voice signal and a writing means for writing
A cycle time slot counter, a register for holding transmission control information for each time slot, a transmission flag, a start address of the audio signal data on the memory, and transmission to this register based on an instruction from the control device. Setting means for setting the number of bytes and "0" for the sending byte number, first reading means for reading information from the register for each time slot in synchronization with the output of the time slot counter, and the register An adder that calculates the address of the transmitted data on the memory by adding the start address in the read information and the transmitted byte number, and reads the audio signal data from the memory using the output of the adder as an address. Second reading means, sending means for sending the read data to a time division speech path, and A comparator which operates only when the in-transmission flag of the information read from the register is "1", and outputs a coincidence signal when the transmission byte number and the transmission byte number match and a comparator of this comparator; When the output signals match, the sending flag is set to "0", and when the output signals do not match, the sending byte number is incremented by 1 and set again in the register.

Further, another time division multiplex audio transmission device of the present invention comprises a hardware queue corresponding to each of the transmission time slots, writes transmission information from the control device to the hardware queue, and reads from the register. If the in-transmission flag of the transmitted data is “0”, the hardware queue corresponding to each time slot is checked, and if the data exists in the hardware queue, it is read and set in the register. Characterize.

In each of the above configurations, the adaptive differential PCM signal data may be stored in the memory, and the data of the number of bits corresponding to the 125 μS cycle may be read and transmitted.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing a first embodiment of a time division multiplex audio transmitting apparatus of the present invention, FIG. 2 is a diagram showing an example of a data structure corresponding to addresses of registers in FIG. 1, and FIG. 3 is FIG.
FIG. 4 is a diagram showing an example of the data structure on the memory, and FIG. 4 is a block diagram showing a second embodiment of the time division multiplex voice transmission device of the present invention.

As shown in FIG. 1, a m-time-division time-division multiplex audio transmitting apparatus of the first embodiment is a control apparatus (hereinafter CTL) 1
A time slot counter (hereinafter CNT) 2, a register data selector (hereinafter RDS) 3, a register address selector (hereinafter RAS) 4, a memory (hereinafter ME).
M) 5 and memory address selector (hereinafter MAS) 6
A register (hereinafter REG) 7, a parallel / serial converter (hereinafter P / S) 8, an adder (hereinafter ADD) 9,
11 and a comparator (hereinafter referred to as CMP) 10.

Next, the operation of the first embodiment will be described. The digitized voice data is edited by CTL1 and written in MEM5. The MAS 6 switches the data write / read address from the CTL 1 and the data send address. The data written on the MEM5 is shown in FIG.
As shown in, the first data is a from the start address A1.
One byte is written, and the transmission time is a1 x 125 μS
Is. Similarly, a plurality of data a2 bytes on MEM5,
.About.a5 bytes are written to addresses A2 and .about.A5, respectively. The timing at which data is time division multiplexed and transmitted is given by CNT2. CNT2 counts from 0 to m−1 in 125 μS. The sending instruction is given for each time slot, and the sending control information (the sending flag, the start address, the sending byte number, and the sending byte number) is written from CTL1 to REG7.

The data set in REG7 has the structure shown in FIG. 2, and in the case of the first data transmission of register address 0, "1" is set in the transmission flag, the start address A1 of the audio signal data and the transmission data. Set the number of bytes a1,
Set 0 to the sending byte number. RAS4 gives the timing of writing from CTL1 and timing of data transmission CNT2
Select the output of. RDS3 changes the output data of REG7 by ADD9 and CMP11 and CT
Either of the data at the time of setting from L1 is selected. Data is transmitted in the following procedure for each time slot.

The output of CNT2 is REG4 via RAS4.
7 and the data corresponding to the address is output from REG7. When outputting the first data, REG7
The start address A1 of the transmission data from the transmission source and the transmission byte number 0 are added by the ADD 11, and the ME is transmitted via the MAS 6.
Given to M5. ME based on the given address
The data read from M5 is serially converted by P / S8 and output to the time division multiplex communication path.

Further, in the case of the data read from REG7, when the sending flag in the data is "1", 1 is added to the sending byte number in ADD9, and the sending data byte number a1 and sending byte number 0 are compared in CMP10. Then
If they match, the sending flag is set to "0" and the data is written to REG7 via RDS3. If they do not match, the data is written to REG7 via RDS3. If the sending flag is "0", nothing is executed. Therefore, the sending byte number is incremented by 1 and repeated until the sending byte number matches the sending data byte number.
The read address of MEM5 is given by the output of
Bytes of data are sent in the designated timeslot.

Next, in the second embodiment shown in FIG. 4, C
TL101, CNT102, RDS103, 104, R
AS105, MEM111, MAS112, REG11
0, P / S 117, ADD 114, 116, CMP11
5 are CTL1 and C of the same name in the first embodiment, respectively.
NT2, RDS3, RAS4, MEM5, MAS6, R
It has the same function as the EG7, P / S8, ADD9, 11, and CMP10. The second embodiment has a hardware queue (hereinafter Q
UE) 106 to 107, a hardware queue output selector (hereinafter QSL) 108, an output ready signal selector (hereinafter RDY) 109, and a register write control circuit (hereinafter WRC) 113.

The description of the sending operation in the second embodiment is similar to that in the first embodiment, but the following procedure is added.
When instructing transmission from the CTL 101 in the first time slot, the input ready signal of the QUE 106 is confirmed and data is written. The data format is the same as the case of writing to the REG 110, but writing is possible only for the capacity of the QUE 106. When the QUE 106 has data, an output ready signal is output. Output ready signal is RDY
At 109, each time slot is selected based on the signal from the CNT 102. The output of REG110 is ADD114
And provided to WRC 113 via CMP 115. The signal from RDY109 is ready for output and REG1
If the in-transmission flag of the output of 10 is “0”, QUE
RDS103 and RDS1 by extracting data from 106
Write to REG 110 via 04.

The RDS 103 is controlled by the output of the WRC 113. When the transmission flag of the outputs of the REG 110 is “1” and when the QUE 106 has no data, the outputs of the REG 110 are the ADD 104 and the CMP 1
It is rewritten via 15 and the operation continues. Therefore, when a plurality of data is set in the QUE 106, 107, the data is sequentially taken out from the QUE 106, 107 and set in the REG 110 for transmission.

In each of the configurations of the first and second embodiments, the adaptive differential PCM signal data is stored in the memory and stored as 1
It is possible to adopt a configuration in which data having the number of bits corresponding to the 25 μS cycle is read and transmitted.

[0017]

As described above, according to the present invention, in a time division multiplex audio transmitting apparatus for sequentially reading out and transmitting the data edited and accumulated in the memory, the audio signal data to be transmitted is accumulated in the memory and the time signal is transmitted. Give slot position 1
In synchronization with the output of the time slot counter of 25 μS cycle, the transmission control information (transmission flag, start address, transmission byte number, transmission byte number) for each time slot held in the register is used to store the transmission data in the memory. By calculating the address and controlling the sending completion, the data edited and stored in the memory can be sent to the time slot specified by the instruction from the control device for the specified time. This has the effect of realizing high capacity and large capacity.

Also, in this time division multiplex audio transmission device, each device has a hardware queue corresponding to each transmission time slot, writes the transmission control information in the hardware queue according to an instruction from the control device, and transmits the data read from the register. When the middle flag is "0", the hardware queue corresponding to each time slot is checked, and if there is data in the hardware queue, it is read and set in the register, and multiple messages are connected and sent. This has the effect of making the control of the control device very simple.

Further, by storing the adaptive difference PCM signal data in the memory and reading and transmitting the data of the number of bits corresponding to the 125 μS cycle, there is an effect that the memory amount can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a time division multiplex voice transmission device of the present invention.

FIG. 2 is a diagram showing an example of a data configuration corresponding to addresses of registers in FIG.

FIG. 3 is a diagram showing an example of a data configuration on a memory in FIG.

FIG. 4 is a block diagram showing a second embodiment of the time division multiplex voice transmission device of the present invention.

[Explanation of symbols]

1, 101 control device (CTL) 2, 102 time slot counter (CNT) 3, 103, 104 register data selector (RD)
S) 4,105 Register address selector (RAS) 5,111 Memory (MEM) 6,112 Memory address selector (MAS) 7,110 Register (REG) 8,117 Parallel / serial converter (P / S) 9,11 , 114, 116 Adder (ADD) 10, 115 Comparator (CMP) 106, 107 Hardware queue (QUE) 108 Hardware queue output selector (QSL) 109 Output ready signal selector (RDY) 113 Register write control circuit (WRC) )

Claims (3)

[Claims] 1. A control device for instructing data editing and transmission, and a memory for storing voice signal data to be transmitted.
A writing means for writing the voice signal data in this memory in accordance with an instruction from the control device and a time slot position for time-division multiplexing and transmitting the voice signal 125 μ
A time slot counter of S period, a register holding transmission control information for each time slot, a transmission flag in the register based on an instruction from the control device, and a start address of the audio signal data on the memory. Set the number of bytes to be sent and set the number of bytes to be sent to "0"
Setting means, first reading means for reading information from the register for each time slot in synchronization with the output of the time slot counter, the start address and the sending byte in the information read from the register An adder for adding the numbers to calculate the address of the transmission data on the memory, a second reading means for reading the audio signal data from the memory using the output of the adder as an address, and the read data in a time division manner. Only when the sending means for sending to the communication path and the sending flag of the information read from the register are "1", the sending byte number and the sending byte number are compared, and a match signal is issued when they match. If there is a match between the output comparator and the output signal of this comparator, the sending flag is set to "0". Division multiplexing the audio delivery device when anda resetting means for setting to 1 the addition to the register again sending byte number. 2. A hardware queue corresponding to each transmission time slot is provided, transmission information is written from the control device to the hardware queue, and the transmission flag of data read from the register is “0”. In this case, the hardware queue corresponding to each time slot is checked, and if data is present in the hardware queue, it is read out and set in the register. apparatus. 3. The time-division multiplex audio transmitter according to claim 1, wherein the adaptive differential PCM signal data is stored in the memory, and data having a bit number corresponding to a 125 μS cycle is read out and transmitted.