JPS6412398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic sound generation circuit used in electronic musical instruments and the like.

This type of electronic sound generation circuit decomposes sound into pitch and timbre elements, and uses digital circuits to generate sound source data related to the sound source waveform representing the pitch and envelope waveform data related to the envelope waveform representing the timbre. The generated data are D/A converted and synthesized to generate an electronic sound signal. According to this type of digital processing, data for various types of electronic sounds can be generated in the same circuit through time-sharing processing, making it suitable for integrated circuits and having the advantage of eliminating the need for circuit adjustments. be.

By the way, in order to generate each of the above-mentioned data in a digital circuit, taking sound source waveform data as an example, one period of the sound source waveform is divided into N parts, and the amplitude value of the waveform in each time division interval is stored in a storage circuit. It is sufficient to store the information and sequentially read it out using a clock that is N times the frequency of the sound source waveform. In addition, when generating multiple sound source signals with the same sound source waveform but different frequencies, clocks with different frequencies are required as many as the number of sound source signals. Since doing so would greatly increase the number of circuit elements used, it is impractical and an accumulator is generally used.

Figure 1 shows a conventional electronic sound generation circuit.
1 is a sound source waveform block, and 2 is an envelope waveform block. In the sound source waveform block 1, reference numeral 3 stores sound source waveform coefficient data related to analog sound signals of multiple channels, and a sound source waveform coefficient ROM (read-only) from which stored data at a designated address is read out by an address signal.
4 is an adder circuit in which the output of this ROM 3 becomes one addition input; 5 is an adder circuit in which the output of this adder circuit 4 becomes a data input; the readout output of the stored data becomes the other addition input of the adder circuit 4; This is a RAM (random access memory) in which data is read from and written to a designated address using signals. The above adding circuit 4
The RAM 5 and RAM 5 form an accumulator 6 that performs accumulation by the addition cycle of the adder circuit 4. 7 is addressed by the output of the adder circuit 4,
A sound source waveform data ROM 8 from which pre-stored sound source waveform data (binary data) is read is a D/A conversion circuit that converts the read data of the ROM 7 into analog and outputs a sound source analog signal.
On the other hand, the envelope waveform block 2 has almost the same structure as the sound source waveform block 1, with reference numeral 9 an envelope waveform coefficient ROM, 10 an adder circuit, 11 a RAM, 12 an accumulator, and 13 an envelope waveform data ROM. , 14 is a D/A conversion circuit.

In the sound source waveform block 1, the coefficient ROM is
Coefficient data is read from 3, and the data and the previous addition output data of the same channel (read from RAM 5) are added in adder circuit 4, and this added data is stored at the original address of RAM 5 again. Therefore, the time change in the binary value of the addition data is proportional to the value of the coefficient data read from the coefficient ROM 3. Therefore, the readout output from the data ROM 7 addressed by the addition data becomes sound source waveform data in which the speed of time change in the amplitude value of the sound source, that is, the sound source frequency changes depending on the magnitude of the coefficient data. This data is then converted into a sound source analog signal by the D/A conversion circuit 8.

Note that the address signal given to RAM5 is
The accumulation operation of the accumulator 6 described above is performed in a time-division manner for the number of desired sound source signals, and the change is made so that a certain address range of the RAM 5 is repeatedly scanned at a certain period so that this operation is repeated. do. In addition, in response to this time-division operation, the address signal of the coefficient ROM 3 is also changed so as to designate an address for reading out the coefficient data necessary to generate a desired sound source frequency in each time-division section. Similarly, in the envelope waveform block 2, an operation similar to that of the sound source waveform block 1 is performed. In this case, since the sound source analog signal from the sound source waveform block 1 is guided as the reference voltage of the D/A conversion circuit 14, this sound source analog signal is amplitude-modulated by the envelope waveform data (binary data), and is time-divisionally modulated. A desired multiplexed analog instrument sound signal can now be obtained.

However, the configuration shown in FIG.
1 is used, and each requires an address signal line, which has the disadvantage of high cost.

The present invention has been made to eliminate the above-mentioned drawbacks by sharing the accumulators for sound source waveform generation and envelope waveform generation, and replacing the storage section of the accumulator with a group of shift registers. Therefore, it is an object of the present invention to provide an electronic sound generation circuit which can reduce the number of circuit elements used, eliminate the need for an accumulator and an address input signal line for a storage section, and reduce costs.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings, with reference to the case where it is applied to, for example, an electronic musical instrument.

In FIG. 2, 21 is a first storage circuit, for example, a coefficient ROM, which stores sound source waveform coefficient data related to analog sound signals of multiple channels, and from which data at a designated address by an address signal is read; A second storage circuit, for example, a coefficient ROM 23, stores envelope waveform coefficient data related to each analog sound signal of the channel, and from which data at an address designated by an address signal is read out, such as a coefficient ROM 23, which is the ROM 21,
22 is a multiplexer for deriving each read data during the period of multiplex signals T ₁ and T ₂ generated by time division; 24 is an adder circuit to which the output of this multiplexer 23 is led as one addition input; 25 is this adder circuit; A shift register group consisting of a plurality of serial shift registers each having a predetermined number of bits, to which the output (parallel bits) of the adder circuit 24 is guided, and each of the parallel bits is delayed by a predetermined time and becomes the other addition input of the adder circuit 24;
This adder circuit 24 and shift register group 25 form an accumulator 26 that performs an accumulation operation in an addition cycle. In this case, the addresses of the address signals of the ROMs 21 and 22 are changed by the same number as the desired number of sound source signals (number of channels), and this cycle of address changes is repeated. Then, within each of the addressing periods, that is, one channel period, the multiplex signal is
T ₁ and T ₂ are generated, and the adder circuit 24 adds the current sound source waveform coefficient data input and the previous addition output data (sound source waveform coefficient accumulated data) of the same channel, and adds the current sound source waveform coefficient data input and the current envelope waveform. Previous addition output data of the same channel as coefficient data input (envelope waveform coefficient accumulation data)
Each serial shift register of the shift register group 26 has the number of bits twice the number of channels N so that the addition with N is performed in a time-division manner. On the other hand, 27 is a demultiplexer that separates and derives the output of the accumulator 26 into sound source waveform accumulated data and envelope waveform accumulated data using demultiplexed signals T ₁ ′ and T ₂ ′, and 28 separates and derives the sound source waveform data. a third storage circuit, such as a ROM, 29, which stores the sound source waveform accumulated data and whose address is specified by the sound source waveform accumulated data;
30 is a fourth storage circuit that stores envelope waveform data and whose address is specified by the accumulated envelope waveform data, such as a ROM; 30 stores sound source waveforms for each time-division channel based on the output data of these ROMs 28 and 29; This is a D/A conversion circuit that generates an electronic sound, such as a musical instrument sound analog signal, whose signal is amplitude-modulated by an envelope waveform signal.

In the above configuration, the sound source waveform coefficient data and the envelope waveform coefficient data are sequentially read out for each channel from the first ROM 21 and the second ROM 22 by the address signal, and this read data is read out for each channel by the multiplexer 23. The signal is input to the adding circuit 4 in a time-division manner, and the accumulator 26 accumulates the sound source waveform coefficient data and the envelope waveform coefficient data for each channel. The addition output data of the accumulator 26 is divided into sound source waveform and envelope waveform systems by a demultiplexer 27, and each of the divided data is used as a third
The ROM 28 and the fourth ROM 29 are addressed, and the sound source waveform data and envelope waveform data read from each are led to the D/A conversion circuit 30 and converted into an analog musical instrument signal.

The electronic sound generation circuit described above has a multiplexer 23 and a demultiplexer 27 added compared to the conventional circuit, but only one accumulator 26.
Since the multiplexer 23 and the demultiplexer 27 can be easily configured mainly by a group of gates, the number of circuit elements used as a whole can be reduced compared to the conventional circuit. Also, the accumulator 2
6 uses a shift register group 25 and an adder circuit 24 without using a RAM, so compared to the conventional example, a RAM address signal line can be eliminated. Therefore, the cost of the circuit shown in FIG. 2 can be reduced compared to the conventional circuit.

Note that if dynamic type ROMs are used as the ROMs 28 and 29, they are more advantageous than static types in terms of the number of elements and the circuit area on the integrated circuit, and furthermore, dynamic type ROMs require an output latch circuit; Since the latch circuit allows demultiplexing, the demultiplexer 27 of FIG. 2 is not required.

Next, another embodiment of the present invention will be described. In Fig. 3, the same parts as in Fig. 2 are given the same reference numerals, and the difference from Fig. 2 is that the accumulator output data is a mixture of sound source waveform accumulation data and envelope waveform accumulation data. By directly using the address signal of the sound source/envelope waveform data ROM 31, the address signal line for all or part of this ROM 31 becomes common, and as a result, the circuit shown in FIG. 3 becomes the same as that shown in FIG. 2. The number of wires is reduced compared to other circuits, making the circuit simpler. Here, the ROM 31 stores sound source waveform data and envelope waveform data, and each data is read out in a separate system.For example, the ROM 31 is configured as shown in FIG. 4a and as shown in FIG. 4b. It operates at the appropriate timing. In Fig. 4, I is an inverter group, T _P is a P channel MOS transistor group for memory cells, T _N
40 is a latch circuit group that latches the sound source data using the sound source waveform data latch clock _φ2 , _and 41 latches the envelope data using the envelope waveform data latch clock _φ3 . This is a group of latch circuits.

By the way, in the circuits shown in FIGS. 2 and 3, since the adder circuit 24 operates sequentially due to the carry from the lower order, the operation speed is very slow compared to other circuits when the number of bits becomes large. Also, ROM2
8, 29, and 31 also have a slow operation speed when the number of gate stages is large. Therefore, the output of the adder circuit 24 is
The use of address signals 28, 29, and 31 is not sufficient in terms of operating speed, and for this reason, when the circuits in FIGS. 2 and 3 are integrated, the yield is insufficient, and the cost reduction is become a hindrance. To avoid this, if the output data of the shift register group 25 is used as the address input of the ROM 31 as shown in FIG. 5, the time delay of the output of the adder circuit 24 will be reduced.
There is no effect on the operation of ROM31, and ROM3
1, the operating speed margin increases. In addition, the same parts in FIG. 5 as in FIG. 3 are given the same reference numerals. Also in FIG. 2, shift register group 2
It goes without saying that if the output data of No. 5 is input to the ROMs 28 and 29 via the demultiplexer 27 instead of the output of the adder circuit 24, the operating margin will increase as described above.

The circuit in Figure 6 uses the two coefficients of the circuit in Figure 2.
The ROMs 21 and 22 are combined into one coefficient ROM 60 in which sound source/envelope waveform coefficient data is stored, and a switching signal for switching and controlling the selective reading of sound source waveform coefficient data or envelope waveform coefficient data is added to the ROM address input, and the sound source By multiplexing the waveform coefficient data output and the envelope waveform coefficient data output using a wired OR, the multiplexer (Fig. 2
3) is omitted to simplify and downsize the circuit. For example, as shown in FIG. 7, the coefficient ROM 60 includes an inverter I, a group of memory cell MOS transistors T _A for sound source waveform coefficient data, a group of memory cell MOS transistors T _B for envelope waveform coefficient data, and a clock φ ₁ for reading data. It consists of a group of MOS transistors T _N , a group of latch circuits 70 for latching read data, and the like.

The circuit in FIG. 8 includes each ROM 21 and 2 in FIG.
2, 28, and 29 are replaced with RAMs 81, 82, 83, and 84 for storing corresponding data, respectively, and each data can be exchanged through a write data bus line 85 by an external input switch (not shown) or the like. This makes it possible to generate a variety of electronic sounds.

Furthermore, the present invention can also combine parts of the variations shown in FIGS.
As long as the shift register group 25 is used in the storage section of the accumulator, it is possible to reduce the number of circuit elements used and eliminate the need for an address input signal line for the storage section of the accumulator.
It is possible to reduce costs.

As described above, the present invention reduces the number of circuit elements used and address input signal lines of the accumulator storage section when multiple channels of analog sound signals are generated based on digital signals by time division in a predetermined unit time. It is possible to provide an electronic sound generation circuit that can eliminate the need for and reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional electronic sound generating circuit, FIG. 2 is a block diagram showing one embodiment of the electronic sound generating circuit according to the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. Figure 4a is a circuit diagram showing a specific example of the data ROM in Figure 3, Figure 4b is a timing diagram shown to explain the operation of Figure 4a, and Figures 5 and 6 are respectively FIG. 7 is a block diagram showing another embodiment of the present invention. FIG. 7 is a circuit diagram showing a specific example of the coefficient ROM in FIG. 6. FIG. 8 is a circuit diagram showing another embodiment of the invention. 21...first coefficient ROM (first storage circuit),
22...Second coefficient ROM (second storage circuit), 2
3... Multiplexer, 24... Addition circuit, 25
...Shift register group, 26...Accumulator, 27...
... Demultiplexer, 28 ... Third ROM (third storage circuit), 29 ... Fourth ROM (fourth storage circuit), 30 ... D/A conversion circuit.

Claims (1)

[Claims] 1. In an electronic sound generation circuit that generates analog sound signals of multiple channels by time-division of a predetermined unit time based on pre-stored data regarding sound source waveforms and data regarding envelope waveforms, A first storage circuit that stores sound source waveform coefficient data related to the sound source waveform and sequentially reads the sound source waveform coefficient data of each channel by inputting an address signal, and also stores envelope waveform coefficient data related to the envelope waveform of each channel. a second memory circuit from which envelope waveform coefficient data of each channel is sequentially read out by inputting an address signal; means for time-division multiplexing each read data of the first and second memory circuits for each channel; The output of the means serves as one addition input to an addition circuit that performs an addition operation in a predetermined addition cycle, and the output of this addition circuit is guided to output previous addition output data of the same channel and type as the current one addition input data. The accumulation circuit comprises a shift register group which is used as the other input of the addition circuit, and the accumulation of both the sound source waveform coefficient data and the envelope waveform coefficient data is performed through a common accumulation path of the addition circuit and the shift register group. a third storage circuit from which the stored sound source waveform data addressed by the accumulated data of the sound source waveform coefficient data among the accumulated output data of the accumulator is read; and the accumulated data of the envelope waveform coefficient data. a fourth storage circuit from which the envelope waveform data addressed and stored is read out; and analog conversion is performed based on the read data for each same channel of these third and fourth storage circuits to generate analog sound signals of multiple channels. 1. An electronic sound generation circuit comprising: a D/A conversion circuit that outputs the following in a time-division manner. 2. The third storage circuit and the fourth storage circuit are combined into one ROM, and addressing is performed by the accumulated output data of the accumulator, and this
2. The electronic sound generating circuit according to claim 1, wherein the sound source waveform data output and the envelope waveform data output of the ROM are derived through separate systems. 3. The electronic sound generation circuit according to claim 1, wherein the output of a shift register group is used as the accumulated output data of the accumulator. 4 The first storage circuit and the second storage circuit are integrated into one ROM, and a switching signal for selectively switching between reading sound source waveform coefficient data and reading envelope waveform coefficient data is transmitted to the ROM.
2. The electronic sound generating circuit according to claim 1, wherein in addition to the address signal, readout outputs of both coefficient data are multiplexed by wired-OR connection. 5 Part or all of each of the above storage circuits may be configured as a RAM.
2. The electronic sound generating circuit according to claim 1, wherein the electronic sound generating circuit is configured such that the data can be replaced.