JPH04205000A - Waveform generator - Google Patents

Abstract

PURPOSE:To make reproduction up to a high tone range without increasing the total capacity of a waveform memory by dividing the waveform memory to two groups ; even and odd addresses, according to the lowermost bit of the addresses. CONSTITUTION:An address generating section 100 generates the address ADR for reading out the waveform memory according to the timber and pitch of musical tones. The integer part of the ADR is divided to the even and odd groups according to the lower bit thereof. These groups are respectively outputted as waveform data WA, WB in a waveform computing section 10 via the waveform memories 11, 12. On the other hand, the decimal part of the ADR is outputted as an interpolation coefft. H. These outputs are subjected to processing of (WB-WA)H+WA by computing elements 113 to 115. A DFF 116 latches these values and outputs the values as waveform memory data W. The access for twice of the waveform memories is simultaneously executed at one time in this way and, therefore, the time for computation per tone is reduced by half and the sampling frequencies are eventually increased. The reproduction up to the high tone range is thus possible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a waveform generator that generates waveform data at a constant cycle regardless of the pitch of a musical tone.

2. Description of the Related Art In recent years, so-called PCM (Pulse C) technology has been developed, which generates musical tones by storing data obtained by analog/digital conversion of musical tones in a waveform memory and reading out this data.
Musical tones are now being generated using the ode modulation method. The PCM method is roughly divided into two types: a method that depends on the period in which waveform data is generated or the pitch of a musical tone, and a method that does not. Recently, the latter method has become mainstream because it is easy to perform time-division calculations and it is possible to mix musical tone signals as they are digital signals.

A method that does not depend on the period in which waveform data is generated or the pitch of a musical tone is shown in, for example, Japanese Patent Application Laid-Open No. 2-108099 and Japanese Patent Application Laid-Open No. 51-9348.

A conventional waveform generator that generates waveform data at a constant cycle regardless of the pitch of a musical tone will be described below.

FIG. 5 is a block diagram of a first conventional waveform generator. In FIG. 5, 300 is an address generation section, 301.
308 is an adder, 307 is a subtracter, 302.303°3
04, 305.310 is a D flip-flop (hereinafter DF
Abbreviated as F. ), 309 is a multiplier, 30 is a waveform calculation unit, 3
1 is a waveform memory, and 32 is an address supply section.

The operation of the first conventional waveform generator configured as described above will be described below with reference to the operation timing diagram of FIG. 6.

First, the address generating section 300 generates an address for reading out the waveform memory 31 according to the timbre and pitch of the musical tone. The address is calculated by cumulatively adding up the atsis increment corresponding to the pitch of the musical tone. The address increase is
It doubles every time the pitch increases by one octave, and is made up of exactly one integer part and one decimal part. Therefore, the address also consists of an integer part and a decimal part. If the integer part of the address is output to the waveform memory 31 and the waveform data is read, and the waveform data corresponding to only the integer part of the seven addresses is output as is, noise called so-called "sick" will occur.

In order to alleviate this problem, waveform data corresponding to an address including not only the integer part but also the decimal part may be calculated by interpolating the values of a plurality of waveform data. The simplest method for interpolation is to draw a straight line (i.e. 1
This is a method of interpolating (with the following function). WA the two adjacent waveform data.

When WB and the interpolation coefficient (that is, the address decimal part) are H, the waveform data W corresponding to the address including the decimal part is (
1) It is expressed as follows.

W=(WB-WA)・H0W A (11 Of the addresses ADR generated from the address generation section 300, the integer part ADRU is input to the adder 301, and the decimal part ADRL
is latched in DFF 303.

The timing signal t which is the other input of the adder 301
33 is 0 at first, so A'DRU or D F as it is.
F 302 is latched, and the address A of the waveform memory 31 is
Output as DI. The waveform data DTI corresponding to the address value ADRU is output from the waveform memory 31, and the waveform data DTI corresponding to the address value ADRU is output.
It is latched into F F 304 and output as waveform data WA.

Next, the timing signal t33 becomes 1, and (ADRU+
1) is latched into DFF 302. Waveform data DTI corresponding to the address value (ADRU+1) is output from the waveform memory 31, latched by the DFF 305, and output as waveform data WB.

The subtracter 307 receives two waveform data WA and WB and outputs the value (WB-WA). The multiplier 309 is
(WB-WA), which is the output of the subtracter 307, and D F
The interpolation coefficient H (interpolation coefficient H is equal to the address decimal part ADRL) which is the output of F303 is input, and (WB-
WA) Outputs the value of H.

Adder 308 outputs W A which is the output of D F F 304
and -(WB-WA).H, which is the output of the multiplier 309, are input, and the value of (WB-WA).H+WA is output.

The DFF 310 latches this value and outputs it as waveform data W.

In this way, the address A'D R with an integer part and a decimal part
Waveform data W corresponding to is calculated.

These calculations are performed in a time-sharing manner as shown in Figure 6.
It is possible to generate multiple musical tones. In Figure 6,
(11 represents the data of the nth musical tone among multiple musical tones. Also, the access time of the waveform memory (the time from giving an address to confirming the data) is the same as the ROM (read It is set to 300 [n seconds], which is the access time of 250 [n seconds], which is the access time for the private memory), and an operation margin of 50 [n seconds].

FIG. 7 is a schematic diagram of a second conventional waveform generator. In FIG. 7, 400 is an address generation section, 401
．． 410 is an adder, 409 is a subtracter, 402.403,
404.405.406.407.412 is DFF, 4
11 is a multiplier, 40 is a waveform calculation section, 41 and 42 are the same waveform memories, and 43 is an address supply section.

The operation of the second conventional waveform generator configured as described above will be described below with reference to the operation timing diagram of FIG. 8.

Address generation section 400 generates an address consisting of an integer part and a decimal part, as in the first conventional example. Of address ADR, integer part ADRU is D F F 402
is input to the adder 401, and the decimal part ADRL is D F
F 404 is entered. The DFF 402 latches the address integer part ADRU and outputs it to the waveform memory 41 as an address ADI. The adder 401 adds 1 to the address integer part ADRU, and D F F 40
Output to 3. D F F 403 is CADRU+1
) is latched, and the address AD2 to the waveform memory 42 is latched.
Output as .

From the waveform memory 41, the waveform data DTI corresponding to the address value ADRU is outputted as 0, latched by the DFF 406, and pressed as the waveform data WA.

Further, from the waveform memory 42, the address value (ADRU+1
) is output as waveform data DT2 corresponding to D F F
407 and output as one skin shape data wB.

The subtracter 409 receives two waveform data WA and WB and outputs the value (WB-WA). Multiplier 411 is the output of subtracter 409 (WB-WA) and D F
The interpolation coefficient H which is the output of F 405 is input, and (W
Outputs the value of B-WA)・H. Adder 410 is D
WA, which is the output of F F 406, and (WB-WA), H, which is the output of multiplier 411, are input, and (WB-WA
)・Output the value of H×WA.

The DFF 412 latches this value and outputs it as waveform data W.

In this way, the waveform data W corresponding to the address ΔDR having an integer part and a decimal part is calculated.

These calculations are performed in time division as shown in Figure 8.
Can generate multiple musical tones. Since the waveform memory is accessed twice at the same time, the calculation time per note is halved compared to the first conventional example.

Problem to be Solved by the Invention However, in the configuration of the first conventional example, the waveform memory access time is waveform memory access count) is Y.

If the maximum number of sounds by time-division calculation is Z, the sampling frequency Fs is expressed by the formula Fs=]/(X-Y-Z) (2),
When X = 300 [n seconds], Y = 2, Z = 64 sounds, Fs = 26 [kHz1, reproduction band is approximately 12 [kHz]
zl, which is the human audible range of 20 [kHzl].
It had the disadvantage that it could not be played back. 20 [kHz
In order to be able to reproduce up to 1, the sampling frequency must be increased, or in order to do so, the maximum number of sounds Z must be decreased, since the values of X and Y are generally fixed. However, reducing the maximum number of sounds Z reduces the performance of the electronic musical instrument.

On the other hand, in the configuration of the second conventional example, the two waveform memories are accessed simultaneously and separately, so the number of accesses to the waveform memory is equivalent to Y=1. Therefore, waveform memory access time X = 300 [n seconds], maximum number of pronunciations Z-
Even in the case of 64, Fs=52 [kHzl], and it is possible to reproduce up to the high frequency range.

However, the total capacity of the waveform memory doubles, resulting in an increase in cost.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a waveform generator capable of reproducing up to a high frequency range without increasing the total capacity of a waveform memory.

Means for Solving the Problems To achieve this object, the waveform generator of the present invention includes an address generator that outputs an address consisting of an integer part and a decimal part, and a waveform generator that generates a plurality of address generators based on the integer part of the address. an address supply unit that outputs a waveform memory address; and inputs the waveform memory addresses that are divided into a plurality of groups according to the lower hit of the integer part of the address and output from the address supply unit, and outputs each waveform memory address. a plurality of groups of waveform memories that output waveform data corresponding to the address; and a waveform calculation unit that calculates waveform data corresponding to the address based on the waveform data output from the plurality of waveform memories and a decimal part of the address. It is composed of and.

Effect: With this configuration, the address supply unit supplies separate waveform memory addresses to multiple groups of waveform memories based on the integer part of the address generated from the address generation unit, and multiple waveform memory addresses corresponding to the multiple waveform memory addresses are The waveform data are simultaneously read out, and the waveform calculation unit calculates waveform data corresponding to an address including an integer part and a decimal part based on the plurality of waveform data and the decimal part of the address.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a waveform generator according to a first embodiment of the present invention. In FIG. 1, 100 is an attribution generator, +01.103.114 is an adder, 102,
109 is inverter, 104.105.106.107
．． Il1, II2.1+6 is D F F , 10
8.110 is a selector, 113 is a subtracter, and 115 is a multiplier. Further, 10 is a waveform calculation unit, 11 is a waveform memory that stores only waveform data corresponding to even addresses, and 12
1 is a waveform memory that stores only waveform data corresponding to odd addresses, and 13 is an address supply section.

The waveform memories 11 and 12 store only waveform data corresponding to even and odd addresses, respectively. Therefore, compared to the waveform memory 31 in the conventional example shown in FIG. 5, the memory capacity is halved. In other words, the waveform memory 11
The sum of the memory capacities of the waveform memory 12 and the waveform memory 12 is equal to the memory capacity of the conventional waveform memory 31.

The operation of the waveform generator configured as described above will be explained below according to the operation timing chart shown in FIG.

First, the address generating section 100 generates an address ADR for reading out the waveform memory in accordance with the timbre and pitch of a musical tone. Address ADR is integer part ADRU and decimal part ADR
Consists of L.

Next, the address integer part ADRU is processed by adders 101 and 103.
is input. When the address integer part ADRU is an even number, the timing signal tll is 1, the output of the inverter 102 is 0, the adder 101 calculates (ADRU+O), and the adder 103 calculates (ADRU+1). When the address integer part ADRU is an odd number, the timing signal tll is 0, the output of the inverter 102 is 1,
The adder 101 calculates (ADRU+1), and the adder 103 calculates (ADRU+0).

Further, the address decimal part ADRL is the timing signal tl
O is latched to D F F 106.107 and output as an interpolation coefficient H.

Next, the output of adders 101.103 is the least significant bit (
At timing t10, all signals except for the LSB (hereinafter abbreviated as LSB) are latched by the DFF 104 and 105, and the addresses are supplied to the waveform memory 11 and 12. LSB
This is because the waveform memory is already divided into even addresses and odd addresses, so the LSB after addition is unnecessary.

Next, the waveform memory 11. 12 are waveform data DTI of even addresses and waveform data DT2 of odd addresses, respectively.
Output.

When the address integer part ADRU is an even number, the timing signal t12 is 1, the output of the inverter 109 is 0, the selector 108 selects the DTI of input A, and the selector 11
0 selects DT2 of input B. Address integer part ADR
When U is an odd number, the timing signal t12 is O, the output of the inverter 109 is 1, and the selector 108 is input B.
DT2 of input A is selected, and selector 110 selects DTL of input A.

The output of the selector 108 is latched in the DFF 111, and when the address integer part ADRU is an even number, the DTI is
When the number is odd, DT2 is output as waveform data WA. Also, the output of selector lI'0 is D F
The address integer part ADRU is latched in F112, and when the address integer part ADRU is an even number, it is DT2, and when it is an odd number, it is DTI, and each is output as waveform data WB.

The subtracter 113 receives two waveform data WA and WB and outputs the value (WB-WA). Multiplier 115 outputs (WB-WA), which is the output of subtracter 113, and D F
The interpolation coefficient H (interpolation coefficient H is equal to the address decimal part ADRL) which is the output of F107 is input, and (WB-
WA) ・Outputs the H value.

Adder 114 outputs WA, which is the output of DFFIII.
and (WB-WA).H which is the output of the multiplier 115 are input, and the value of (WB-WA)-H+WA is output. D
F F +16 latches this value and stores the waveform data W
Output as .

In this way, waveform data W corresponding to address ADR having an integer part and a decimal part is calculated.

These calculations are performed in time division as shown in Figure 2.
Can generate multiple musical tones. In Figure 2,
(n) represents the data of the nth musical tone among the plurality of musical tones, and in the nth address integer part ADRU is an even number, (n
+ll)-th shows the operation timing when the number is odd.

Since the waveform memory is accessed twice at the same time, the calculation time per note is halved compared to the first conventional example in Figure 6, and as a result, the sampling link frequency is increased. This makes it possible to reproduce musical sounds up to the high range.

Further, unlike the second conventional example shown in FIG. 7, the total capacity of the waveform memory (total memory capacity of the waveform memory) does not increase at the cost of shortening the computation time.

As described above, according to this embodiment, the waveform memory is divided into two groups of even addresses and odd addresses according to the lowest address address, and separate addresses are supplied to each group, and the integer part and Since the waveform data corresponding to the address including the decimal part is calculated, it is possible to reproduce up to the high frequency range without increasing the total capacity of the waveform memory.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a waveform generator according to a second embodiment of the present invention. In FIG. 3, 200 is an address generator, 20'1.211 is an adder, 205 is an inverter, 202.203.204.206.207.20
8.213 is a DFF, 210 is a subtracter, 2+2 is a multiplier, and 20 is a waveform calculation unit. A waveform memory 21 has an output control terminal ○E and stores only waveform data corresponding to even addresses.

A waveform memory 22 similar to the waveform memory 21 stores only waveform data corresponding to odd addresses.

OE is its output control terminal. 23 is an address supply section.

The operation of the waveform generator configured as described above will be described below with reference to the operation timing diagram of FIG. 4.

First, the address generating section 200 generates an address ADR for reading out the waveform memory according to the timbre and pitch of the musical tone. Address ADR is integer part ADRU and decimal part ADR
Consists of L.

Next, the address integer part ADRU is input to the adder 201. When the address integer part ADRU is an even number, the timing signal t22 becomes 0 in the first half period and l in the second half period, and the value of (ADRU + 0) is in DFF202. , the value of (ADRU+1) is latched in the DFF 203.

When the address integer part ADRU is an odd number, the timing signal t22 is 1 in the first half period, and the second half is 1/2.
becomes 0 in the period of , and D F F 202 has (A
DRU+1), D F F 203i, m is (
The f value of ADRU 10) is latched. However, the LSB is removed before latching. The reason for excluding the LSB is that the waveform memory is already divided into even addresses and odd addresses, so the LSB after addition is unnecessary.

Further, the address decimal part ADRL is the timing signal t21.
is latched to D F F 204.2'06 and output as interpolation coefficient H.

The outputs of the waveform memory 21 and the waveform memory 22 are connected by the same data bus, and when the timing signal t3 is 0, the waveform memory 21 is in a state where data can be output, and the waveform memory 22 is in a state where it cannot output data (that is, a high impedance state). )become. Conversely, when the timing signal is t3 or l, the waveform memory 21 is in a state where it cannot output, and the waveform memory 22 is in a state where it can be output. The access time of the waveform memory is usually about 250 [ns] in the case of ROM used in electronic musical instruments, or the time it takes to determine whether it is output data when the output side terminals OE are changed from 0 to 1 (this is The OE access time (referred to as the OE access time) is about loO [n seconds], which is shorter than the access time, so even if the last 150 [n seconds] of the 300 [n seconds] for accessing the waveform memory are set to be outputtable. , you can get waveform data.

Therefore, as shown in FIG. 4, if the two waveform memories are accessed alternately with a shift of tso [n seconds], the waveform data DTI in the waveform memory 21 and the waveform data DT2 in the waveform memory 22 are alternately accessed on the data bus. appear.

When the address integer part ADRU is an even number, the DFF 207 latches the waveform data DTI of the even address in response to the timing signal t23, and the DFF 208 latches the waveform data DT2 in the odd address in response to the timing signal t24. If the address integer part ADRU is an odd number, D
F F 207 latches waveform data DT2 at an odd address, and D F F 208 latches waveform data DTI at an even address. In other words, the address value or the smaller waveform data is latched into the DFF 207 and output as waveform data WA, and the address value or the larger waveform data is latched into the DFF 208 and output as the waveform data WB. .

The subtracter 210 receives two waveform data WΔ and WB and outputs the value (WB-WA). Multiplier 2+2 is
(WB-WA), which is the output of the subtracter 210, and DFF
The interpolation coefficient H which is the output of 206 is input, and (WB
-WA)・H value is output. The adder 211 is D F
WA, which is the output of F 207, and (WB-WA), H, which is the output of the multiplier 212, are input, and (WB-WA)
・The value of H+WA is input. DFF 213 is
This value is latched and output as waveform data W.

In this way, the waveform data W corresponding to the address ADR having an integer part and a decimal part is calculated.

These calculations are performed in time division as shown in Figure 4.
Can generate multiple musical tones. In Figure 4,
(nl represents the data of the nth musical tone among multiple musical tones. In this figure, the address integer part ADRU is an even number at the n, (n+1), and (n+3)th, and is an odd number at the (n+2)th. The figure shows the operation timing for the case.

Here, the waveform memory is accessed twice at the same time, so the calculation time per note is halved compared to the first conventional example shown in Figure 6.
The sampling frequency becomes higher, making it possible to reproduce musical sounds up to the high range. Further, the total capacity of the waveform memory does not increase compared to the first conventional example shown in FIG. Furthermore, the data bus of the waveform memories is shared by shifting the accesses of the waveform memories by 1/2 and using the pressure control function of the waveform memories.

As described above, in this embodiment, the waveform memory is divided into even addresses and odd addresses according to the least significant bit of the address.
Split into two groups and supply each with a different address,
Calculate waveform data corresponding to an address including an integer part and a decimal part. Therefore, it is possible to reproduce up to the high frequency range without increasing the total capacity of the waveform memory. moreover,
By shifting the accesses of the waveform memories by 1/2, it is possible to share the data bus for the two waveform memories, which makes it possible to reduce the number of terminals when implementing LSI, thereby reducing costs. Become.

Note that in the first embodiment and the second embodiment, the waveform memory is stored in the least significant bit (LSB) of the address integer part.
It was divided into two groups (that is, a group of even addresses and a group of odd addresses) according to the 2 bits on the LSB side (LSB
and the bit one bit higher than the LSB), or may be divided into eight depending on the three bits on the LSB side.

However, the interpolation calculation of the waveform data in this case needs to be an interpolation calculation using a third-order or higher-order function, and a seventh-order or higher-order function, respectively. In other words, when accessing waveform data for 4 and 8 consecutive addresses at the same time (including when shifted as in the second embodiment), the 4-division and 8-division methods are effective. Become.

Furthermore, in the first embodiment and the second embodiment, one group of divided waveform memories may be composed of one waveform memory, or one group may be composed of a plurality of waveform memories. Needless to say.

Effects of the Invention As described above, the present invention includes an address generation unit that outputs an address consisting of an integer part and a decimal part, an address supply unit that outputs a plurality of waveform memory addresses based on the integer part of the address, A waveform memory of multiple groups that is divided into multiple groups according to the lower bits of the integer part of the address, inputs the waveform memory address output from the address supply unit, and outputs waveform data corresponding to each waveform memory address. , the total capacity of the waveform memory is increased by providing a waveform calculation unit that calculates waveform data corresponding to the address based on the waveform data output from the plurality of groups of waveform memories and the decimal part of the address. Therefore, it is possible to realize a waveform generator that can reproduce up to a high frequency range without any noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a waveform generator according to a first embodiment of the present invention, FIG. 2 is an operation timing diagram of the waveform generator of FIG. 1, and FIG. 3 is a block diagram of a waveform generator according to a second embodiment of the present invention. A block diagram of the Nigero waveform generator, FIG. 4 is an operation timing diagram of the waveform generator of FIG. 3, FIG. 5 is a block diagram of the first conventional waveform generator, and FIG. 6 is a diagram of the operation timing of the waveform generator of FIG. FIG. 7 is a block diagram of a second conventional waveform generator, and FIG. 8 is an operation timing diagram of the waveform generator shown in FIG. 100, 200...address generation section, 13.23.address supply section, 11.12.21.22..waveform memory, 10.20.waveform calculation section. Agent Yoshihiro Morimoto Figure 2 Figure 74 Paralysis number I...
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Claims (1)

[Claims] 1. An address generator that outputs an address consisting of an integer part and a decimal part; an address supply unit that outputs a plurality of waveform memory addresses based on the integer part of the address; a plurality of groups of waveform memories that are divided into a plurality of groups according to lower bits of the integer part, input waveform memory addresses output from the address supply section, and output waveform data corresponding to each waveform memory address; A waveform generation device comprising: a waveform calculation section that calculates waveform data corresponding to the address based on the waveform data output from the plurality of groups of waveform memories and a fractional part of the address. 2. The waveform generator according to claim 1, further comprising separate data buses for data output from the plurality of groups of waveform memories. 3. The waveform generator according to claim 1, further comprising a common data bus for time-divisionally transmitting data output from the plurality of waveform memories. 4. The waveform generator according to claim 1, wherein the plurality of groups of waveform memories are waveform memories divided into two groups corresponding to even addresses and odd addresses.