JPH09146549A - Delay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To vary the delay time continuously and optionally and to prevent noise accompanying the generation of a discontinuous point of a musical sound signal from being generated by providing a delay time setting means which sets the delay time according to the operation of a real-time operation element. SOLUTION: When the real-time operation element 10 is operated, its operation state is detected in a 1st cycle by an operation detecting means 16, whose detection result is supplied to a control signal interpolating means 18. The control signal interpolating means 18 performs interpolation in a 2nd cycle which is shorter than the 1st cycle and longer than or equal to a sampling cycle and supplies the result as delay time information to a control means 24. The control means 24 reads out delay data required for delay signal calculation and a delay data interpolating means 22 performs interpolating operation, delays the musical sound signal according to the interpolating operation result, and outputs it. Even when the delay time is varied, side interpolation is performed without generating any discontinuous point of the musical sound signal, noise generation can securely be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay device,
More specifically, the present invention relates to a delay device for delaying a tone signal input to an electronic musical instrument by a predetermined delay time and outputting the signal, and more particularly to a delay device capable of changing the delay time.

[0002]

BACKGROUND OF THE INVENTION Conventionally, in the field of electronic musical instruments, there has been known a delay device for delaying an input tone signal by a predetermined delay time and outputting the signal. Such a delay device is generally designed so that the delay time can be changed.

A delay device capable of changing the delay time as described above is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-325.
A delay device having a configuration disclosed in Japanese Patent Publication No. 95 or Japanese Patent Publication No. 63-32393 is known.

A delay device having a configuration disclosed in Japanese Patent Application Laid-Open No. 63-32595 discloses a delay device for preventing the occurrence of noise due to the occurrence of discontinuous points in a tone signal when the delay time is changed. When the tone signal is changed, the tone signal is muted to prevent the occurrence of noise due to the occurrence of a discontinuity in the tone signal.

However, in order to prevent the occurrence of noise due to the occurrence of discontinuous points in the tone signal, when the tone signal is muted, the delay time is changed by real-time operation of an external operator. However, there is a problem that the tone being produced is lost due to muting, and it is not appropriate to change the delay time by real-time operation.

A delay device having a configuration disclosed in Japanese Patent Publication No. 63-32393 modulates a read address with a modulation signal to change a delay time. Does not have interpolation means. That is, the address supplied to the digital memory 4 is an integer address.
When D 'is a very low frequency (modulation data in which the change in the decimal point region is long and the integer region sometimes changes), the modulation is performed only when the integer portion changes. That is, extremely unnatural modulation occurs. In order to prevent such a situation, it is necessary to previously store only a modulation signal having a waveform that does not apply unnatural modulation, and perform modulation with an arbitrary modulation signal by a real-time operation of an external operator, and There is a problem that changing the delay time based on the delay time is not considered.

That is, in the above-mentioned conventional delay device, there has been a problem that any digital control of the delay time in real time is not considered at all.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide an operator that can be operated in real time and to operate the operator in real time. Even if the delay time can be continuously changed arbitrarily by operating, and the delay time is continuously changed without muting at that time,
An object of the present invention is to provide a delay device that does not generate noise due to the occurrence of discontinuity points of a musical tone signal.

[0009]

In order to achieve the above-mentioned object, according to the present invention, there is provided a real-time operator for controlling an operation in real time, and an input terminal according to an operation of the real-time operator. Delay time setting means for setting a delay time of a tone signal input at a more predetermined sampling period; delay means for delaying the tone signal by the delay time set by the delay time setting means and outputting to the output terminal The delay time setting means detects a first control signal that is an operation state of the real-time operator in a first cycle longer than a predetermined sampling cycle, and performs an interpolation operation on the first control signal. Done, shorter than the first cycle,
And generating a second control signal having a second period longer than or equal to the predetermined sampling period, and supplying the second control signal to the delay unit, wherein the delay unit stores the tone signal input at the predetermined sampling period. A storage means for storing data as readable and writable, and a decimal point address corresponding to the second control signal supplied from the delay time setting means is used as a read address of the storage means, and is interpolated by a plurality of storage data of the storage means. And delay data interpolating means for performing an operation, generating delay data corresponding to the second control signal, and outputting the generated delay data to an output terminal.

Therefore, when the real-time operator is operated, the delay time setting means detects the first control signal in the operating state in the first cycle longer than the predetermined sampling cycle, and further the first control signal. Is interpolated, and a second control signal having a second period shorter than the first period and longer than or equal to the predetermined sampling period is generated and supplied to the delay means. The delay means stores the musical tone signal input at a predetermined sampling period as storage data in a readable / writable manner by the storage means, and the decimal point representation corresponding to the second control signal as a read address of the storage means by the delay data interpolation means. , An interpolation operation is performed using a plurality of stored data by using the address, and delay data corresponding to the second control signal is generated and output to the output terminal.

In this case, the delay data interpolating means may include a decimal point address separated from the write address by an address corresponding to the second control signal supplied from the delay time setting means. Means for performing an interpolation operation on the storage data corresponding to and outputting a plurality of storage data necessary for the interpolation operation, and calculating the storage data corresponding to the address of the decimal point expression using the plurality of storage data It may be one that performs an interpolation operation.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a delay device according to the present invention;

FIG. 1 is a block diagram showing a first embodiment of a delay device according to the present invention. This delay device is implemented, for example, as a part of the configuration of an electronic musical instrument.

The delay device is controlled by a central processing unit (CPU), and includes a real-time operator 10 and a real-time operator 1.
0, a delay time setting means 12 for setting a delay time of a tone signal input at a predetermined sampling cycle from the input terminal IN, and a delay time set by the delay time setting means 12 for the input terminal. Delay means 14 for delaying the tone signal input from IN and outputting it to the output terminal OUT.

The real-time operator 10 is an operator that can be operated in real time, for example, a pedal operator such as an expression pedal used for controlling an electronic musical instrument, or a bender used for controlling pitch bend. And the like, which can be operated in real time.

The delay time setting means 12 includes an operation detecting means 16 for detecting an operation state of the real-time operator 10 at a predetermined cycle longer than the sampling cycle (hereinafter, referred to as a first cycle), and an operation detecting means. 16 detection results (first control signal) are input, and interpolation is performed accordingly.
The control signal interpolating means 18 outputs the result to the delay means 14 as delay time information (second control signal).

The control signal interpolating means 18 performs a predetermined interpolation at a period shorter than the first period and longer than or equal to the sampling period (hereinafter, referred to as a second period), and outputs the result as a delay time. The information is supplied to the delay unit 14 as information.

That is, in the control signal interpolation means 18,
The following processing is performed. The detection value a and the detection value b detected by the operation detection means 16 in the first cycle are interpolated by linear interpolation, and the first cycle is defined as “0” to “n−1” in the second cycle. A description will be given of the case where interpolation is performed in n steps.

First, a change amount d for one step is calculated from d = (ba) (1 / n).

Thereafter, d is accumulated for each step in the second cycle, and the interpolated value D _n is output to the delay means 14.

That is, the operation of D _n = a + (d × n) is executed. In detail for each step, 0 step D ₀ = a + 0 = a 1 step D ₁ = a + d 2 step D ₂ = a + 2d 3 step D ₃ = a + 3d (n-1) step D _n-1 = a + (N-1) d.

Further, the delay means 14 stores the tone signal input from the input terminal IN in a readable and writable manner, and calculates the storage data stored in the storage means 20 of the decimal point address to calculate the delay data. And a control means 24 for controlling the storage means 20 and the delay data interpolation means 22.

Here, the control means 24 inputs a control signal having a value corresponding to the delay time indicated by the delay time information input from the control signal interpolation means 18 to the storage means 20, thereby changing the write address to the delay time. Control is performed to read from the storage means 20 a plurality of pieces of storage data necessary for interpolation of storage data of addresses represented by decimal points separated by the corresponding addresses.

Further, the control means 24 supplies the address of the decimal point representation read from the storage means 20 to the delay data interpolation means 22 and controls the interpolation calculation in the delay data interpolation means 22.

In the delay data interpolation means 22, the following processing is performed. First, according to the delay time information supplied from the control signal interpolation means 18, the address of the decimal point expression read from the storage means 20 is (I +
D) (I: integer address, D: decimal point address),
The stored data of the integer address I is W _I , and the integer address I +
When one of the stored data is to W _{I + 1,} data (delayed data) W _{I + D} of the address point representation (I + D) _{is, W I + D = W I} + 1 × D + W I × (1-D) of It can be calculated by interpolation.

In the above configuration, when the real-time operator 10 is operated, this operation state is detected by the operation detecting means 16 in the first cycle, and the detection result (first control signal) is sent to the control signal interpolating means 18. Given. The control signal interpolation means 18 performs interpolation in a second cycle shorter than the first cycle and longer than or equal to the sampling cycle, and supplies the result to the control means 24 as delay time information (second control signal). I do. Then, the control unit 24 reads out the delay data necessary for calculating the delay signal from the storage unit 20,
An interpolation operation is performed by the delay data interpolation means 22, and the input tone signal is delayed and output based on the interpolation operation result.

For this reason, even when the delay time is changed, interpolation is performed so that discontinuous points of the tone signal do not occur, so that generation of noise can be reliably prevented.

In the above-described first embodiment, the control signal interpolation means 18 has been described with respect to the process of performing linear interpolation. However, the present invention is not limited to this, and an integration circuit and a filter are simulated. Stuff, n
As a matter of course, the processing may be performed by another interpolation method such as n-th order interpolation using a quadratic function.

Further, for a simulated integration circuit or filter, the speed at which the interpolation changes can be arbitrarily controlled by the value of the parameter corresponding to the time constant.

Furthermore, the first cycle, which is the cycle in which the operation detecting means 16 reads out the operation state of the real-time operator 10, is a periodical cycle in the first embodiment, but the operation amount of the real-time operator 10 is fixed. May be non-periodic so that the value is detected and output only when is greater than or equal to a predetermined amount.

The interpolation method of the delay data interpolation means is also as follows.
An interpolation method used in a sound source device of a storage waveform reading method of an electronic musical instrument may be used.

FIG. 2 is a block diagram showing a second embodiment of the delay device according to the present invention. The first embodiment differs from the first embodiment in that the processing of each component is realized by a CPU and a DSP. Is different.

That is, in the second embodiment, the operation detection means 16 of the delay time setting means 12 is constituted by a CPU, and the control signal interpolation means 18 and the delay means 14 of the delay time setting means 12 (the storage means 20, Delayed data interpolation means 2
2 and the control means 24) are constituted by a DSP.

FIG. 3 is a flowchart showing the processing of the operation detecting means 16 in the second embodiment. The operation detecting means 16 operates at a period longer than the sampling period. Assuming that the operation is performed at a cycle of n times T _s , the processing of the flowchart shown in FIG. 3 is executed every time nT _s .

That is, first, in step S302,
The current value P of the real time operator 10, and inputs each time nT _s.

When the process in step S302 is completed, the process proceeds to step S304, where the current value P input in step S302 is compared with the output value _Pc previously output to the control signal interpolation means 18.

If it is determined that the current value P and the output value _Pc are the same as a result of the determination in step S304, the real-time operator 10 has not performed any operation. The process of this flowchart ends without performing anything.

On the other hand, if it is determined in step S304 that the current value P and the output value _Pc are not the same (different), it is determined that the real-time operator 10 has been operated. Proceed to S306.

In step S306, the output value P _c
To the current value P. When the processing in step S306 ends, the process proceeds to step S308.

In step S308, step S306
The output value _Pc rewritten in is output to the control signal interpolation means 18, and the processing of this flowchart ends.

The processing of the operation detecting means 16 is different from that of the first embodiment, and is different from that of the first embodiment.
Only when is operated, operation data based on the operation is output to the control signal interpolation means 18.

FIG. 4 is a flowchart showing the processing of the control signal interpolation means 18 in the second embodiment.
The operation of the control signal interpolation means 18 simulates the charging / discharging characteristics by the calculation executed in step S408 described later, and the output value _Pc input from the operation detection means 16 is determined by the control signal interpolation means 18 , The charge / discharge target value is changed.

[0043] Further, since the control signal interpolation means 18 is adapted to operate at a sampling period T _s, time T _s
The process of the flowchart shown in FIG. 4 is executed every time.

It should be noted, "T _s <lT _s <nT _s" (l, n is a positive integer) may operate at a cycle of "lT _s" in the case of.

First, in step S402, it is determined whether the real-time operator 10 has been operated and the output value _Pc has been input.

If the determination result of step S402 is affirmative (Y), that is, if the real-time operator 10 is operated and the output value _Pc is input, the process proceeds to step S404, and the determination result of step S402 is negative (N). That is,
The real-time operator 10 is not operated and the output value P _c
If has not been input, the process proceeds to step S406.

In step S404, the output value P _c
Is input, the charge / discharge target value M is changed to the output value _Pc .

Upon completion of the process in step S404, the flow advances to step S406 to set a value K specified by an operator (not shown). This value K corresponds to the time constant of the charge / discharge circuit, and can be set as appropriate by operating an operation member (not shown).

[0049] Upon completion of the processing in step S406, the process proceeds to step S408, by performing the operation of _{D n + (M-D n} ) / K simulates the charge-discharge characteristics, changes the D _n.

[0050] Upon completion of the processing in step S408, the process proceeds to step S410, and outputs the D _n obtained in step S408 to the delay unit 14 as the delayed data, and ends the processing of this flowchart.

Therefore, according to the above-described second embodiment, the interpolation processing of the operator data is performed by the DSP, and the processing is divided into the CPU and the DSP.
Since the data to be transferred from the PU to the control signal interpolating means 18 is configured so as to be required only when the real-time operator 10 is operated, the CPU processing is shorter than that for transferring the real-time operator data periodically. The burden is reduced, and other processing can be performed.

It is needless to say that various modifications similar to those of the first embodiment may be made in the second embodiment.

As described above, in either the first embodiment or the second embodiment according to the present invention, the delay time is changed in real time by operating the real-time operator 10. As a result, the delay time can be controlled in accordance with the atmosphere and performance state of the performance hall, and the performance expression becomes extremely rich.

That is, specifically, the present invention can be used in the following cases.

1. Vibrato When the delay time is changed in real time while the delay signal is being generated, frequency modulation occurs, and if the control is performed periodically, a vibrato effect can be added.

Unlike the modulation by the periodic signal generated by the oscillator, a vibrato effect according to the player's control can be added.

2. Pitch Bend By controlling the above-described frequency modulation to one side, a pitch bend effect can be added. For example, if the delay time is controlled to be shorter, the pitch increases. Conversely, if the control is made to increase the delay time, the pitch will decrease.

Therefore, a pitch bend effect according to the control of the player can be added in real time.

In an electronic musical instrument having a sound source,
Although there is a type in which pitch bend can be freely controlled by directly controlling a sound source, the present invention is different from the configuration in that a pitch bend effect is added to a tone signal input from the outside.

3. Real-time setting of delay time Since a delay time that matches the performance tempo can be set, it is advantageous when obtaining a delay signal with a repetition cycle that matches the performance tempo. That is, since the real-time operator can be operated while listening to the delay signal, it is possible to reliably cope with a change in the performance tempo.

There is a delay device which can set a delay time by operating a switch of an operation element in a cycle of a performance tempo. In such a delay device, however, the delay time changes from the next operation cycle. It is supposed to
The delay time changes discontinuously, and does not change continuously as in the present invention.

[0062]

Since the present invention is configured as described above, it is possible to continuously and arbitrarily change the delay time by operating the real-time operator.
In addition, even when the delay time is continuously changed without performing muting at this time, there is an excellent effect that it is possible to reliably prevent the possibility of noise occurring due to the occurrence of a discontinuity point in the tone signal. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a delay device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the delay device according to the present invention.

FIG. 3 is a flowchart illustrating a process of an operation detecting unit according to the second embodiment.

FIG. 4 is a flowchart illustrating processing of a control signal interpolation unit according to the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Real-time operator 12 Delay time setting means 14 Delay means 16 Operation detection means 18 Control signal interpolation means 20 Read / write storage means 22 Delay data interpolation means 24 Control means

Claims (2)

[Claims] 1. A real-time operator for performing operation control in real-time, and a delay time setting means for setting a delay time of a tone signal input at a predetermined sampling cycle from an input terminal in accordance with an operation of the real-time operator. Delay means for delaying the tone signal by the delay time set by the delay time setting means and outputting it to an output terminal, wherein the delay time setting means is longer than the predetermined sampling period. In a cycle, a first control signal that is an operation state of the real-time operator is detected, an interpolation operation is performed on the first control signal, and the shorter than the first cycle, and the predetermined sampling cycle. A second control signal having a longer or equal second period is generated and supplied to the delay unit, wherein the delay unit performs the predetermined sampling. The tone signal input in the cycle is
A storage unit that stores the data as readable and writable as storage data; and a read address of the storage unit using an address in a decimal point expression corresponding to the second control signal supplied from the delay time setting unit, and A delay data interpolating means for performing an interpolation operation using the stored data of (1), generating delay data corresponding to the second control signal, and outputting the delay data to an output terminal. 2. The delay data interpolation means according to claim 1, wherein said delay data interpolation means interpolates storage data corresponding to an address in a decimal point expression separated from a write address by an address corresponding to said second control signal supplied from said delay time setting means. Means for reading out a plurality of storage data required for the interpolation operation and performing an interpolation operation for calculating storage data corresponding to the address of the decimal point expression using the plurality of storage data. The delay device according to claim 1.