GB2040537A - Digital electronic musical instrument - Google Patents

Abstract

An electronic musical instrument, is characterised by a data distribution network interconnecting data processing means and data storage means, wherein at least one such data storage means stores data from which a waveform of the desired sound may be derived; means for producing a plurality of microinstructions from which sets of data flow control signals may be derived, said data flow control signals determining the source and destination of data being handled by said distribution network; and means for storage and retrieval of a program of said microinstructions, said program effecting control of data flow in a manner such as to allow the generation of the desired sound. Preferably said program effects control of data flow in a manner which allows the substantially simultaneous generation of a plurality of waveforms. <IMAGE>

Description

SPECIFICATION An output processing system for a digital electronic musical instrument FIELD OF THE INVENTION This invention relates to musical sound generating systems and more particularly to output processing apparatus whose data-flow is controlled from a stored set of control instructions.

BACKGROUND TO THE INVENTION Keyboard operated electronic musical instruments of the digital waveform synthesising type are well known, notable examples being U.S. Patents 3,515,792, 3,809,786 and 3,639,913. When it is required to produce a polyphonic waveform synthesiser wherein several waveforms of different fundamental pitch, instantaneous amplitude and harmonic content are to be generated simultaneously, several options for implementation are open. One waveform generator could be assigned for each simultaneously sounded not up to some maximum number of allowable notes. This is expensive in production if the maximum allowable number is high. An alternative is to use time-sharing techniques using just one tone generator wherein each simultaneous note is given a discrete time slot in a repetitive sequence of time slots. U.S.Patent 3,639,913 describes such a technique wherein the 'phase-angle calculator' and the wave-shape memory are shared by each simultaneously generated tone.

Control of data flow through such a time-shared system needs to be very precise in order for the system to perform correctly. As the maximum allowable number of simultaneously sounded notes increases so the logic circuitry for producing the necessary data flow control signals also increases. The implementation of this control signal logic is specific to the particular system which is being controlled and therefore only a "random logic" array comprising S.S.I. circuits or a dedicated and inflexible L.S.I.

circuit can be used. The waveform generator therefore becomes expensive either due to the high volume of S.S.I. circuits required in production or the high pre-production investment in a special purpose L.S.I. controller.

SUMMARY OF THE INVENTION It is an object of the present invention to implement a data distribution network between the data storing and data processing elements within the generating system wherein the data distribution network is controlled from a stored programme of control instructions, thus removing the need for specific logic S.S.I. circuits or a special purpose L.S.I. device.

It is a further object of this invention to control the data distribution network in a manner which reduces the number of data processing elements required by, for example, using the same arithmetic calculation element at more than one stage of an output calculation.

A further object of the invention is to enable more than one control algorithm to be performed, by selecting different stored microprograms dependent upon predetermined system requirements.

BRIEF DESCRIPTION OF THE DRAWINGS An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawing in which the single Figure, Figure 1, shows a block diagram of an output control system (output processor) for an electronic musical instrument. Also referred to are: Appendix 1: a table containing the instruction set of the output control system, and Appendix 2: a table containing the microprogram itself i.e. the order in which the microinstructions occur.

DETAILED DESCRIPTION OF FIGURE 1 Referred to Figure 1 , the output control system uses an input control processor to supply its input information. The data storage devices used by the system include 1 Kbyte RAM memory used as workspace and temporary storage and 3byte ROM memory for holding waveshape tables and other information permanently required by the system. The data processing device comprises an 8 bit parallel adder with 'carry control'. Analogue outputs to a sound system (not described) are provided by two 8 bit Digital to Analogue converters of standard design. The data distribution network comprises:-- a) A 12 bit address bus.

b) An 8 bit data bus.

c) An 8 bit sum bus.

d) Registers ED and EA (data and address from input controller).

e) Registers DAO and DA1 (output data to D-A converters).

f) Registers RO and R1 (Calculation data to the adder).

g) Register SM (Sum to data bus transfer).

h) Register LI (Sum to address bus transfer).

i) Register Ml (Data to address bus transfer).

The microprogram of control instructions is held in the microprogram ROM memory and is addressed directly from the construction counter shown in the figure. The microprogram contains no 'jump' instructions except 'return to beginning of sequence' i.e. 'clear contour. Each microinstruction so accessed is appropriately decoded and held in the microinstruction register and this register contains both individual control signals and information relevant to RAM addresses. The RAM address is further controlled by register CD and is enabled onto the address bus via tri-state enable devices.

The timing of the input control processor and the output control system is derived from a common central timing clock.

It will be noted that all the registers, memory devices and the adder circuit are standard devices and will be familiar to those skilled in the art of digital engineering. A more detailed description of the internal workings of these 'building blocks' is therefore omitted.

OPERATIONAL REQUIREMENTS OF THE OUTPUT CONTROL SYSTEM By way of example only, a generating system is described herein which is similar in operating principle to that shown in U.S. Patents 3,639,913 and 3,743,755 in terms of waveshape storage and access but improved in terms of polyphonic efficiency by way of microprogram-controlled data flow. It will be appreciated by those skilled in the art of digital musical instrument design that the same data flow control techniques could equally be applied to other operating principles such-as the Fourier calculation technique described in U.S. Patent 3,809,786.

The requirements for keyboard scanning and polyphonic note assignment are well known in the art and for ease of description of the present invention it is assumed that these requirements are fulfilled in a separate part of the musical instrument and that the input control processor shown in Figure 1 is capable of supplying to the output control system the following information for each simultaneously sounded note.

a) A frequency constant (equivalent to the 'phase-angle number' described in U.S. Patent 3,639,913).

b) The base address of the desired waveshape store or 'sound table' held in ROM in the output control system.

c) The base address of the Logarithmic to Linear Conversion table held in ROM in the output control system.

d) An attenuation value representing the amplitude modulation required on the waveshape in order to produce a desired sound envelope characteristic.

GENERAL OPERATIONAL DESCRIPTION The particular embodiment being described produces up to four notes simultaneously. Each note can have a different sound characteristic (waveshape), frequency and amplitude relative to the other notes.

The system holds the waveshapes of various sounds in tabular form in ROM. The tables hold a single cycle of the sound split into 256 samples evenly distributed in the time domain. The samples hold the amplitude of the sound encoded in logarithmic form together with a sign bit.

The ROM also holds a table of 256 entries which converts logarithmic numbers to linear numbers.

The process of calculating the next output from the system takes a finite length of time. Let this be called the sample period. To produce a note of a particular frequency, a constant is added to an accumulating total (overflow being ignored) each sample period. The most significant eight bits of the accumulating total are used to address the relevant sound table to obtain the amplitude of the current sample. The relationship between the constant added for each sample period and the resultant frequency is as follows:- Constant Frequency = 2N x sample period where N is the number of bits used in the addition. In this particular embodiment N = 1 6.

For high-frequency notes, successive entries in the sound table will be missed out between successive accesses of the sound table. For low-frequency notes, successive accesses of the sound table can produce the same sound table entry.

To the sample value retrieved from the ROM is added a number, also held in logarithmic form, which represents the attenuation required on the note. The result of this addition is used to address the logarithmic-to-linear conversion table held in ROM. The value so obtained is the linear value of the current sample multiplied by the required attenuation value.

The above procedure is performed for each of the four notes and the resulting four values are added together to form the current sample period's output. This output is fed to a D-to-A converter to produce an analogue output.

The sequence of events described above is performed every sample period.

OPERATIONAL DESCRIPTION OF THE HARDWARE The microprogram of the output control system contains no jumps, hence it can be addressed from the counter which is reset (PE3) at the end of the sequence. The output from the microprogram ROM is decoded, and then loaded into the microprogram instruction register, at the beginning of each microinstruction cycle of the system. The microinstruction register contains address information and control information to perform the instruction repertoire of the output control system.

Information is transferred from the input control processor to the RAM of the output control system by the input control processor simultaneously loading registers ED and EA (by load pulse SRR).

The ED is loaded from the DATA bus and the EA register is loaded from the least significant ten bits of the ADDRESS bus of the input control processor. A specific microinstruction is used to enable register EA onto the ADDRESS bus (PE3) and register ED onto the DATA bus and effect a 'write' cycle in the RAM. The microinstruction may be performed several times before the Contents of ED and EA are changed, but this has no effect since the information in question is not changed by the output control system itself.

The ROM is split into twelve 256-byte tables each starting at address N (Hex) where N is the table number.

The only RAM addresses used in this system are O) to Q)3F, which, for ease of programming, are conceptually split into four blocks of 16 bytes. Each of the four notes 'played' concurrently by the system is allocated one of these blocks, (numbered S3). The information stored in a block is as follows:: O least significant byte of constant 1 most significant byte of constant 2 attenuation of note 3 base address of sound table 4 base address of log/linear table 5 unused 6 unused 7 unused 8 least significant byte of accumulating total 9 most significant byte of accumulating total A workspace B zero (not 0 only) C unused D unused E unused F unused Addresses 0 and 1 contain the 1 6-bit constant added to the accumulating total (addresses 8 and 9) each sample period. Address 2 contains the attenuation value of the note in logarithmic form. The most significant seven bits are used and the attenuation value is held in l's complement form. The least significant bit is set to zero.

The least significant four bits of address 3 contain the table number holding the required sound table. The contents of the table are in logarithmic form. The most significant seven bits are used, the least significant bit holds the sign.

The least significant four bits of address 4 contain the table number holding the log-to-linear conversion table. The contents of this table are in conventional form, the most significant bit being the sign bit. Addresses 8, 9 and A are used as workspace by the output control processor; address B in block 0 must be set to zero by the control processor.

The instructions that can be performed by the output control system are tabled as appendix 1, which is given at the end of this specific description and is intended to be read in conjunction with the block diagram of Figure 1. Instructions EY and FX clear the microprogramme counter at the end of the cycle, when the next instruction is loaded into the n'icroinstrucfion register,-hence one more'instrudtion is executed before the first instruction of the sequence of instructions (at address zero) is fetched.

Registers Ml and LI form an indirect register which is used to access the sound tables held in the ROM. It will be noted that some tables could also be held in the unused portion of the RAM, provided they were first entered there by the input control processor.

Register CD, and the least significant four bits of certain instructions, form the direct register for accessing the first 256 bytes of RAM.

Manipulation of the carry flip-flop is required for multiple-length working. The requirement to clear register LI when carry is not set is explained later.

OPERATIONAL DESCRIPTION OF THE SOFTWARE The data flow and microprogram instruction set of the output control system allows for a large variety of output algorithms other than the one described in this particular embodiment. The program used for the device being described is given at the end of the overall description as Appendix 2 but it will be appreciated that more or less notes, and such things as stereo output, could easily be incorporated into it.

The program tables in Appendix 2 consists of four similar sections each one generating one of the four notes.

The first section (counter value 0 to D) generates the same value for note zero in RAM location 1A.

The section is entered with register CD containing zero and the carry flip-flop clear. Location OB has previously been set to zero by the input control processor, which has also set the required values in addresses 00 to 04, 10 to 14,20 to 24 and 30 to 34.

The first seven instructions (counter values 0 to 6) add the double length frequency constant to the double length accumulating total. This is done by using the carry flip-flop.

Instruction 5 loads the indirect register with the address of the required sound sample. Instruction 7 fetches the sample into register 0 (the contents of CD are not changed even though it is loaded).

Instructions 8 and 9 add the attenuation to the sample and put into the indirect register the address of the calculated entry in the logarithmic-to-linear conversion table.

Since the attenuation value is held in "1's complement" form, the result of the calculation will be to cause a carry from the adder if the sample value is larger than the required attenuation: if the reverse is true, underflow occurs and carry is not generated. Instruction A clears the LI register if underflow occurred, the base value of the log/linear conversion table contains no output.

Since the least significant bit of the sound sample is the sign bit, and the least significant bit of the attenuation value is zero, and that for the addition the carry flip-flop is clear, the sign bit of the result is the same value as that of the sound sample.

Instruction A also enters information from the input control processor into the RAM. Instruction B loads zero into register 0 (since the input control processor sets RAM address OB to zero). Instruction C enters the linear value of the computed sound sample modified by the attenuation into register 1 and updates the contents of register CD in anticipation of the sequence for calculating the sample fdr note 1. Instruction D puts the computed value for note 0 into RAM address 1 A (since RO contains zero).

The sequence for the remaining three notes is similar to that described above, except that instructions 1 9 to 1 27 to 29 and 35 to 37 are used to add the four derived samples together. The result of this addition process is loaded into the D to A converter register by instruction 38.

Instruction 37 clears the microprogram sequence counter, thus causing the complete sequence to be recommenced after instruction 38.

Thus, in the manner described above the output control system simultaneously generates up to four notes each of which can have different sound characteristics with respect to each other. It will beappreciated that having structured the data flow in such as system the flexibility of control algorithm which may be performed is greatly enhanced by storing several different microprogrammes each written from the same instruction set. It will also be apparent that if the selection of these microprograms is controlled by the input control processor a different control algorithm could be performed dependent upon some specific requirement of the input.An example of the improvement that this could have is explained as follows:- In a polyphonic sound generator having a maximum allowable number of simultaneously played notes of 1 6 and using a fixed, dedicated data flow control technique as described in the prior art examples, certain compromises to the accuracy of synthesis may have to be made. This is due to the processing time constraints put on by the logic device types used to implement the system. In such a generator these compromises will still be present even if only one note is to be sounded at any given time. Whilst these compromises may not be noticed when 16 notes are simultaneously played due to the overall complexity of the sound, they may be discernable when, for example, an unaccompanied solo is performed. Using the improvements described in the present invention different control algorithms due to different microprograms could be selectable and dependent upon the number of simultaneously sounded notes required at any given time. This can result in a higher accuracy of synthesis the fewer the simultaneous notes required, since more processing time can be made available under these circumstances.

APPENDIX 1 MICROPROGRAM INSTRUCTION SET FOR OUTPUT CONTROL SYSTEM

instruction Control Code Signals (HEX) Function Description Produced 1Y RAM H RO Load RO with PE1 contents of RAM address OZY (HEX) PSO where Y is least significant 4 bits READ of instruction and Z is contents of register CD.

5Y RAM R1 Load R1 with PE1 contents of RAM address OZY. PS1 READ 9Y RAM -MI: Load Ml wi th PE1 least significant SM#L1 4 bits contained PS2 in RAM ad((ress OZY. LI is READ loaded with contents of SUM BUS.

DY RAM W DA DA output PE1 register selected by least significant PDAO or 1 bit of Y is loaded with contents of READ RAM address OZY.

2Y SM#RAM Load RAM address RE1 OZY with contents PE2* of SUM BUS. WRITE 6Y SM#RAM: Load RAM address PE1 strobe carry OZY with contents F/F of SUM BUS and PE2* enter current carry value out WRITE of adder into carry flip-flop. PR1 AY SM#RAM: Load RAM address PE-i clear carry OZY with contents PE2* F/F of SUM BUS and WRITE clear carry flip-flop PR2 EY SM#RAM: Load RAM address PE1 clear counter OZY with contents PE2* of SUM BUS and WRITE set microprogramme PR3 counter to zero.

APPENDIX 1(Continued)

Instruction Control Code Signals (HEX) Function Description Produced OZ (1)#RO: RO is loaded with PEO contents of address Z#CD contained in Ml PSO and LI; CD is loaded with Z, READ Z being least significant 4 bits of instruction.

4Z (1)#R1: R1 is loaded with PEO contents of address Z#CD contained in Ml and PSO LI; CD is loaded with Z. READ CZ (1)#DA: D to A output PEO register selected Z#CD by least significant PDA0 or 1 bit of Z is loaded with contents of READ address contained in MI and LI: CD is loaded with Z.

3X ED#(EA): Contents of ED PE3 are loaded into LI = LI x carry RAM address CLEAR= contained in EA: CARRY PE3 LI is cleared if carry out of adder WRITE is zero: X is not decoded as part of instruction and therefore can be any Hex value.

FX ED = (EA) Contents of ED are PE3 LI = LI x carry loaded into RAM clear counter address contained CLEAR = in EA; LI is cleared if carry carry PE3 out of adder is zero; micro- PR3 programme counter is set to zero. WRITE *Contents of sum bus are loaded into register at the beginning of the cycle in case the sum bus changes value during the cycle due to changes to the carry flip-flop.

APPENDIX 2 MICROPROGRAM FOR THE OUTPUT CONTROL SYSTEM

Counter Instruction Value Code (HEX) (HEX) Function Comments 0 10 00 > RO 1 58 08 # R1 2 68 SM - @ 08: strobe carry F.F. Update accumulating 3 11 01 # R0 total of note 0 4 59 09 > R1 5 93 03 # Ml: SM > LI 6 A9 SM > 09: Get current sample value from relevant clear carry F.F. sound table into RO 7 00 (1) # R0: # 0 # CD # 8 52 02 # R1 Add attenuation and 04 Ml: # set up pointer to 9 94 SM # Ll log/linear table A 30 ED # (EA): # Input value from LI = LI x carry control processor, clear LI if carry + LI from adder is not set B 1B 0B # R0 Get linear value of note 0: add to C 41 (1) R1: # zero (0B is set to 1 # CD zero): store result in 1A; load CD with D 2A SM # 1A base address of RAM block for note 1 E 10 10 - > R0 F 58 18 - > R1 10 68 SM > 18: strobe carry F.F. Update accumulating total for note 1 11 11 11 # R0 12 59 19 # R1 # 13 93 13 # Ml: SM # Ll APPENDIX 2 (Continued)

Counter Instruction Value Code (HEX) (HEX) Function Comments 1,4 A9 SM A 19: @ Get current sample value from relevant clear carry F.F.

# sound table into 15 01 (1) # RO: I - > CD 16 52 12 # R1 Add attentuation and set up pointer 17 94 14 # Ml: to log/linear table SM # Ll 18 30 ED # (EA): Input value from control processor, clear Ll if carry # Ll from adder is not set 19 1A 1A 1A RO Get linear value of note 1: add to 1A 42 (1) # R1: note 0: store 2 > CD result in 2A: load CD with base 1B 2A SM # 2A address of RAM block for note 2 1C 10 20 2OR0 1D 58 28 # R1 Update accumulating 1E 68 SM # 28: total for note 2 strobe carry F.F.

1F 11 21 # RO 20 59 29 # R1 21 93 23 # Ml: SM # Ll APPENDIX 2 (Continued)

Counter Instruction Value Code (HEX) (HEX) Function Comments 22 A9 SM # 29: Get current sample value from relevant clear carry F-F # sound table into RO 23 02 (1) # RO: 2 # CD 24 52 22 > R1 Add attenuation and set up pointer 25 94 24 ,- MI: to log-linear table SM # Ll # 26 30 ED # (EA): # Input value from control processor; clear LI x carry clear LI if carry # Ll # from adder is not set 27 1A 2A # RO Get linear value of note 2: add to 28 43 (I) sRI: current total of 3 # CD notes 0 and 1 store result in 29 2A SM 6 3A 3A: load CD with base address for note 3 2A :10 30 30 # RO 2B 58 28 > R1 2C 68 SM # 38:: Update accumulating strobe carry F-F total of note 3 2D 11 31 # RO 2E 59 39 > R1 2F 93 33-*Ml: SM # Ll # 30 A9 SM # 39: Get current sample # value from relevant clear carry F-F sound table in RO 31 03 (I) RO: 3 > CD 32 52 32 # RI Add attenuation and set up pointer 33 94 34 > Ml: to log/linear table SM * LI

Claims (4)

1. An output processor for an electronic musical instrument, characterised by: a data distribution network interconnecting data processing means and data storage means, wherein at least one such data storage means stores data from which a waveform of the desired sound may be derived; means for producing a plurality of microinstructions from which sets of data flow control signals may be derived, said data flow control signals determining the source and destination of data being handled by said distribution network; and means for storage and retrieval of a program of said microinstructions, said program effecting control of data flow in a manner such as to allow the generation of the desired sound.

2. An output processor according to claim 1, characterised in that said program effects control of data flow in a manner which allows the substantially simultaneous generation of a plurality of waveforms.

3. An output processor according to claim 1 , characterised by means to select said program from a stored set of programs wherein each selected program effects a different control of data flow from that effected by any of the other programs.

4. An output processor according to claim 3, characterised in that selection of said program from said set of programs is automatic.

APPENDIX 2 (Continued)

Counter Instruction Value Code (HEX) (HEX) Function Comments 34 30 ED b(EA): Input value from control processor; LI = LI x carry clear LI if carry Ll Ll from adder is not set 35 1A 3A # RO Get linear value of note 3: add to 36 40 (I) b R1: total of notes 0, total @@ @otes @, 1 and 2 : store 0 # CD result in OA: load 37 EA SM > OA CD into base clear counter address of RAM clear counter block for note 0: clear microprogramme counter 38 DA OA # DAO Output total of 4 notes to D-to-A converter