JPH06250654A - Electronic musical instrument - Google Patents

Abstract

PURPOSE:To provide the electronic musical instrument which has an envelope generator and can control speed data on a segment repeated by the envelope generator. CONSTITUTION:The envelope generator of the electronic musical instrument which has the envelope generator is equipped with a storage means 100 which stores data for envelope generation of respective segments, an arithmetic means 106 which sequentially calculates an arrival signal outputted when an envelope value and a target value of its segment are reached and outputs it to the outside and storage means, a control means which repeats transition between specific segments on the basis of data read out of the storage means 100 and the arrival signal when specific conditions are met, and a selecting means which selects specific data among plural speed data read out of the storage means 100 and outputs it to the arithmetic means 106 on the basis of the data read out of the storage means 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument having an envelope generator, which can repeat a segment and control an envelope speed at the time of repeating. It is a thing.

[0002]

2. Description of the Related Art Conventionally, some electronic musical instruments have a waveform read-out tone generating means. This method
A tone signal having a waveform memory storing tone waveforms corresponding to a plurality of tones, reading waveform data from the waveform memory at an address interval corresponding to a pitch, and multiplying the envelope data generated by an envelope signal generator with the tone signal. Generate.

The second method is a signature combining method. This is based on the theory of Fourier synthesis that any periodic signal can be expressed by a combination of harmonics that are an integral multiple of the fundamental period, and multiple harmonics with different levels (envelopes) are added depending on the timbre to create an arbitrary tone waveform. I will get it.

In this system, an envelope for each harmonic or an envelope of a synthesized tone signal is generated by an envelope signal generator and multiplied by a waveform signal. An envelope signal generator is also used for various effects.

As an envelope generator used for the above-mentioned applications, the envelope is divided into a plurality of sections, that is, segments, and an envelope value is calculated by an arithmetic circuit based on the target value and speed data of each segment. It has been known. In addition, in order to obtain an LFO-like effect, a method has been proposed in which specific data is set and the transition between specific segments is repeated.

[0006]

In the envelope signal generator that repeats the transition between the specific segments as described above, since the speed data is fixedly assigned to the segment, the transition between the segments is repeated. However, there is a problem that the change becomes unnatural.

An object of the present invention is to improve the above-mentioned problems of the prior art and, in an electronic musical instrument having an envelope generator, an electronic musical instrument capable of controlling speed data of a segment repeated by the envelope generator. The purpose is to provide.

[0008]

According to the present invention, in an electronic musical instrument having an envelope generator, the envelope generator stores the data for generating the envelope of each segment, and the data read from the memory means. Based on the envelope value and the arrival signal output when the target value of this segment is reached are sequentially calculated and output to the external and storage means, the data read from the storage means, and the arrival signal , A specific one of a plurality of speed data read from the storage means based on the data read from the storage means and the control means that repeats the transition between the specific segments when a specific condition is satisfied. And selecting means for selecting and outputting to the calculating means.

[0009]

According to the present invention, the speed data of the repeating segment in the envelope generator can be selected by such means. For example, by repeating the segment, the LFO-like effect can be applied to a continuous musical tone such as an organ sound. When added, a natural envelope change can be obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a hardware configuration of an electronic musical instrument which is an embodiment. The CPU 1 controls the entire electronic musical instrument such as key assignment and sound generation control. RO
M2 stores programs required for control and data such as harmonic coefficients for each tone color, phase shift data, and envelope data.

The RAM 3 stores panel setting information such as tone color, tempo and volume, various control data in the musical instrument, automatic performance data and the like. Further, at least a part of the battery is backed up by a battery so that the tone color information set from the panel can be retained even when the power is turned off. The keyboard unit 4 includes a keyboard and a circuit for scanning a plurality of key switches of the keyboard under the control of the CPU 1.

The panel section 5 comprises a panel provided with operation switches, a volume and a display such as an LCD or LED, a panel scan circuit for scanning the switches of the panel under the control of the CPU 1, and a drive circuit for the display.

The tone generation section 6, which will be described in detail later, creates waveform information of a desired tone color by a sine synthesis method, stores this waveform information in a RAM, and digitally reproduces a pitch corresponding to a keyboard by a waveform reading method. A musical tone signal is generated. It also includes a sound image effect circuit and a reverberation effect circuit. The D / A converter 7 adds and synthesizes digital tone signals of all channels, and D / A converts the signals. The analog signal processing unit 8 is a circuit that performs filter processing for noise removal on the analog tone signal.

The amplifier 9 amplifies a musical tone signal in order to drive one or a plurality of speakers 10. The bus 11 connects each circuit in the musical instrument. In addition, it is configured so that the left and right stereo signals are output from the musical sound generation unit, and D /
Two systems may be provided for each of the A converter 7 to the speaker 10. In addition to this, a MIDI interface circuit or the like may be provided.

FIG. 2 is a block diagram showing the internal structure of the tone generation circuit 6 of FIG. The execution control circuit 20 incorporates a system counter that regulates the operation of the musical tone generating section 6 and generates various control signals such as a clock, an address signal, and an interpolation signal. It also includes an interface circuit between the CPU 1 and each tone generator circuit described below, and this circuit has a buffer memory for exchanging data.

The harmonic information generator 21 will be described in detail later, but the envelope information for each harmonic of the sine synthesis method,
The phase shift information is generated and written in a built-in buffer memory (harmonic memory 36 described later) for transfer to the next waveform calculation unit 22.

As will be described later in detail, the waveform calculator 22 reads envelope information and phase shift information of each harmonic from the buffer memory, obtains amplitude information for each harmonic, and further obtains the amplitude information. Accumulation is performed for each musical sound, and waveform information for each musical sound is output. The calculation of this waveform is not performed in real time, but at a cycle of, for example, about 8 milliseconds.
A plurality of waveform data of is updated.

As shown in FIG. 15D, the waveform memory 23 is a waveform memory for storing a synthesized waveform composed of three areas A, B and C, and each area generates a plurality of (for example, 16 channels) musical tones. It is divided into areas for channels. In the area of each channel, one cycle of musical tone waveform data (for example, 512 sample points) is written from the waveform calculator 22.

The waveform calculator 22 is provided in each channel region of the A region.
While the waveform data is being written in, the waveform data written in the previous time is read from the B and C areas two times before. The reason why the waveforms are read from the two regions is that the waveform interpolation circuit 26 in the subsequent stage performs interpolation calculation in order to prevent the amplitude value from changing rapidly when switching the waveforms.

When the waveform writing in the area A is completed, the writing and reading areas are switched, and this time the waveform data is written in the area B and read from the areas C and A. A control signal for writing or the like is supplied from the execution control circuit 20.

The waveform reading circuit 24 has a structure similar to that of a circuit of a normal waveform reading system, and waveform data is read from the waveform memory at an address interval corresponding to a desired tone frequency corresponding to a depressed key. An address signal for reading is generated. The selector 25 switches between the write address from the execution control circuit 20 and the read address from the waveform read circuit 24 by the control signal from the execution control circuit 20, and supplies the address signal to the waveform memory 23.

As described above, the waveform interpolation circuit 26 simultaneously reads the waveform data from two areas other than the area currently written in the waveform memory 23 so that the waveform value does not change abruptly when the waveform data is switched. , Performs interpolation calculation and outputs waveform data.

As a method of interpolation, for example, the following method can be adopted. First, the waveform update period is divided into 16 time slots. Now, the writing of the area B is completed,
Assuming that writing to the area C has started, the output waveform data D at this point (first time slot) is
D = (16/16) An + (0/16) Bn.
Here, An and Bn are waveform data read from the A and B areas, respectively.

Then, in the next time slot, D =
As in (15/16) An + (1/16) Bn, the weight of the data in the A region gradually decreases and the weight of the waveform data in the B region increases. Then, in the last time slot, D = (1/16) An + (15/16)
Bn.

When the writing to the area C is completed and the areas are switched, the read areas become B and C, and the output of the first time slot is D = (0/16) Cn +
(16/16) Bn. Then, the weight of the data in the B region gradually decreases, and the weight of the waveform data in the C region gradually increases. The waveform interpolation circuit 26 performs the above-described interpolation calculation and outputs gradually changing waveform data.

The envelope generator 27, which will be described in detail later, generates musical tone waveform envelope information based on the data set by the CPU 1 according to the tone color, the strength of key depression, and the like. The multiplier 28 multiplies the waveform information output from the waveform interpolation circuit 26 and the envelope information output from the envelope generator 27, and outputs a digital tone signal.

The tone generating section 6 has the same function as that of a tone signal generating circuit of a normal waveform reading system by the waveform memory 23, the waveform reading circuit 24, the envelope generator 27, and the multiplier 28. Part of
By using a ROM or the like that stores waveform data, tone signal generation by the sine synthesis method for each channel and P
It is also possible to select the tone signal generation of the CM waveform reading method.

Each circuit of FIG. 2 is configured to generate independent tone signals of a plurality of channels by time division multiplexing operation. In the following embodiments, the number of channels will be described as 16. Although not shown, a sound image effect circuit, a reverberation effect circuit, or the like may be inserted between the multiplier 28 and the D / A converter 7 to distribute the tone signals to the left and right and control their respective levels. .

<Harmonic Information Generation Unit>

FIG. 3 is a block diagram showing the internal structure of the harmonic information generation unit 21 of FIG. Phase shift information generator 3
0 and the harmonic coefficient generator 31 have the same circuit configuration, and the harmonic order signal q (for example, the 1st order, that is, the fundamental wave to the 16th order) output from the execution control circuit 20.
(Up to the next harmonic), phase shift information P (address offset amount in the sine waveform memory described later) for each harmonic order, and harmonic coefficient information h corresponding to the tone color.
Is output.

Although the details will be described later, in the ROM 2,
The reference phase shift and harmonic coefficient data are stored for each tone range or touch intensity of a certain tone color, and data corresponding to a specific pitch or touch intensity is output by interpolation calculation in each generator. It is configured to do.

The formant coefficient generator 32, which will be described in detail later, generates a formant coefficient FS for correcting the harmonic coefficient h in accordance with, for example, a tone color and a pitch. The multiplier 33 has a harmonic coefficient h and a formant coefficient FS.
And multiply.

The harmonic envelope generator 34 generates a harmonic envelope signal E for controlling the envelope for each harmonic, as will be described later in detail. The multiplier 35 multiplies the harmonic coefficient h corrected by the formant coefficient FS by the harmonic envelope signal E.
With this circuit, the coefficient for each harmonic can be independently changed over time, and the tone color of a musical tone can be gradually changed during sound generation.

The circuits from the harmonic coefficient generator 31 to the multiplier 35 correct the formant characteristics and change the time for each harmonic, for example, from the fundamental wave to the 16th harmonic of each channel. Harmonic coefficient data H is obtained.

The harmonic memory 36 is composed of two areas A and B, as shown in FIG.
It is divided into first to sixteenth harmonic regions of the channel. Phase shift information P and harmonic coefficient H for each harmonic are written in the area of each harmonic.

When the phase shift and the harmonic coefficient data are written in the respective harmonic regions of the A region, the previously written data for one channel is read out from the B region to the waveform calculation section 22. Therefore, when the writing in one area is completed, the writing and reading areas are switched.
The selector 37 switches the write address WA and the read address RA from the execution control circuit 20 by the control signal from the execution control circuit 20, and supplies the address signal to the harmonic memory 36.

<Waveform Calculation Unit> FIG. 4 is a block diagram showing the internal structure of the waveform calculation unit 22 of FIG. The accumulator 40 is based on the control signal from the execution control circuit 20,
Phase information of each harmonic is sequentially generated. This phase information is
It serves as an address signal for reading the amplitude value of each sampling point (phase point) of the harmonic of each order from the sine waveform memory 42.

FIG. 5A is a block diagram showing the internal structure of the accumulator 40. The adder 401 adds the word number WN (corresponding to the phase information of the fundamental wave) input from the execution control circuit 20 and the output of the AND gate 403. The latch 402 latches the output of the adder 401 with a latch pulse every calculation cycle of each harmonic. The AND gate 403 is the first in the calculation period of each word number.
It outputs a logical product of the control signal which is 0 only during the calculation period of the harmonic, that is, the fundamental wave, and is 1 during the other periods, and the output of the latch 402.

FIG. 5B is a diagram showing the output signal of the latch 402 with respect to the word number WN and the harmonic order q. For example, in the calculation period of the word number 2, since the AND gate 403 outputs 0 in the period in which the harmonic order q is 1, the word number is latched in the latch 402 as it is.

During the next period in which the harmonic order q is 2, the control signal of the AND gate 403 is 1, and the content of the latch 402 is output from the AND gate 403. Therefore, a value twice the word number is output to the output of the adder 401, and the value is latched. In this way, the values twice, three times, and four times the word numbers are sequentially output. These values correspond to the phase information of each harmonic.

The sine waveform memory 42, which will be described later,
For example, when data of 512 sample points (address 9 bits) is stored as one cycle, the adder 40
1 and the latch 402 need only have 9 bits, and overflow bits are ignored. Further, the word number WN may be up to 255 for a half cycle as described later.

Returning to FIG. 4, the adder 41 adds the output address signal of the accumulator 40, which is phase information for each harmonic, and the phase shift information P read from the harmonic memory 36. Then, the amplitude information corresponding to each harmonic is read from the sine waveform memory 42 by the addition output address signal.

The sine waveform memory 42 is a memory that stores, for example, amplitude value data of 512 sample points of the sine waveform, and may store data for one period, but the symmetry of the waveform is used. Then, it is also possible to store data for 1/2 or 1/4 cycle and obtain data for one cycle by processing the address and read data.

The multiplier 43 multiplies the amplitude value data read from the sine waveform memory 42 by the harmonic coefficient H read from the harmonic memory 36. Therefore, at the output of the multiplier 43, the first to sixteenth musical tones corresponding to the desired tone color and formant at a certain sample point are output.
Amplitude data of the second harmonic is sequentially obtained.

The circuit from the adder 44 to the latch E52 forms an accumulator of harmonic amplitude values, and it is possible to obtain the waveform amplitude values of two sample points separated by a half cycle by one accumulation. It can be configured. So, first 1
A method of obtaining the waveform amplitude values of two sample points separated by a half cycle by accumulating twice will be described.

FIG. 16 is a conceptual diagram showing how to obtain the amplitude values of two sampling points of the harmonics of each of the odd and even phases that are out of phase. For odd harmonics, as shown in FIG. 16 (a), when the amplitude value of a certain point P1 is obtained, the amplitude value of the point P2, which is a half cycle ahead of the fundamental period, is the positive or negative sign of the amplitude value of P1. Will be reversed. Therefore, when a negative number is processed by the two's complement notation, the amplitude value of P2 is obtained by passing it through a complementer which converts the input data into the two's complement.

For even harmonics, as shown in FIG. 16B, when the amplitude value at a certain point P1 is obtained, the amplitude value at a point P2 which is a half cycle ahead of the fundamental cycle is equal to the amplitude value at P1. Will be equal. Therefore, in order to obtain the cumulative value of the amplitudes of the harmonics from 1 to 16 at the two sample points, the following calculation is performed.

First, a cumulative value of only odd harmonics and a cumulative value of only even harmonics are obtained. Next, the accumulated value at the point P1 is obtained by adding both accumulated values. Further, the cumulative value of the even harmonics is added with the complement of the cumulative value of the odd harmonics to obtain the cumulative value of the point P2. By performing such an arithmetic process, the waveform data of the phase-shifted higher harmonics can be obtained by the operation of half the sample points.

Returning to FIG. 4, the adder 44 successively performs accumulation by adding the output of the AND / OR circuit 45 and the output of the multiplier 43. The latch A46 sequentially latches the odd-numbered harmonic amplitude data accumulated values such as 1, 3, 5, ... In accordance with the latch signal WGL1. Latch B4
7 sequentially latches even-numbered harmonic amplitude data accumulated values such as 2, 4, 6, ... In accordance with the latch signal WGL2.
The AND / OR circuit 45 controls the control signals WGG1, W described later.
The output signal of the latch A46 or the latch B47 is selected according to GG2 and is supplied to the adder 44.

The operation timing will be described later, but the multiplier 43
At the time when the amplitude values of up to 16 harmonics of a channel are output, the accumulated value of the odd-numbered harmonic amplitude data of 1 to 15 is held in the latch A46, and the latch B47 stores 2 The accumulated values of the even-numbered harmonic amplitude data from 1 to 16 are held.

Latch C48 and latch D49 are respectively
The accumulated values of the odd and even harmonics are latched according to the respective latch signals WGL3 and WGL4. When the control signal CCS is 0, the 2's complement device 50 passes the input signal as it is, and when the CCS is 1, the input signal is converted into a 2's complement representation (0 and 1 are inverted and 1 is added). And output. The adder 51 outputs the output of the latch D49 and the 2's complementer 50.
And the output of.

The latch E52 first latches the output of the adder 51 in accordance with the latch signal WGL5 while the CCS is 0, and the output data is written in the waveform memory. Next, the latch E52 latches the output of the adder 51 in accordance with the latch signal WGL5 during the period when CCS is 1, and the output data is written to the address corresponding to the sampling point which is a half cycle away from the waveform memory. With such a configuration, for example, by performing the amplitude value calculation 256 times, 5
Writing to the waveform memory having 12 sample points is completed.

<Phase shift information generator>.

The phase shift information generator 30 and the harmonic coefficient generator 31, which will be described later, have the same circuit configuration, and these require a required sound based on reference data for each range or touch intensity. It forms an interpolator that produces high or touch intensity phase shifts and harmonic coefficient data.

FIG. 6 is a block diagram showing the internal structure of the phase shift information generator 30. First phase shift information memory 30
Both the first and second phase shift information memories 302 are shown in FIG.
It has a memory map as shown in (b). In the first phase shift information memory 301, the reference phase shift data Pa of the range including the depressed key or the intensity range of the depressed key Pa from the CPU 1 via the execution control circuit 20.
Is written.

This reference data is, for example, data corresponding to the lowest pitch in the tone range or the weakest intensity in the intensity range. Second phase shift information memory 302
The reference phase shift data Pb of the next higher pitch range or intensity is written in. These data are stored in the execution control circuit 2
The channel number C starting from 0 and the harmonic order q are read as addresses.

The multiplier 303 is the first phase shift information memory 3
The output Pa of 01 and the output of the complementer 305 are multiplied.
The multiplier 304 outputs the output P of the second phase shift information memory 302.
b is multiplied by the balance signal BL. Complement unit 305
The balance signal BL is converted into a two's complement representation, and (1-B
This is a circuit for outputting L). The adder 306 is both multipliers 3
The outputs of 03 and 304 are added. Therefore, the output phase shift information P is as follows.

P = (1−BL) Pa + BL · Pb.

Here, the balance signal BL will be described. The balance signal BL is an interpolation coefficient signal when interpolation calculation is performed in the phase shift information generator 30 and the harmonic coefficient generator 31, and FIG. 8 shows, for example, the execution control circuit 2
It is a block diagram which shows an example of the balance signal generation circuit by the pitch information in 0.

The input signal BKNo corresponds to the first phase shift information memory 301 of FIG. 6 or the first harmonic coefficient memory 3 of FIG.
It is a key number corresponding to the phase shift or harmonic coefficient information set to 11. The input signal TKNo is shown in FIG.
2 is a key number corresponding to the phase shift or harmonic coefficient information set in the second phase shift information memory 302 or the second harmonic coefficient memory 312 of FIG. CKN
o is the key number of the key that is currently pressed and is to calculate the waveform.

The adder 70 subtracts BKNo from CKNo. Further, the adder 71 subtracts BKNo from TKNo. The divider 72 divides the output of the multiplier 70 by the output of the multiplier 71. Therefore, the following output PBL is obtained at the output of the divider 72.

PBL = (CKNo-BKNo) / (TK
No-BKNo).

Since BKNo is a key number that serves as a reference for the tone range including the depressed key, and TKNo is a reference key number for the tone range that is one level higher than it, BKNo <CK
No <TKNo and the range of PBL is 0 ≦ PBL <1
Becomes

The address decoder 73 converts the PBL into an address in the conversion memory 74. The conversion memory 74 is composed of a plurality of memories 741 to 74n, each of which stores data having different change curves in the range of 0 to 1 as shown in FIG. Outputs a balance signal BL. The decoder 75 outputs a memory selection signal based on the curve selection signal set by the CPU 1 based on the tone color.

In the case of performing the interpolation based on the touch strength, the circuit configuration shown in FIG. 8 may be used, and the input signal only changes to the touch strength. CKTH of the input signal in FIG. 8 is touch strength data of the pressed key, and BKTH is CKTH.
It is data corresponding to the weakest intensity in the intensity range including the value, and TKTH is data corresponding to the weakest intensity in the intensity range one level above.

<Harmonic Coefficient Generator> FIG. 7 is a block diagram showing the internal structure of the harmonic coefficient generator 31. This circuit has the same circuit configuration as that of the phase shift information generator 30 as described above, and includes an interpolation circuit that generates the required harmonic coefficient data based on the reference data for each range or touch intensity. Is forming.

The first harmonic coefficient memory 311 and the second harmonic coefficient memory 312 both have a memory map as shown in FIG. 15 (a). First harmonic coefficient memory 3
The reference harmonic coefficient data of the specified tone color of the tone range including the pressed key or the touch intensity of the touch intensity is written in the CPU 11 from the CPU 1 via the execution control circuit 20, and in the second harmonic coefficient memory 312, The reference harmonic coefficient data of the tone range or touch intensity of the designated tone color is written.

313 and 314 are multipliers, 315 is a complementer which complement-converts BL and outputs (1-BL), 3
16 is an adder. The operation of this circuit is the same as that of the phase shift information generator described above, and outputs the harmonic coefficient data h interpolated based on the balance signal BL.

The phase shift information generator 30 and the harmonic coefficient generator 31 may be used in the following manner as an effect adding circuit in addition to the above interpolation.

For example, different tone color data are set in the first memories 301 and 311 and the second memories 302 and 312 of the phase shift information generator 30 and the harmonic coefficient generator 31, respectively. Then, as the BL signal, for example, the amplitude changes from 0 to 1 at the maximum around 0.5 and 5
If sine wave data (LFO signal) of 0 Hz or less is used,
A so-called LFO effect can be applied.

Alternatively, if a wheel (volume) is provided on the panel section and is manually operated, the BL signal is supplied through a circuit that generates a digital signal in the range of 0 to 1. You can manually and continuously change the timbre.

Therefore, in the BL signal input section of the phase shift information generator 30 and the harmonic coefficient generator 31, the signals from the BL signal generating circuit, the signal from the LFO signal generating circuit, and the wheel as shown in FIG. It is also possible to provide a circuit for switching the signal and the like.

<Formant Coefficient Generator> FIG. 9 is shown in FIG.
3 is a block diagram showing an internal configuration of a formant coefficient generator 32 of FIG. The key number conversion memory 80 is for converting the harmonic order q into the key number HKNo, and the relationship between HKNo and q is as shown in the following equation.

HKNo = 12 · Log 2 (q).

The adder 81 is a key number conversion memory 80.
And the key number KNo of the pressed key are added. The formant envelope generator 82 generates an envelope signal that changes with time according to a key on / off signal and a key number. The multiplier 83 multiplies the output of the formant envelope generator 82 by the depth information set by the CPU 1. This depth information is a depth signal that controls how much the formant envelope signal acts on the read address of the formant coefficient memory 86.

The adder 84 adds the output of the adder 81 and the output of the multiplier 83. The integer part In of this output is input to the address decoder 85, and In and (In + 1) are sequentially output from the address decoder 85 as read addresses of the formant coefficient memory 86.

The formant coefficient memory 86 stores the formant coefficients corresponding to the key numbers as shown in FIG. 12, and according to the address signal from the address decoder 85, the formant coefficient values Fn and Fn.
n + 1 is sequentially output. It should be noted that a plurality of formant characteristic data may be stored in this memory so that the formant characteristic data can be selected according to the tone color, the effect and the like.

The interpolator 87 is a formant coefficient memory 86.
Based on the formant coefficient values Fn and Fn + 1 output from the above and the fractional part fr output from the adder 84, the formant coefficient FS interpolated as in the following equation is output.

FS = Fn + (Fn + 1-Fn) .fr.

The formant coefficient generator 32 operates in synchronization with the harmonic coefficient generator 31, and the same harmonic wave is generated at the timing when the harmonic coefficient generator 31 outputs the harmonic coefficient h of a certain harmonic order. Formant coefficient FS of order
Is output.

FIG. 12 is a conceptual diagram for explaining the operation of the formant coefficient generator 32. In FIG. 12A, the pressed key number is indicated by K. Further, it is assumed that the formant envelope multiplied by the depth value is set so as to generate a waveform as shown in the figure, and the current value is the point A.

At this time, a key number value corresponding to each harmonic order q is sequentially obtained at the output of the adder 84, and the formant coefficient is read from the formant coefficient memory of FIG. 12A by this key number value. And further interpolated to obtain a formant coefficient value FS corresponding to each harmonic order as shown on the right side of the figure.

When time passes and the envelope value reaches, for example, point B in FIG. 12 (b), the key number value as a whole moves upward, and the output formant coefficient value FS also becomes
It changes as shown in the right side of FIG. When the depth value is changed, the level of the formant envelope (overall change range) increases or decreases.

By properly setting the parameters and depth value of the formant envelope generator 82, the characteristics of the fixed formant filter operating on the frequency axis can be changed with time.

<Envelope Generator> FIG. 10 is a block diagram showing the internal structure of the envelope generator. This envelope generator corresponds to the envelope generator 27 of FIG.
The harmonic envelope generator 34 of FIG. 3 and the formant envelope generator 82 of FIG. 9 are applicable.

This envelope generator has four segments (periods corresponding to attack, decay, etc.), target value and speed data of each segment, and CN, RS, and RT flags described later. Is set from the control device (CPU1), a desired envelope is generated.

The parameter / data memory 100 stores various parameters set by the CPU 1 for generating the envelope, the current envelope value, the segment value and the like. The latch F101 has a parameter, the current envelope value read from the data memory 100, the current segment RSG1,
0, latch the repeat request status RPT.

The latch G102 is responsive to the current segment state ASG0,1 based on the output of the latch F101 and the key-on / off data, and the parameter data memory 10
It holds parameters consisting of the target value, speed, and control flag read from 0. Latch H103
Holds the parameter (speed data) of segment 2 in case it is used during the transition from segment 2 to segment 1 during envelope repeat.

The gate 104 blocks the supply of the current value to the arithmetic circuit in response to the input gate signal. The selector C105 responds to the signal from the gate 123 by latching G
The speed data of the segment m from 102 or the speed data of the segment 2 from the latch H103 is selected and supplied to the arithmetic circuit 106.

The arithmetic circuit 106 uses the envelope current value supplied from the gate 104, the target value of the segment m supplied from the latch G102, and the speed data supplied from the selector C to generate a new envelope value at the next time point. Is output to the selector D107, and an arrival signal is generated when the new envelope value reaches or exceeds the target value. Various kinds of arithmetic circuits have been proposed in the past, and arbitrary ones can be applied. Therefore, the internal description will be omitted.

In response to the arrival signal, the selector D107 outputs a new envelope value when it has not arrived and a target value when it has arrived. This output signal is output to the outside and is written in the parameter and data memory 100 as a new envelope current value.

The envelope value is calculated by the above circuit. Next, the control circuit for the segment or the like will be described. The NAND gate 108 outputs 0 when RSG0 and 1 are both 1 (that is, segment 3: key-off state) and when the key is turned on. In FIG. 10, circles at the intersections of the gate input line and other lines indicate that these lines are input to the NAND gate.

The AND gates 109 to 111 set the segment and repeat request state signals to 0 at the time of key-on by the output of the NAND gate 108. AND gate 11
2 sets the repeat request status signal to 0 when the key is turned off. The OR gates 113 and 114 are AN when the key is on.
Although the segment signals output from the D gates 110 and 111 are passed through as they are, the output of the NOT circuit 115 becomes 1 at the time of key-off, so that the output becomes 1 in both cases, indicating the segment 3. The segment signals ASG0, 1 are supplied to the parameter data memory 100 as segment signals (address signals).

Reference numerals 121 and 122 denote NOT circuits. AN
The D-gate 119 has two segments (ASG0 = 0, A
SG1 = 1), the repeat flag RT is 1, and
Further, when the arrival signal is 1 (reached), 1 is output. The AND gate 120 has a segment of 0 or 1.
When the arrival signal is 1, the 1 is output.

The OR gate 118 is an AND gate 119,
If any of the outputs of 120 is 1, 1 is output. The OR gate 117 outputs 1 when either of the outputs of the AND gates 112 and 119 is 1. The adder 125 adds the 2-bit data input from the two inputs A0, 1 and B0, 1 and outputs a new 2-bit segment output WSG0, 1. These output WR
T, WSG0, 1 are new repeat request status signals, and as a segment number, parameters, data memory 1
00 is written.

The NOT circuit 116 is the NAND gate 108.
Invert the output of. The NAND gate 124 outputs 0 when both the output of the NOT circuit and the flag CN held in the latch G102 are 1, and the output of the gate 104 is 0.
To This is to set the envelope initial value at key-on to 0 when CN is 1.

The AND gate 123 has one segment.
(ASG0 = 1, ASG1 = 0), and when the flag RS and the repeat request status signal are both 1, the selector C
1 is output to 105, and the speed data of segment 2 held in the latch H103 is supplied to the arithmetic circuit 106 even though it is segment 1.

Next, transition of segment states will be described. This envelope generator has three flags CN, R
Equipped with T and RS. The CN controls the initial value of the envelope when the key is turned on from the key off (segment 3). RT selects a mode in which segment 1 and segment 2 are alternately repeated during key-on. When the RT is 1, the RS controls whether or not the speed data of the segment 1 is used as the speed data of the segment 1.

FIG. 11 is an envelope waveform diagram showing how the segments transit according to the state of each control flag. First, the flag CN will be described. The envelope generator holds the target value of the segment 3 at the end of the sounding operation in the latch F101 as the current value.

When the flag CN is 0, the output of the NAND gate 124 becomes 1 when the key is turned on, so this value is supplied to the arithmetic circuit 106 as the current value. Therefore, as shown in FIG. 11A, the envelope waveform has the envelope initial value at the time of key-on being the target value of the previous segment 3. If a new allocation is made during the sounding operation, the current value at that time becomes the initial value.

When the flag CN is 1, the output of the NAND gate 124 becomes 0 when the key is turned on, so 0 is supplied to the arithmetic circuit 106 as the current value. Therefore, the envelope waveform starts from 0 as shown in FIG.

Next, the flags RT and RS will be described. FIG. 11C shows an envelope waveform when RT = 0 and CN = 1. AND if the flag RT is 0
The output of gate 119 remains zero. When the key is turned on, the outputs of the AND gate 112 and the OR gates 113 and 114 are all 0. The output of the AND gate 120 is also 0. Therefore, the output of the adder 125 and the OR circuit 117
Will be all zero.

When time passes and the arrival signal from the arithmetic circuit 106 becomes 1, the output of the AND gate 120 becomes 1 and the output of the OR gate 118 also becomes 1. Therefore, the output of the adder also becomes WSG0 = 1 and WSG1 = 0, and the process moves to segment 1.

When the segment signal becomes 1, the parameter, the target value of segment 1, the speed data and the flag are read from the data memory 100 and held in the latch G. Therefore, the arithmetic circuit again starts the arithmetic operation toward the new target value.

When a further time elapses and the arrival signal from the arithmetic circuit 106 becomes 1 again, the output of the AND gate 120 becomes 1 and the output of the OR gate 118 also becomes 1. Since the signal of segment 1 is input to the B0 and 1 terminals of the adder 125, the output of the adder is WSG0 = 0, WSG1.
= 1, and the process moves to segment 2.

After that, since the AND gate 120 does not become 1 even if the arrival signal is generated from the arithmetic circuit, the state of the segment 2 continues, and when the current value reaches the target value of the segment 2, the selector D107 switches, The target value is continuously output. When the key is turned off, the OR circuit 113,
The outputs of 114 both become 1, and the process moves to segment 3.

FIG. 11D shows the envelope waveform when RT = 1 and RS = 0. When RT is 1, it is the same as when RT = 0 until segment 2, but the output of the AND gate 119 becomes 1 when the current value reaches the target value of segment 2. This output is the OR gate 117
Output WRT of 1 and A0 of the adder 125,
Set both inputs to 1.

A segment value of 2 is input to the B0 and 1 inputs of the adder.
, The segment value output from the adder is WSG0 = 1, WSG1 = 0, that is, segment 1
Becomes (Ignore carry.) Therefore, the envelope waveform repeats segment 1 and segment 2 until key-off, as shown in FIG. 11 (d).

FIG. 11 (e) shows the envelope waveform when RT = 1 and RS = 1. When RS is 1, segment 1 and segment 2 are also repeated, but the speed data is different from the above example. When RT is 1, when the target value of the segment 2 is reached, the repeat request status signal RPT is 1, and RS is 1,
The output of the AND gate 123 becomes 1. Then, the selector C105 outputs the speed data of the segment 2 held in the latch H103 to the arithmetic circuit 106.

Therefore, the segment state returns to 1 as in the above example, but the speed data of segment 2 is supplied to the arithmetic circuit. Therefore, the waveform is
As shown in (e), the absolute values of the change rates (gradients) of the waveforms of the segment 2 and the segment 1 after the second time become equal.

The CN flag is segment 0 and RS
Since the flag may be output in the segment 1 and the RT flag may be output in the segment 2, it is not necessary to provide a latch and a signal line separately for each flag, and one signal line may be used in a time division manner. The number of segments may be 5 or more.

<Operation Timing> FIG. 13 (a) is shown in FIG.
5 is a time chart showing an outline of operation timings of the harmonic information generation unit 21 and the waveform calculation unit 22 of FIG. In the figure, the channel number is the number of a channel that independently generates a musical sound, and in this example, exists from 1 to 16. W means write and R means read.

During the calculation period of the channel 1, the harmonic information generating unit 21 as shown in FIG. 3 is based on various information such as the harmonic coefficient and phase shift set by the CPU 1.
The phase shift information P and the harmonic coefficient H of each harmonic of the tone of channel 1 are calculated, and the harmonic memory 36 shown in FIG.
, For example, in area A.

During the calculation period of channel 2, the harmonic information generation unit 21 writes the data of channel 2 in the B area of the harmonic memory, while the waveform calculation unit 22 reads the data of channel 1 from the area A, By the method as described above, the amplitude value at each sample point of the waveform is obtained and written in the waveform memory 23.

As described above, the harmonic memory 36 alternately uses the two areas to sequentially transfer the data for 16 channels, and the waveform memory 23 switches the areas when all the waveform data for 16 channels are prepared. , The waveform is updated.

FIG. 13B is a time chart showing an outline of the operation timing of the waveform calculation section 22. The write cycle to the waveform memory 23 is divided into the number of channels (16), and the calculation period of one channel is divided into 256 sample point calculation periods. The word number in the figure is the number (address) of the waveform data stored in the waveform memory. Furthermore, the calculation cycle of each sample point is
It is divided into 16 harmonic amplitude calculation periods.

The calculation time for one harmonic amplitude value is, for example, 1
If it is 25 nanoseconds, one sample point calculation time (actually two sample point data can be obtained) is 2 microseconds, and one channel waveform data calculation time is 512 microseconds. Therefore, the period for calculating the waveforms of all 16 channels and updating the waveforms is about 8.2 milliseconds.

FIG. 14 is a time chart showing the operation of the waveform calculator 22 of FIG. The waveform calculation unit 22 is a circuit that requires the fastest calculation, and the multiplier 43 of FIG. 4 outputs the amplitude value of each harmonic at a period of 125 microseconds, for example, as shown in FIG. 13B. Is coming.

The signal WGG1 is a gate signal for accumulating odd-numbered harmonics, and becomes 1 at the timing of odd-numbered harmonics other than the first harmonic. WGG2 is a gate signal for accumulating even harmonics, and becomes 1 at the timing of even harmonics other than the second harmonic. WGL1, WGL
Reference numerals 2 are latch pulses of the odd harmonic cumulative value latch A46 and the even harmonic cumulative value latch B47, respectively. Each latch circuit latches the input signal at the rising edge of the latch pulse.

Therefore, the accumulated values of the odd harmonics and the even harmonics are sequentially latched in the latches A and B as shown in the figure. Then, at the end of the n-word operation period, the accumulated value On of the odd harmonics 1 to 15 is stored in the latch A.
However, the accumulated value En of even harmonics from 2 to 16 is latched in the latch B.

WGL3 and WGL4 are pulses for latching the outputs of the latch A and the latch B in the latch C and the latch D at the timings shown in the figure. The outputs of the latches C and D hold the accumulated values of odd and even harmonics as shown.

The signal CCS controls the operation of the complementer 50. When the CCS is 0, the complementer 50 passes the input signal as it is, and when the CCS is 1, the input signal is represented by 2's complement. To 0 (invert 0 and 1 and add 1) and output. Therefore, during the period when CCS is 0, the outputs of the latch C and the latch D are directly added by the adder 51 to output (On + En), and during the period when CCS is 1, (-On + En) is output.

WGL5 is a pulse for the latch E to latch the output of the adder 51 immediately before CCS changes. In the output of the latch E, (On + En) and (-On + En) appear in order as shown in the figure. This (-On + E
As described with reference to FIG. 16, the n) value becomes the value of the sample point which is a half cycle (address 256) ahead of the basic cycle in the waveform memory.

Therefore, according to the write address of the waveform memory supplied from the execution control circuit 20, (On + En)
The value is written to address n, and the (-On + En) value is (n +
256) Address is written. Note that W in the bottom row of FIG. 14 is an address value for a half cycle of the basic cycle, which is 256 in this example.

<Processing at Key-On> Finally, the operation of the CPU 1 at key-on will be described. CPU1 is RO
The keyboard and panel are constantly scanned according to the program stored in M2, and when any key is pressed, this is detected, a vacant channel is searched for, and a tone corresponding to the key is generated. Determine the channel to use.

Next, the CPU 1 sets various data in each circuit of the harmonic generating section 21. First, the tone range or touch intensity including the pressed key and the phase shift information of the tone range or touch intensity one level above it are read from the ROM 2,
It is set in the two phase shift information memories 301 and 302 in the phase shift information generator 30.

Next, the tone range or touch intensity including the pressed key and the harmonic coefficient data of the tone range or touch intensity one level higher than the tone range corresponding to the designated tone color are stored in the ROM 2.
Read out from and set in the two harmonic coefficient memories 311 and 312 in the harmonic coefficient generator 31.

A key number and depth information are set in the formant coefficient generator 32, and a target value and speed data of each segment are set in the formant envelope generator 32. Envelope information for each harmonic is set in the harmonic envelope generator 34 in order to change the timbre with the passage of time.

Further, in the balance signal generating circuit in the execution control circuit 20, the pressed key and the reference key numbers above and below or the touch strength are set. With these settings, the harmonic information generator and the waveform calculator automatically calculate the waveform and output the waveform to the waveform memory at a period of, for example, about 8.2 mm.

The CPU 1 also sets a key number in the waveform reading circuit 24 and sets envelope information in the envelope generator 27, as in the normal waveform reading method. These circuits read waveform data from the waveform memory at an address interval corresponding to the key number by a known method and multiply the envelope data by the envelope signal to generate a tone signal.

Although the embodiments have been described above, the following modifications are also possible. Since the phase shift information generator and the harmonic coefficient generator have the same circuit configuration, they can be realized by one circuit by performing time division multiplexing processing.

[0132]

As described above, according to the electronic musical instrument of the present invention, it is possible to select the speed data of the segment to be repeated in the envelope generator. When an LFO-like effect is added to a certain musical sound, there is an effect that a natural envelope change can be obtained.

Since the speed data of a specific segment is used, the memory amount does not increase. In addition, whether or not to repeat, or to select speed data at the time of repetition, sets a flag /
Since control can be performed by resetting, control becomes simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of an electronic musical instrument.

FIG. 2 is a block diagram showing an internal configuration of a tone generation circuit 6.

FIG. 3 is a block diagram showing an internal configuration of a harmonic information generation unit 21.

FIG. 4 is a block diagram showing an internal configuration of a waveform calculation unit 22.

5 is a block diagram showing an internal configuration of an accumulator 40. FIG.

FIG. 6 is a block diagram showing an internal configuration of a phase shift information generator 30.

7 is a block diagram showing an internal configuration of a harmonic coefficient generator 31. FIG.

FIG. 8 is a block diagram showing an example of a balance signal generation circuit.

9 is a block diagram showing a configuration of a formant coefficient generator 32. FIG.

FIG. 10 is a block diagram showing an internal configuration of an envelope generator.

FIG. 11 is a waveform diagram showing an envelope waveform.

FIG. 12 is a conceptual diagram for explaining the operation of the formant coefficient generator.

FIG. 13 is a time chart showing the operation timing of the musical sound generating unit.

FIG. 14 is a time chart showing the operation timing of the waveform calculation unit.

FIG. 15 is an explanatory diagram showing an example of a memory map of various memories.

FIG. 16 is a conceptual diagram showing how to obtain amplitude values of two sampling points of a phase-shifted harmonic.

[Explanation of symbols]

1 ... CPU, 2 ... ROM, 3 ... RAM, 4 ... Keyboard section, 5 ... Panel section, 6 ... Musical sound generating section, 7 ... D / A converter, 8 ... Analog signal processing section, 9 ... Amplifier, 10 ... Speaker , 11 ... Bus, 20 ... Execution control circuit, 21 ... Harmonic information generation section, 22 ... Waveform calculation section, 23 ... Waveform memory, 2
4 ... Waveform readout circuit, 25 ... Selector, 26 ... Waveform interpolation circuit, 27 ... Envelope generator, 28 ... Multiplier

Claims (2)

[Claims] 1. An electronic musical instrument having an envelope generator, wherein the envelope generator stores an envelope generation data of each segment, and an envelope value and a corresponding value based on the data read from the storage unit. Arithmetic means for sequentially calculating the arrival signal output when the target value of the segment is reached and outputting to the external and the storage means, based on the data read from the storage means and the arrival signal, When the condition is satisfied, a control unit that repeats transition between specific segments, and a specific one of the plurality of speed data read from the storage unit based on the data read from the storage unit is selected. An electronic musical instrument, comprising: selecting means for selecting and outputting to the calculating means. 2. The electronic musical instrument according to claim 1, wherein the selecting means includes a holding means for holding speed data of a specific segment.