JP2914137B2 - Time division multiplex switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex switch, and more particularly to a T1 stage time division multiplex switch.

[0002]

2. Description of the Related Art A T1-stage time division multiplex switch is a so-called complete group of switches and has a feature that software control is easy. As a basic configuration, a write to memory by multiplexing all the time slots in the input Haiwe Lee having a frame structure, to achieve replacement function time slots (time switch function) by controlling the readout order of the output highways I have. That is, one frame period (125 μs in the case of a 64 Kbps exchange operation)
It is necessary to write and read the time slots corresponding to the switch multiplicity in the memory in c), and it is necessary to increase the memory operation speed as the multiplicity increases. 125 μs even if the memory is double buffered
If the multiplicity N = 8192 in the ec cycle, a memory operation speed (cycle time) of 15 nsec is required if the multiplicity N is 16384, and if the multiplicity N is 16384, a memory operation speed (cycle time) of 7.5 nsec is required. The limit of the multiplicity is determined by the speed of the memory device. Would.

As a conventional example for solving this problem, as shown in FIG. 3, a plurality (k) of time switches (TSW) 80 are provided for each of input highway groups (IHW) 11-1i.
Are connected to each other, and each TSW8 is connected by a selector (SEL) 90.
There is a configuration in which an output highway group of 0 is selected in a time-sharing manner and each of the output highway groups (OHW) 71 to 7k is output. Here, the multiplicity of the input highway and the output highway are the same (i.e., i = k), and if the multiplicity is N, the multiplicity of each TSW 80 is N / i. Therefore, the operation speed as a memory is reduced to 1 / i.

[0004]

The problem with the conventional time division multiplex switch is that the number of input highways × the number of output highways, i.e., i.times.i, is required for the number of time switches (TSW) in order to reduce the memory speed. It is in. That is, when trying to increase the multiplicity N at a constant memory operation speed,
There is a problem that the number of TSWs increases in proportion to the square of the multiplicity.

[0005]

SUMMARY OF THE INVENTION According to the present invention, a plurality of input highways each consisting of a periodic frame having a plurality of time slots are replaced with data between arbitrary time slots as a plurality of output highways. In the time division multiplexing switch for outputting,
Preset vans for each of multiple input highways
Virtual multi-cycle with multiple frames as many cycles
Assuming a frame configuration, for each virtual multi-frame
Frame at the specified frame position over all input highways.
One input highway in a multi-frame configuration
Editing to iBank is a virtual multi-frame
For all positions while sequentially changing the predetermined frame position for each system
Repeatedly, duplicate the number of banks set in advance.
And editing means for generating a number of input highways banks, a plurality of time switches and said plurality of input highways bank of each time slot position said multiframe period in each replacement plurality of output highways banks, before
Each of the multiple output highway banks has
Select a frame at a predetermined frame position for each frame
To reverse the output highway in one frame cycle
Collecting a predetermined frame for each of the multi-frames.
Repeat for all positions while sequentially changing the position,
Reverse editing means for generating a number of output highways .

Further, in the above configuration, the editing means has first selecting means for alternatively connecting the plurality of input highways to the plurality of input highway banks, respectively. And a frame is sequentially selected by shifting the phase by one frame at a time for each frame period, and a plurality of multi-frames having a cycle of frames corresponding to the number of the input highways are formed for the number of the plurality of input highways. A bank, wherein the reverse editing means includes second selecting means for alternatively connecting the plurality of output highway banks to the plurality of output highways, respectively, wherein the multi-frame of each of the plurality of output highway banks is provided. From each other, the phase is shifted one frame at a time for each frame, and the frames are sequentially selected. It can be respectively decomposing configuration to said plurality of output highways corresponding frame.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Each of the input highways (IHW) 11-1i is a selector (SEL) of the multi-frame editing unit (CNV) 20.
The frames are selected one by one by
Multi-frame input highway bank (IBAN
K) Edited to 31 to 3j. Here, the number of banks j is
Equal to the number of multi-frames . IBANK31-
3j receive time slots (time switch operation) at the time switches (TSW) 41 to 4j, respectively, and are output from the TSWs 41 to 4j as output highway banks (OBANK) 51 to 5j. Each TSW41-
4j is a communication path memory (SPM) 41 as shown in FIG.
0, a read control memory (SCM) 420, and an address counter (CNT) 430. OBAN
K51 to 5j are multi-frame reverse editing units (D
CNV) 60 of the selector (SEL) 1 off at 61~6k
Is selected by frame, the output highways (OHW). 71 to
Edited to 7k.

Next, the operation will be described. FIG. 4 is a highway time slot timing diagram for simplifying and explaining the operation of the embodiment of FIG. 1 with i = j = k = 4. Here, one frame is composed of eight time slots. Further, since j = 4, the TSWs 41 to 4j operate in four multiframes. IHW11-
14 constitutes one frame with eight time slots as shown in FIG. 4A, but the CNV 20 operates assuming that this is a highway having a four multi-frame structure. Also,
It is assumed that the phases of the multi-frame are shifted one by one among the IHWs 11 to 14. Then, as shown in FIG.
Each SEL 21 to 24 of V20 is a temporary
Ties belonging to the same frame position in a imaginary multiframe
System slots in sequence, and four 4-multiframe structures
And outputs the highway bank (IBANK) 31~34 adult. As is clear from FIGS. 4A and 4B, SEL
The operations 21 to 24 are performed in IHW 11 to 14 in one frame cycle.
Simply select them in order. The TSWs 41 to 44 exchange time slots at four multiframe periods for the input IBANKs 31 to 34. FIG. 4 (b)
Has a time slot # 1 of the IHW11 (data A1,
A2, A3, A4, ...) and IHW4 time slot #
7 (data D1, D2, D3, D4...) Are exchanged, and the result of the exchange is shown in FIG. The time slot exchange operation in the TSWs 41 to 44 is the same except that the start position of the multiframe is shifted. That is, the contents of the read control memories (SCM) of the TSWs 41 to 44 are all the same. FIG. 4 (c),
As shown in (d), SEL61 to SEL6 in DCNV60 are used.
4 is O after time slot exchange like CNV20.
BANKs 51 to 54 are sequentially selected for each frame and output as OHWs 71 to 74. By the above,
The operation of exchanging (exchanging) the time slot # 1 of the IHW 11 with the time slot # 7 of the IHW 14 is realized.

In this embodiment, the IHWs 11 to 1j,
Although each of the OHWs 71 to 7j has been described as having one highway configuration, it is needless to say that the OHWs 71 to 7j can be configured with a plurality of highways.

[0011]

According to the present invention, each time switch (TS)
The multiplicity N of W) is equal to the multiplicity N of the entire time division multiplex switch. However, since the switch operation cycle of each TSW is multi-framed with a plurality of (j) frame cycles, the operation speed of the memory operation is proportional to N / j. In other words, by multi-frame,
It is possible to reduce the operation speed of each TSW. In this case, the number of TSWs also increases, but is only proportional to j, and does not increase by the square as in the conventional example. Therefore, according to the present invention, it is possible to realize a high-multiplex time-division multiplex switch more compactly than before using a relatively low-speed TSW.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a time switch (TSW) of the embodiment of FIG.

FIG. 3 is a block diagram showing a conventional time division multiplex switch.

FIG. 4 is a timing chart of a highway time slot for explaining the operation of the present invention. FIG. 4 (a) is an input highway format, FIG. 4 (b) is a highway format after multiframe conversion, and FIG. ) Shows the highway format after the exchange of time slots, and (d) shows the output highway format.

[Explanation of symbols]

 11,..., 1j Input highway (IHW) 20 Multi-frame editing unit (CNV) 41,.

Claims (2)

(57) [Claims] 1. A time division multiplexing switch for switching data between arbitrary time slots of a plurality of input highways each composed of a periodic frame having a plurality of time slots and outputting the data as a plurality of output highways, Each of the input highways of one frame cycle is
Multiple frames for the number of banks set in advance
Virtual multi-frame configuration
Frame at a predetermined frame position for each
Multi-frame configuration by multiplexing over all input highways
Editing one input highway bank of the
Predetermined frame position for each virtual multi-frame
Repeat for all positions while changing
Generate multiple input highway banks for the specified number of banks
And editing means for a plurality of time switches and said plurality of input highways bank of each time slot position said multiframe period in each replacement plurality of output highways banks, each circle from each of said plurality of output highways bank
Frame at the specified frame position for each
Select to reverse to the output highway for one frame period
Editing is performed according to the predetermined frame
Repeat for all positions while sequentially changing the
A time-division multiplex switch, comprising: reverse editing means for generating a plurality of output highways . 2. The method according to claim 1, wherein the editing unit includes a first selection unit configured to selectively connect the plurality of input highways to the plurality of input highway banks. A plurality of input highways corresponding to the plurality of input highways are formed, and a plurality of frames having a period corresponding to the number of the input highways are formed as the plurality of input highways. Reverse editing means having second selection means for selectively connecting the plurality of output highway banks to the plurality of output highways, respectively; The phase is shifted one frame at a time from one frame to another and sequentially selected, and the plurality of output high 2. The time division multiplex switch according to claim 1, wherein the switch is decomposed into frames corresponding to ways.