JPH03106149A - Tdm-pkt conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the delay in conversion at a fast data speed and to reduce the quantity of buffer by switching a storage plane of a double buffer for storing signals on a time division multiplex bus where data of a different speed exist in mixture at the switching speed corresponding to each data speed. CONSTITUTION:A write control section 1 switches storage planes at write in buffers 31, 32 at a switching speed in response to the line speed and writes a data on a TDM bus to a relevant area of a selected buffer in response to line number information of a time division multiplex(TDM) control section 4. Moreover, a readout control section 2 selects storage planes for readout of the buffers 31, 32 in response to the line speed and reads out a prescribed quantity of th data in an area corresponding to the buffers in response to the line number from a packet(PKT) control section 5. Thus, the required buffer capacity is reduced and the conversion delay is decreased.

Description

[Detailed Description of the Invention] [Summary] TDM- for converting time division multiplexed data into packets
Regarding PKT conversion circuits, we have developed TDM-P, which converts TDM bus signals to PKT data, with the aim of reducing the required buffer capacity and conversion delay.
In the KT conversion circuit, there is a two-sided buffer having a storage area for each line number, a TDM control unit that holds line number information and line speed information corresponding to each line position on the TDM bus, and a TDM control unit that holds line number information and line speed information corresponding to each line position on the TDM bus. A write control unit that switches the writing side of the buffer at the switching speed and writes data on the TDM bus to the corresponding area of the switched buffer according to line number information, and a frame address and line number on the PKT receiving side. and a readout control unit that switches the readout side of the buffer according to the line speed and reads the required amount of data from the corresponding area of the buffer according to the line number. , by forming a packet from the read data of each line.

[Industrial application field]

The present invention relates to a device that connects a medium-low speed line interface terminal that is baseband-connected to a device that communicates using fixed-length packets, such as a high-speed, large-capacity LAN, and particularly relates to a device that connects a medium-low speed line interface terminal to a device that communicates using fixed-length packets, such as a high-speed, large-capacity LAN. TDM-PKT enables efficient conversion of data at each speed into packets when converting (TDM) data to packet (PKT) data.
This relates to conversion circuits.

In recent years, there has been an increase in the number of devices such as high-speed, large-capacity LANs that use packet communication as their backbone systems. However, in order to efficiently multiplex and accommodate medium- and low-speed line data for synchronous continuous communication, the TDM method is often used.

Therefore, it is desired to be able to efficiently packetize a TDM bus, in which multiple lines are time-division multiplexed at various speeds, for each line.

[Conventional technology]

Conventionally, packetization of TDM data when lines of different speeds coexist has been difficult to process when TDM bus low-speed data (e.g. 64k
This was done by switching the double bass sofa at certain intervals according to the speed (bps).

FIG. 6 shows a conventional TDM-PKT conversion circuit.

In FIG. 6, from terminals DTEI to DTEn? The data on the TDM bus 11, which is time-division multiplexed data, is transferred to a switch 12 which is switched at a certain period according to a control signal.
Buffer memory 141.14 to avoid double buffering after 13! PKT data is generated at the output by alternately writing and reading data. In this case, if low-speed data and medium-speed data are mixed on the TDM bus 11, the buffer memories 141.14■ will be switched in accordance with the synchronization of the low-speed data, but the buffer memory capacity will be It must be compatible with medium-speed data.

Such buffers are required as many as the number of lines accommodated in the device.

Therefore, overall, a buffer capacity of (number of lines to accommodate x amount of medium-speed data) is required, which not only increases the buffer capacity, but also increases the delay time of packet conversion for medium-speed data. Become.

[Problem to be solved by the invention] As described above, in the conventional TDM-PKT conversion circuit, T
When low-speed data and medium-speed data are mixed on the DM bus, the double buffer is switched according to the synchronization of the low-speed data, so the buffer capacity increases according to the amount of medium-speed data, and There was a problem in that the conversion delay for medium-speed data became large.

The present invention is an attempt to solve the problems of the prior art as described above, and is aimed at packetizing data on a TDM bus in which low-speed data and medium-speed data coexist. The purpose of this technology is to reduce the required buffer capacity and conversion delay by switching the sides of the double buffer for multiplexed data at each speed at a switching speed that matches the speed of each channel. There is.

[Means for Solving the Problem] As shown in the principle configuration of FIG. 1, the present invention is a TDM bus that converts signals of a TDM bus accommodating a plurality of lines having various line speeds into PKT data. In the PKTi exchange circuit, two-sided buffers 31.3. And TDM! I1 control section 4, write control section l, ? It includes a KT control section 5 and a readout control section 2, and forms a packet from the read data of each line.

Here, two buffers 3, . 3) has a storage area for each line number. The TDM control unit 4
It holds line number information and line speed information corresponding to each line position on the M bus, and the write control unit '1 writes the buffer 3, the line speed information at a switching speed according to the line speed.
In addition to switching the writing side in 3■,
Control is performed to write data on the TDM path into the corresponding area of the switched buffer in accordance with the line number information of the TDM control unit 4.

The PKT control section 5 also holds correspondence information between frame addresses and line numbers on the PKT receiving side, and the readout control section 2 controls the buffers 3, . 3.

At the same time as switching the readout side of
It controls reading out the required amount of data from the corresponding area of the buffer in accordance with the line number from the T control unit 5.

? Effect] FIG. 2 is a diagram for explaining the effect of the present invention,
A TDM/PKT converter is shown that converts DM data into packets. In the same figure, transmission buffer 23■2
3■ represents buffer 3+. in the claims, respectively. 3t, the transmission TDM switch 22 and the transmission buffer write control section 24 correspond to the write control section 1, and the TDM control section 25 corresponds to the TDM control section 4.

Further, the transmission PKT switch 26 and the transmission buffer read control section 27 correspond to the read control section 2, and the PKT control section 28 corresponds to the read control section 5.

The TDM bus 21 has multiple terminals DTEI, DTE2,...
1. Data of each channel from DTEn is multiplexed. The transmission TDM switch 22 controls the transmission buffers 23 .
．． 23■ In addition to switching the sides to write alternately,
Is this TDM data the designated channel CH in the switched transmission buffer? ~Write to the specified address in CHn. At this time, the transmission buffer write control unit 24 controls the transmission buffers 23, . 23
．． In addition to controlling the writing in the memory, it also controls the generation of write addresses.

The TDM control section 25 holds time slot position information and line speed information on the TDM bus 21 of each channel and outputs it to the transmission TDM switch 22 and transmission buffer write control section 24, thereby controlling the transmission buffer. 23,. Writing is performed to 23■ by specifying an address for each channel. in this case,
By writing at individual speeds for each channel, you can write at different speeds (e.g. 64kbps and below and 64kbps and below).
4 kbpsX n (where n is an integer).

The transmission PKT switch 26 controls the transmission buffer 23■2 based on the control of the transmission buffer read control section 27.
3) The planes to be read out are alternately switched from (1) onwards, and packets are read out from the switched transmission buffer within the prescribed period of each channel. send? At this time, the buffer read control unit 27 controls the transmission buffer 23 . ．． In addition to controlling the reading in step 23 (2), it also controls the generation of the read address.

At this time, by setting the channel number corresponding to the frame address of the packet receiving side in the PKT control unit 28, the transmission PKT switch 26 and the transmission buffer read control unit 27 reads out data from the transmission buffer for each channel and sends it to a multiplexing (MUX) unit (not shown).

〔Example〕

FIG. 3 shows an embodiment of the present invention, in which TDM data is collected from a plurality of line interface terminals, packetized, and connected to a high-speed line.
The specific structure of the DM/PKT converter is shown in a block diagram. In the figure, buffer memory 30. ,3
0g is buffer 31.3 in the claims
Corresponding to ■, the TDM control memory 31 is TDM
To control section 4? Accordingly, the PKT control memory 4l corresponds to the PKT control section 5. Also, the time stamp counter 32. Transmission buffer write control section 33,
Write address generation section 34, surface switching mode section 35,
Selector 36, gate 37■37z, 3-state buffer 38. ．． 3B■ corresponds to the write control section 1 {this corresponds to a frame counter 42, a transmission buffer read control section 43, a read address generation section 44, a plane switching mode section 45, a selector 46, a gate 47■47■. The 3-state buffer 481.48■ corresponds to the read control section 2.

In FIG. 3, buffer memories 30, . 30t is random access memory (RA
M). TDM control memory 31
corresponds to the TDM address that indicates the time slot position on the TDM line, and contains channel number information, group information that indicates the screen switching cycle of each channel, and whether each time slot is in use (USD) or unused. It has information indicating.

Is the time slot counter 32 a TDM address? It also generates timing signals used in each block. The transmission buffer write control unit 33 is a TDM
The write address generator 34 and the batza memories 30, .
30. Supply light pulses to.

The write address generation section 34 has an address of the buffer memory 30*30* for each channel, and counts up the write pulse of the corresponding channel in response to the write pulse from the transmission buffer write control section 33.
Generates a write address.

Further, the screen switching mode unit 35 controls switching in the selector 36 according to group information from the TDM control memory 31. The selector 36 thereby selects four types of surface switching clocks (2 msecCLκ
+ 4msecCLK, 8msecCLK, 16m
secCLK) and outputs it.

The gates 371.37■ write the clock output from the selector 36 and the enable timing signal WET? 3-state buffer 381, 381 according to the data SDTO from the TDM bus.
~7 corresponds to the period of the surface switching clock in the buffer memory 30■30. are input alternately.

The selector 39 receives a write/read switching signal R.
/W, the buffer memory 30+. 30z is controlled so that writing and reading are performed alternately.

This allows the buffer memory 30. , 302 transfers TDM data to the buffer on the write side in response to the write pulse from the TDM control memory 31 and the write address from the write address generation unit 34 while performing surface switching at a periodicity for each group. is written for each channel separately.

The PKT control memory 41 stores the frame address corresponding to the packet classification on the packet receiving side, and the buffer memory 30 . ,30. It has information on the correspondence between the data stored in the channel number and the channel number. This correspondence relationship is determined in accordance with the speed of each channel so that faster data has higher priority.

Frame counter 42 generates a frame address. The transmission buffer read control section 43 receives the channel number corresponding to the frame address from the PKT control memory 41, and supplies a read pulse to the read address generation section 44 and the buffer memory 301302.

The read address generation section 44 has an address of the buffer memory 30.302 for each channel corresponding to each frame address, and the transmission panfariate control section 43
A read address for the corresponding packet is generated in response to a read pulse from. This read address is supplied via the selector 39 to the buffer memory on the read side.

Further, the plane switching mode section 45 controls switching in the selector 46 according to speed information from the PKT control memory 41. The selector 46 thereby
4 types of surface switching clocks (2msecLK+
4msecCLK, 8msecCLκ. 16lll
secCLK)? Select and output.

Gate 47. ．． 47■ supplies the cross output from the selector 46 to one of the three-state vanofers 48, 48■ in accordance with the read enable tying signal RETM. As a result, data from the backup memory on the read side is
According to the read pulse from the PKT control memory 4l and the read address from the read address generation section 44, it is output in units of frames for each channel and sent to a MUX section (not shown).

The MUX section adds a header section to this data and sends out the page notes.

An example of allocation of each channel in the TDM control memory and the PKT control memory will be described below.

In this case, the data rate of each channel is CH0,
1.4-11. 14-23 is 64kbps or less, CH
2 is 128 kbps, CH3 is 256k
bps, CHI2 is 768kbps, CH2
4 is 1 5 3 6 kbps, C H13 and C
It has not been used since H25.

FIG. 4 shows an example of the contents of the TDM control memory, and shows a TDM control memory consisting of 64 time slots.
Indicates the assignment of each channel to one frame of data on the bus, and each time slot address TSONTS6
3, each channel CHO-CH24 is assigned to occupy a number of time slots according to the data rate indicated by groups 00-11, and
It is shown that time slots in use (tJsD) are indicated by l, and unused time slots are indicated by 0.

FIG. 5 shows an example of the contents of the PKT control memory, in which each channel is assigned to the frame address SFO-SF63 on the packet receiving side, and the time slot in use (USD) is is shown as 1, and unused time slots are shown as 0. In this case, the 64 frames are divided into 8 sections, and channel numbers are given preferentially to allocate the fastest data to each section, starting with the fastest data. The packets are sent out in a time-distributed manner to further reduce the packet conversion delay for high-speed data.

〔Effect of the invention〕

As explained above, according to the present invention, the amount of buffer is reduced by performing double huffer switching of signals on a time division multiplexed bus in which data of different speeds coexist at a switching speed corresponding to the speed of each data. At the same time, conversion delay in high-speed data can be reduced. Furthermore, by reading out faster data in a temporally distributed manner, the conversion delay can be further reduced.

Therefore, according to the present invention, data at various speeds on the special division multiplex bus can be efficiently packetized for each line.

[Brief explanation of drawings]

Figure 1 is a diagram showing the principle structure of the present invention, Figure 2 is a diagram for explaining the operation of the present invention, and Figure 3 is a book? FIG. 4 is a diagram showing an example of the contents of a TDM control memory, FIG. 5 is a diagram showing an example of contents of a PKT control memory, and FIG. 6 is a diagram showing an example of the contents of a conventional TDM-PKT control memory.
FIG. 3 is a diagram showing a conversion circuit. 1 is a write control section, 2 is a read control section, 3.3 is a buffer, 4 is a TDM control section, and 5 is a PKT control section. Patent applicant Fujitsu Limited

Claims (1)

[Scope of Claims] (I) TDM-PKT that converts signals of a time division multiplexing (hereinafter abbreviated as TDM) bus that accommodates multiple lines having various line speeds into packet (hereinafter abbreviated as PKT) data.
In the conversion circuit, a two-sided buffer (3_
1, 3_2), a TDM control unit (4) that holds line number information and line speed information corresponding to each line position on the TDM bus, and a buffer (3_1) that maintains line number information and line speed information corresponding to each line position on the TDM bus.
, 3_2), and writes the data on the TDM bus to the corresponding area of the switched buffer according to the line number information, and the frame on the PKT receiving side. A PKT control unit (5) that holds correspondence information between an address and the line number, and a PKT control unit (5) that holds correspondence information between the address and the line number, and the buffer (3_1, 3
A readout control unit (2) that performs side switching on the readout side in _2) and reads out a required amount of data from a corresponding area of the buffer according to the line number, A TDM-PKT conversion circuit characterized by forming a TDM-PKT conversion circuit. (II) The TDM-PKT conversion circuit according to claim 1, wherein the read control unit (2) reads data of each line from the buffer (3_1, 3_2) with priority according to line speed. .