JPH03109841A - Time division multiplex data packet conversion circuit - Google Patents

Abstract

PURPOSE:To decrease a data storage time for packet-processing a line data of the same destination and same speed and to decrease conversion delay by handling plural lines communicating with a same opposite party equipment as a single line and applying multiplex and packet-processing to the data. CONSTITUTION:A time division multiplex data/packet conversion section 10 is provided with a 1st channel number rewrite section 3, which rewrites each channel number of a channel having the same destination and same speed read by a 1st data storage means 1 into the same channel number. Moreover, a packet/time division multiplex data conversion section 20 is provided with a 2nd channel number rewrite section 4, which rewrites the same channel number rewritten by the 1st channel number rewrite means 3 into each original channel number. Thus, data of same speed having same destination are multiplexed and processed into packets to reduce the data storage time for packet processing thereby reducing the packet conversion delay.

Description

[Detailed Description of the Invention] [Summary] The purpose of the present invention is to provide a time division multiplexed data-to-packet conversion circuit that can reduce conversion delay with respect to a circuit that performs mutual conversion between time division multiplexed data and packets. a time-division multiplex data/packet converter that reads and packetizes time-division multiplex data written for each channel in the first data storage means according to correspondence relationship information between the input packet information and the channel number; A time-division multiplex data-packet converter comprising a packet/time-division multiplex data converter that reads data written to the data storage means for each channel and creates time-division multiplex data according to the correspondence information between time slots and channel numbers. In the circuit, a first channel number rewriting means rewrites the numbers of channels having the same destination and the same speed written in the first data storage means to the same channel number, and and second channel number rewriting means for rewriting the same channel number to the original channel number.

[Industrial application field]

The present invention provides time division multiplexed (TDM) data and packet (P
This circuit is used for accommodating terminal equipment that handles time division multiplexed data in equipment that performs fixed-length packet communication, such as high-speed, large-capacity LAN, etc. The present invention relates to a division/multiplex data/packet conversion circuit.

In recent years, an increasing number of devices have adopted packet communication in core systems such as high-speed, large-capacity LANs. Packet communication is suitable for communication between terminal devices that does not require immediacy, such as voice conversation, and can improve the efficiency of using transmission paths.

On the other hand, the time division multiplex communication method accommodates multiple terminal devices on a transmission path and communicates using time division multiplexed data.
It is possible to efficiently multiplex and accommodate medium and low speed data that performs synchronous continuous communication.

In this way, each of the two communication systems has different features and is used in combination depending on the purpose, but it is necessary to be able to connect the two communication systems with each other, and for this purpose, time division multiplexing is required. There is a need for a time-division multiplex data/packet converter circuit that can efficiently convert between data and packets.

[Prior Art] FIG. 5 shows a conventional time division multiplexed data/packet conversion circuit, which includes a time division multiplexed data/packet conversion section 10 that converts time division multiplexed data into packets, and a time division multiplexed data/packet conversion section 10 that converts time division multiplexed data into packets. A packet/time division multiplex data conversion unit 20 that converts into division multiplexed data, and a TDM counter 30 that creates control information regarding the TDM bus 100 based on information regarding the position of each channel on the TDM bus 100.
It consists of a control section 40.

The time division multiplexed data/packet converter 10 includes a transmission TDM switch 11 that distributes TDM data by channel and inputs it to a transmission panzer memory 12, and a transmission buffer memory 12 that has an area for storing time division multiplexed data corresponding to each channel. and transmit buffer memory 12 for each channel.
a transmitting PKT switch 13 that reads the data stored in the transmitting PKT switch 13; a multiplexing unit 14 that creates a packet by adding a header section from the packet header section 17 to the data output from the transmitting PKT switch 13; a transmission buffer write control section 15 that controls writing of data, and a transmission buffer read control section 16 that controls reading of data from the transmission buffer memory 12.
, a packet header section 17 that creates a header section consisting of control information such as the destination of the packet I, and a transmission buffer memo 1.
It consists of a transmission packet determination unit that reads data from month 2 and determines its priority order.

The packet/time division multiplex data conversion unit 20 includes a separation unit 2 that separates an information part and a header part included in a received packet.
1, and a reception PKT switch 2 that distributes the data of this information section by channel and inputs it to the reception buffer memory 23.
2, a reception buffer memory 23 having an area for storing packet data corresponding to each channel, and a reception TD that reads data stored in the reception buffer memory 23 for each channel.
M switch 24 , a receive packet header processing unit 25 that analyzes headers in received packets, a receive buffer write control unit 26 that controls writing of data to the receive buffer memory 23 , and a receive buffer memory 2
3, and a receive buffer deep control section 28 that detects the amount of data stored in the receive buffer memory 23 for each channel.

Further, the TDM count 30 generates a TDM address indicating the position of a channel on the TDM bus (for example, a time slot position), and the TDM control unit 40 controls the time division multiplexed data/packet conversion unit 10 according to this TDM address.
It also outputs timing signals used by each component of the packet/time division multiplex data converter 20. For this reason, T
The DM control unit 40 includes, as information corresponding to the TDM address, a channel number for identifying the channel,
It has a table that stores data such as a channel speed indicating the communication speed of the corresponding channel, and valid display information indicating whether the channel corresponding to the TDM address is used or not.

The operation for converting time division multiplexed data into packet data is performed as follows.

First, data on the TDM bus ioo is sorted according to channel via the transmission TDM switch 11, and is input to the corresponding channel of the transmission buffer memory 4.

In synchronization with this time division multiplexed data supply operation, the TDM counter 30 supplies the TDM control unit 40 with a TDM address corresponding to the time slot of the time division multiplexed data on the TDM bus 100, and the TDM control unit 40 further transmits the data. The buffer write control unit 15 is supplied with the channel number corresponding to this TDM address and the validity display information of the channel.

The transmission buffer write control section 15 controls the distribution of data in each time slot of 70M data in the transmission TDM switch 11 based on the channel number supplied from the TDM control section 40 . The transmission buffer write control unit 15 also sends a write instruction to the transmission buffer memory 12 to store the 70M data output from the transmission TDM switch 11 in the area of the corresponding channel of the transmission buffer memory 12.

The transmission packet determination unit 18 detects the amount of data for each channel accumulated in the transmission buffer memory 12, and determines whether the amount of data can be packetized. At this time, the transmission packet determination unit 18 is supplied with information about the channel number and channel speed of the corresponding channel from the TDM control unit 40, and based on this, the transmission packet determination unit 18 determines whether the amount of accumulated data is large or not. Control is performed to assign a high priority during packetization to a channel that increases the amount of supplied data.

The transmission packet determination section 18 notifies the transmission buffer read control section 15 and the packet header section 17 of the channel numbers in descending order of priority determined by the transmission packet determination section 18 .

The transmission buffer read control unit 16 performs control to read data stored in the transmission buffer memory 12 according to this channel number.

At this time, the transmission buffer read control unit 16 sends a read instruction to the transmission buffer memory length to read the data of the corresponding channel, and also controls the transmission PKT switch 13 to read out the data from the transmission buffer memo January 2. Data is input to one input terminal of the multiplexing section 14.

The packet header creation unit 17 includes a transmission packet determination unit 18
A header section is created according to the channel number notified from the multiplexer 14, and inputted to the other input end of the multiplexer 14. For this reason, the packet header section 17 has a built-in table that defines the relationship between each channel number and the contents of the header, for example, and by searching this table, outputs the corresponding header section.

The multiplexing section 14 adds a packet header section 17 to the data of each channel inputted via the transmission PKT switch 13.
Create a packet by multiplexing the header part created in , and output it as a transmission packet.

Further, the operation when converting a packet into time division multiplexed data is performed as follows.

First, a received packet is input to the separation unit 21 and separated into an information part and a header part, and the separated information part is the received PKT.
At the same time, the header section is sent to the received packet header processing section 25.

The received packet header processing section 25 analyzes the input header section, extracts the channel number corresponding to the input packet, and notifies the received buffer write control section 26 of the channel number.

The reception buffer write control unit 26 controls the reception PKT switch 22 based on the notified channel number, and the reception PKT switch 22 thereby distributes the reception data so that it is input to the corresponding channel of the reception buffer memory 23. At the same time, the reception buffer write control unit 26 sends a write instruction to the reception buffer memory 23 at the same time.
The data of the information section input from the reception PKT switch 22 is stored in the area of the reception buffer memory 23 corresponding to the channel number.

The reception buffer control unit 28 detects the amount of data corresponding to each channel stored in the reception frequency memory 23, and determines whether this data amount exceeds a specified value that guarantees synchronous continuous communication in each channel. Determine. At this time, since the channel number is notified from the TDM control unit 40, if the amount of accumulated data in that channel exceeds a predetermined value, permission to read this channel is given to the reception buffer read control unit 27. .

When receiving notification of the channel number from the TDM control unit 40 and receiving permission to read corresponding to this channel number from the reception banfaide control unit 28, the reception hashifarito control unit 27 performs reception corresponding to this channel number. Controls reading of data stored in the buffer memory 23.

The reception buffer read control section 27 sends a read instruction to the reception buffer memory 23 to read the data of the corresponding channel, and also controls the reception TDM switch 24 to connect the output of the corresponding channel of the reception buffer memory 23 to the TDM lotus 100. .

As a result, the data read from the reception buffer memory 23 is sent onto the TDM lotus 100.

[Problems to be Solved by the Invention] The conventional time division multiplex data-to-packet conversion circuit shown in FIG. If you do,
Slower speed lines require more time to accumulate the data needed for packetization, increasing conversion delays.

An increase in packet conversion delay is not a problem for data that does not require immediacy, but is undesirable for data that requires real-time transmission, such as voice, because it causes problems such as deterioration of sound quality.

2. The present invention aims to solve the problems of the prior art, and provides time division multiplex data-packet conversion that can reduce packet conversion delay by shortening data storage time for packetization. The purpose is to provide circuits.

[Means to solve the problem]

As shown in FIG. 1(aL(b)), the present invention is characterized in that data is written for each channel in the first data storage means l according to information on the correspondence between each time slot and a channel number. time division multiplexed data/packet converter 1 that reads a predetermined amount of time division multiplexed data and packetizes it;
0, and a packet that reads a predetermined amount of data written in the second data storage means 2 for each channel, and creates time division multiplexed data according to information on the correspondence between each time slot and channel number. A time division multiplex data-to-packet conversion circuit consisting of a time division multiplex data conversion section 20 is provided with a first channel number rewriting means 3 and a second channel number rewriting means 4.

Here, the first channel number rewriting means 3 rewrites the numbers of channels of the same destination and the same speed written in the first data storage means 1 to the same channel number, and the second channel number rewriting means The unit 4 rewrites this same channel number read from the second data storage means 2 to the original channel number.

[Operation] As shown in FIG. 1(a), the time division multiplexed data/packet converter (10) is connected to the first data storage means (1).
, a first line information storage means (50), a first writing means (51), a packet determining means (52), and a first line information storage means (50).
reading means (53), multiplexing means (54), and header creating means (55).

The first data storage means 1 has a data write area for each channel. The first line information storage means 50 stores information that determines the correspondence between each time slot and channel number in time division multiplexed data. The first writing means 451 performs the function of writing time division multiplexed data into a corresponding area of the first data storage means according to the channel number. The packet determining means 52 determines that the data of each channel in the first data storage means 1 exceeds a predetermined data amount.

The first reading means 53 reads data from the first data storage means 1 for each channel according to the determination by the packet determining means 52. The multiplexing means 54 adds the header part created by the header creation means 55 to the data read by the first reading means 53 and packetizes the data. Header creation means 55 creates a predetermined header section according to the channel number.

Further, as shown in FIG. 1(b), the packet/time division multiplex data conversion section 20 includes a second data storage means 3,
A header analysis means 61, a second writing means 62, a storage amount determining means 63, a second reading means 64, a second
and line information storage means 65.

5. The second data storage means 3 has a data write area for each channel. The header analysis means 61 detects the channel number corresponding to the packet from the header section separated from the input packet. The second writing means 62 is
The information part separated from the input packet according to the channel number detected by the header analysis means 61 is written into the corresponding area of the second data storage means 2. Storage amount determining means 63
determines that the amount of data of each channel stored in the second data storage means 2 exceeds a predetermined amount.

The second line information storage means 65 stores information on the correspondence between each time slot and channel number in time division multiplexed data. The second readout means 64 reads out the data in the corresponding area of the second data storage means 2 in the corresponding time slot according to the determination by the storage amount determination means 63.

In such a time division multiplex data/packet conversion unit 10, a first channel number rewriting unit 3 is provided, and a first channel number rewriting unit 3 is provided.
The channel numbers of the channels having the same destination and the same speed that are read into the data storage means 1 of 6 are rewritten to the same channel number. Further, in the packet/time division multiplex data conversion section 20, a second channel number rewriting section 4 is provided so that the data read from the second data storage means 2 is not rewritten by the first channel number rewriting means 3. Rewrite the same channel number with the original channel number.

Therefore, according to the present invention, packet conversion delay can be reduced by multiplexing and packetizing data having the same destination and the same speed, and shortening the data storage time for packetization.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the present invention, and the same parts as in the fifth part are indicated by the same numbers, and since their operations are the same as in FIG. 5, detailed explanation will be omitted. 3A and 4A are address determination sections, 3B and 4B, respectively.
are respectively channel number rewriting units.

Each part in Figure 2 is the same as each part in Figure 1 and the following 7. They have a correspondence relationship like this.

The transmission TDM switch 11 and the transmission hapharite control section 15 in FIG.
Corresponds to the writing means 51 of the sending buffer memo January 2
corresponds to the first data storage means 1, the transmission PKT switch 13 and the transmission buffer ret control section 16 correspond to the first reading means 53, the multiplexing section 14 corresponds to the multiplexing means 54, and the packet header section 17 corresponds to the header creation means 55, and the transmission packet determination section 18 corresponds to the packet determination means 52.

Further, the separation section 21 corresponds to the separation means 60, the received packet header processing section 25 corresponds to the header analysis means 61, the reception PKT switch 22 and the reception buffer write control section 26 correspond to the second writing means 62, The reception buffer memory 23 corresponds to the second data storage means 2, the reception TDM switch 24 and the reception buffer ret control unit 27 correspond to the second readout means 64,
The reception panoramic control unit 28 corresponds to the storage amount determining means 63. The TDM counter 30 and the TDM controller 1-roll unit 40 are
This corresponds to the first line information storage means 50 and the second line information storage means 65.

Furthermore, the address determination unit 3A, the channel number 1s.

The rewriting unit 3B corresponds to the first channel number rewriting unit 3, and includes an address determining unit 4A and a channel number rewriting unit 4.
B corresponds to the second channel number rewriting means 4.

In FIG. 2, the address determination unit 3A detects TDM addresses corresponding to low-speed channels having the same destination and the same speed in the TDM counter 30. The channel number rewriting unit 3B rewrites the channel number output from the TDM control unit 40 to the same channel number in accordance with the detected TDM address, and causes the transmission buffer write control unit 15 to output the same channel number.

The address determination unit 4A also detects TDM addresses corresponding to low-speed channels having the same destination and the same speed in the TDM counter 30. The channel number rewriting unit 4B controls the TDM control unit 40 in accordance with the detected TDM address to restore the same channel number that has been rewritten by the channel number rewriting unit 3B to the original address. The channel number is rewritten and output to the receiving Hanwha read control unit 27.

FIG. 3 is a diagram illustrating rewriting of channel numbers in the present invention.

In Figure 3, one frame is defined as the TDM address TSO.
- TDM data divided into seven time slots indicated by TS119 is shown.

As shown, TSO, TS4. TS5. TS12 has the same line information (64kbps, USD=1.
in use)) and has the same destination A. In the conventional system, different channel numbers CHOCH2 and CH3 are assigned to these time slots as shown in the figure.
, hit CH6.

In contrast, in the present invention, the same channel number CI-TO is assigned as shown in the figure.

Therefore, the data of each of these time slots is written to the same channel area on the 0 transmission buffer memory, read out at the same time, and transmitted in the same packet. In this way, since the low-speed data of multiple (n) lines to the same destination are multiplexed and packetized, the data storage time for packetization becomes 1/n, reducing the conversion delay associated with packetization on low-speed lines. I can do it.

On the receiving side, when reading from the receiving buffer memory, the same channel number is rewritten to the original channel number and output as TDM data according to this channel number, so it can be handled in the same way as before. Communication between each channel can be performed.

In the example shown in Fig. 3, when converting to a fixed length packet of 64 bytes, the conventional technology uses a 54 kbps line (CHO,
CH2, CH3, CH6) required an accumulation time of 8 ms, but according to the present invention, by multiplexing 4 lines, packetization can be performed in an accumulation time of 2 ms, making it possible to significantly reduce conversion delay. Become.

1 FIG. 4 shows a specific configuration example of the present invention,
The same parts as in FIG. 2 are indicated by the same numbers, and their operations are the same, but the transmission TD in FIG.
M switch 11. The transmit PKT switches 13 are replaced by a write address generator 41 and a read address generator 42, respectively, and the receive PKT switches 22 . Reception TD
The M switches 24 each have a write address generator 43
．． It has been replaced by the read address generation section 44.

The write address generation section 41 includes the TDM control section 4
A write address in the transmitter sofa memory 12 is generated based on the channel number indicated from 0. Based on this address, T
DM data is stored in the transmission buffer memo January 2.

The read address generation unit 42 is connected to the transmission packet determination unit 18
A read address in the transmitting buffer memory 12 is generated based on the channel number instructed by the transmitting buffer memory 12. Based on this address, stored data is output from the data output terminal Do in response to a read pulse supplied from the transmission buffer read control unit 16 to the output enable terminal OE.

Further, the write address generation section 43 generates a write address in the reception panzer memory 23 according to the channel number instructed by the reception packet I/header processing section 25. Based on this address, packet data supplied to the data input terminal DI is stored in the reception buffer memory 23 in response to a write pulse supplied from the reception buffer write control section 26 to the write enable terminal WE.

The read address generation section 44 is the TDM control section 4
A read address in the reception buffer memory 23 is generated based on the channel number output from 0. Based on this address, stored data is output from the data output terminal Do in response to a read pulse supplied from the reception buffer read control section 27 to the output enable terminal OE.

3 4 is a second channel number rewriting means.

[Effects of the Invention] As explained above, according to the present invention, in a time division multiplex data-packet conversion circuit, multiple lines communicating with the same partner device are treated as if they were a single line, and multiplexed and packetized. Therefore, the same destination.

It is possible to reduce the data storage time for packetizing line data at the same speed, and to reduce conversion delay. The present invention is particularly effective when used for converting time division multiplexed data and packets on a line that requires real-time transmission of voice and the like.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram explaining rewriting of channel numbers in the present invention. FIG. 4 is a diagram showing a specific configuration example of the present invention, and FIG. 5 is a diagram showing a conventional time division multiplex decouple bucket conversion circuit. 2 is the first data storage means, 2 is the second data storage means, 3 is the first channel number rewriting means, 4

Claims (1)

[Claims] When a predetermined amount of time division multiplexed data written in the first data storage means (1) for each channel is read out and packetized according to information on the correspondence between each time slot and a channel number. The division multiplex data/packet converter (10) reads out a predetermined amount of data written into the second data storage means (2) of input packet information for each channel, and obtains information on the correspondence between each time slot and channel number. In a time division multiplex data-to-packet conversion circuit comprising a packet/time division multiplex data conversion unit (20) that creates time division multiplex data according to the same destination written in the first data storage means (1),
a first channel number rewriting means (3) for rewriting the numbers of channels with the same speed to the same channel numbers; and a second channel number rewriting means (3) for rewriting the same channel numbers read from the second data storage means (2) to the original channels. 1. A time division multiplexed data-packet conversion circuit comprising: second channel number rewriting means (4) for rewriting the channel number.