JPH04221491A - Fifo circuit for cell - Google Patents

Abstract

PURPOSE:To accelerate a speed and to increase a capacity by employing an FIFO controller which can simultaneously control a plurality of virtual passes. CONSTITUTION:When a memory block 2 receives a write start signal from an FIFO controller 1, the block 2 writes data for one cell in a write address. A leading word of a cell to be started by the start signal is written in a memory bank. When a read start signal from the controller 1 is received, data for one cell is output from the read address. In this case, the leading head of the cell is read from next memory bank of the final word memory bank of the cell which was previously read, and then sequentially read. The writing/reading of the respective words are deviated at the banks for the respective one words, and hence the banks to be written and read are not simultaneously conducted to be written and read, but sequentially written and read. N pieces of the banks are provided thereby to alleviate writing/reading time limits.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to, for example, ATM (Asylum)
Chronous Transfer Mode
) Requires a high-speed, large-capacity FIFO (first-in-first-out) like the speed conversion buffer in an exchange, and data is written and read in fixed-length units called cells. FI as a buffer for FIFO when
This relates to the FO circuit. In addition, the present invention can be applied to general information processing equipment that requires a high-speed and large-capacity FIFO.

0002

[Prior Art] As a prior art, for example, Japanese Patent Application Laid-open No. 63
As disclosed in the attached drawing of the specification of No. 271601 "Packet Communication Device", there is an invention that uses so-called 2-port RAM (also called dual-port RAM) in the memory block part.
is not produced in large scale compared to normal 1-port RAM, and large-scale FIFO using 2-port RAM
It is currently difficult to configure a

[0003] For this reason, it cannot necessarily be said that a sufficient capacity can be obtained as a buffer in an ATM switch. In particular, as seen in recent standardization trends in the CCITT (International Telegraph and Telephone Consultative Committee), specifications have been realized in which multiple virtual paths (logical virtual transmission paths) exist on the same transmission path that do not share the band with each other. If you try to do this, a FIFO corresponding to the plurality of virtual paths will be required in the buffer corresponding to one transmission path, and in such a case, if a 2-port RAM was used, the external dimensions of the device would be enormous. The problem was that it was not practical.

0004

[Problem to be solved by the invention] As already mentioned,
When a large number of high-speed, large-capacity FIFOs are required, such as speed conversion buffers in ATM exchanges, conventional 2-port RAMs are not manufactured in large scale compared to 1-port RAMs, so It is difficult to configure a large-scale FIFO using RAM, and when attempting to configure the entire system with asynchronous FIFO, using such RAM would result in a large external size of the device, making it impractical. This problem is solved by using a FIFO controller that can control multiple virtual paths at once.
The problem to be solved by the present invention is to enable a device to be manufactured quickly and compactly even when a large number of IFOs are required.

[0005]

[Means for Solving the Problems] The solution to the above problems of the present invention is to solve the above problems by using N numbers from the first to the Nth (however, N is any integer).
A memory block is provided, which is composed of a memory bank, one timing control circuit, one write address conversion circuit, and one read address conversion circuit, and is capable of writing and reading data in units of one cell. This is achieved by providing a FIFO controller circuit that provides control signals such as a write address, a write start signal, a read address, and a read start signal to the memory block. The memory bank uses a normal 1-port RAM, and can be switched between writing and reading under the control of a timing control circuit.

[0006]

[Operation] The first cell FIFO circuit according to the present invention is the cell FIFO circuit according to claim 1, but the first cell FIFO circuit according to the present invention is
Upon receiving a write start signal from the controller, the memory block writes data for one cell to the write address. At this time, the first word of the cell whose writing is started by the write start signal is written to the memory bank next to the memory bank to which the last word of the cell that was previously written is written, and from then on, each word is written one by one. Write to the next memory bank after the memory bank in which the word was written. However, if the memory bank to which the previous word was written is the final Nth memory bank, the first memory bank is set as the next memory bank.

[0007] When receiving a read start signal from the FIFO controller, data for one cell is output from the read address. At this time, the first word of the cell is read from the memory bank next to the memory bank of the last word of the cell that was read last time, and then each word is sequentially read from the next memory bank from which the previous word was read. However, when the memory bank from which the previous word was read is the final Nth memory bank, the first memory bank is used as the next memory bank for reading. Through the above write and read operations, cells with an arbitrary number of words can be handled.

[0008] Furthermore, if the number of waiting cells does not reach a preset limit when a cell arrives, the FIFO controller gives an unused address as a write address to the memory block and also sends a write start signal. give. Conversely, if the limit number has been reached, the write start signal is not given. In addition, at a certain period, if the number of waiting cells in the memory block is 1 or more, the address containing the waiting cell to be output next is given to the memory block as a read address. , a read start signal is given, and when the number of waiting cells is 0, the read start signal is not given.

In the timing diagram shown in FIG. 3 (an example in which the number of memory banks is 4), when writing and reading each word, the memory banks are shifted for each word, so that the memory banks for writing and reading are Writing and reading are performed sequentially without overlapping. In addition, by increasing the number of memory banks to N, the time to write and read one word in N memory banks is extended by N/2, which eases the time limit for data written to and read from each bank. be done. As a result, the speed on the incoming and outgoing highways can be increased to N/2 times the access speed of a commercially available RAM. Due to the above-described effects, the first cell FIF according to the present invention
Although the O circuit is small, it realizes a large capacity and high speed FIFO.

A second cell FIFO circuit according to the present invention adds a small-scale asynchronous FIFO to the first cell FIFO circuit according to the present invention, and the small-scale asynchronous FIFO is connected to the FIFO controller. Asynchronous FI of scale
An acceptable signal is given when the number of cells in the FO is below a certain number, and no acceptable signal is given when it exceeds a certain number.

[0011] Furthermore, in a data read operation from a memory block that is performed at a certain period, the FIFO controller determines that the number of waiting cells is 1 or more and that an acceptance signal from the small-scale asynchronous FIFO is given. If so, a read start signal is given to the memory block and at the same time a write enable signal is given to the small-scale asynchronous FIFO.

[0012] Furthermore, if the number of waiting cells is 0 or an acceptability signal is not given from the small-scale asynchronous FIFO, the read start signal to the memory block is also sent to the small-scale asynchronous FIFO. The write permission signal is also not given. This is because a write operation to a small asynchronous FIFO causes cells to be discarded.

The cell write operation in the memory bank is the same as in the first cell FIFO circuit. Also, FI
When the FO controller provides a read start signal, the cell read operation from the memory bank is also the same as that of the first cell FIFO circuit. The cells read from the memory bank are temporarily stored in a small-scale asynchronous FIFO, and then output to the output highway using the output highway clock, which is asynchronous with the input highway clock.

As described above, the second cell FI according to the present invention
In the FO circuit, most of the cell storage capacity is realized by a memory bank whose write and read operations operate using synchronous clocks, but the write clock and read clock can be made asynchronous by the action of a small-scale asynchronous FIFO. Due to the above-described effects, the second cell FI according to the present invention
The FO circuit is a small FIFO that has a large capacity and high speed, but is realized under the same asynchronous input/output conditions as a FIFO circuit that is made up only of asynchronous FIFOs that are small but have a small capacity.

In the third cell FIFO circuit according to the present invention, the cell write operation to the memory bank is the same as that of the first cell FIFO circuit, but the cell write position at this time is stored in the FIFO controller, and the cell write operation to the memory bank is When reading a cell, the FIFO controller reads from the memory bank specified based on the cell position stored at the time of writing, and the timing control circuit sequentially reads each word from the memory bank after the previous word was read. Reading is performed from the memory bank.

At this time, if the memory bank from which the previous word was read is the final Nth memory bank, reading is performed using the first memory bank as the memory bank for the next word. Note that in the third cell FIFO circuit according to the present invention, since reading is performed asynchronously with the writing operation, writing and reading may overlap on the same memory bank, and in this case, writing takes priority. Reading will be temporarily stopped. Moreover, here, FIFO
For example, by using a FIFO controller capable of managing queues of multiple cells corresponding to multiple virtual paths having a structure as shown in FIG.
It can be used for the same function as a circuit.

[0017] The fourth cell FIFO circuit according to the present invention includes the first cell FIFO circuit in the third cell FIFO circuit.
Similar to the second cell FIFO circuit for the O circuit,
A small asynchronous FIFO is added. The cell write operation in the memory bank is performed by the third cell FIF.
It is the same as the O circuit. Further, even when the FIFO controller gives a read start signal, the cell read operation from the memory bank is the same as that of the third cell FIFO circuit.

The cells read from the memory bank are once input into the small-scale asynchronous FIFO, and then output to the output highway using the output highway clock, which is asynchronous with the input highway clock. Said third cell FIF
In the O circuit, if writing and reading overlap on the same memory bank, writing takes priority and reading is temporarily stopped, but small-scale asynchronous FIFO
is added, so that an irregular number of intervals that are less than the cell length will not be left on the outgoing highway due to the reading restriction.

However, as an exception, if the speed difference between the write clock and the read clock is extremely small, all cells in the small asynchronous FIFO are output when writing is in progress and reading is inhibited. There is a possibility that However, the present invention is originally used to suppress cell discard when the speed difference between the write clock and the read clock is large. Therefore, it can be considered that such a phenomenon does not occur in practice.

[0020] Due to the above-described effects, it is possible to use the same function as using a plurality of asynchronous cell FIFO circuits for each virtual path. The clocks can be operated asynchronously, and even if cell reading is uneven in the memory block, the cell spacing on the output highway can be kept constant.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a cell FIFO circuit according to a first embodiment of the present invention. In FIG. 1, address is an address designation signal that specifies write and read addresses from FIFO controller 1 to memory block 2, ICS is a write start signal sent from FIFO controller 1 to memory block 2, and I
CSS is a signal indicating the beginning of an arriving cell, ICK is a word clock on the input highway and is supplied to the IFO controller 1 and memory block 2, and OCSS is a read start signal sent from the FIFO controller 1 to the memory block 2.

As shown in FIG. 4, the memory block 2 includes a timing control circuit TB, a memory bank (BA
NK) 0 to memory bank (BANK) 3, data input side registers 0 to 3 (DIFF)
0 to 3), data output registers 0 to 3 (DOFF
0 to 3), write registers 0 to 3 (DWAFF0
3), read registers 0 to 3 (DRAFF0 to 3), a write address conversion circuit (WACNV), and a read address conversion circuit (RACNV), and the timing control circuit TB sends timing pulses to each register. Each register writes and reads cell data based on this timing.

Furthermore, the memory bank (BANK) is for storing cell data, and at the time of writing, data is written from the data input side register (DIFF), but at this time, the data is written from the data input side register (DIFF). When the internal address of the memory bank (BANK) is held in the write register (DWAFF), the write pulse output from the timing control circuit TB is sent to the memory bank (BANK) using this internal address.
is supplied to the address input of the timing control circuit T.
A write pulse is output from B to the memory bank (BANK), and one word worth of data of the cell held by the cell data input register (DIFF) is written to the memory bank (BANK).
ANK).

Write address conversion circuit (WACNV)
Now, using the address designation value "what cell" from the FIFO controller, ICS and ICK, generate an internal address value for each memory bank (BANK) at appropriate timing (for example, as shown in Figure 3). do. At the time of reading, cell data is read out through the cell data output register (DOFF), but at this time, the address output from the read address conversion circuit (RACNV) is input to the read address register (DRAFF), and then this Using the internal address value, data is read from the memory bank (BANK) to the data output register (DOFF) by a read pulse from the timing control circuit TB.

Read address conversion circuit (RACNV)
Then, an internal address value for each memory bank (BANK) is generated at appropriate timing using the address designation value "which cell" from the FIFO controller, OCSS and ICK.

The timing in the memory bank (BANK) at this time is as shown in FIG. are not duplicated on the same memory bank (BANK), and if the number of memory banks is 4 as in this example,
Since the writing and reading time for the entire memory block is doubled (N/2 times) compared to the case of one memory bank, the time limit for writing and reading per RAM is relaxed. Therefore, the cell F of the present invention
The speed of IFO is twice the access speed of commercially available RAM (N
/2), and the inbound and outbound highway speeds are also doubled.

The FIFO controller provides an unused address and a write start signal as a write address to the memory block when the number of waiting cells in the memory block has not reached a preset limit number. However, if the number of waiting cells in the memory block has reached a preset limit, neither a write address nor a write start signal is given. At this time, this is to prevent data in the cell from being overwritten and erased by data that has not yet been read out when writing is performed.

[0028] Also, reading is performed at a certain period,
If the number of waiting cells in a memory block is 1 or more, a read address and a read start signal are given to the memory block, but if the number of waiting cells in a memory block is 0, neither a read address nor a read start signal is given. I won't give it.

FIG. 2 is a block diagram of a cell FIFO circuit according to a second embodiment of the present invention. In FIG. 2, address is a signal that specifies write and read addresses from FIFO controller 1 to memory block 2, ICS is a write start signal sent from FIFO controller 1 to memory block 2, and ICSS is a signal for specifying a write and read address from FIFO controller 1 to memory block 2. A leading instruction signal, ICK, is a word clock on the input highway and is supplied to the FIFO controller 1 and memory block 2, and OCSS is a read start signal sent from the FIFO controller 1 to the memory block 2.

[0030] Furthermore, in the small-scale asynchronous FIFO 3,
The NOTFUL terminal is connected to the REN terminal input which allows the FIFO controller 1 to read with an acceptable signal indicating that the data in the small asynchronous FIFO 3 has not reached the preset value;
The N terminal receives a write permission signal sent from the JK>0 terminal of the FIFO controller 1 indicating that one or more cells are waiting in the memory block 2, and the LDC
The K terminal receives ICK, which is the input highway clock.

In addition, the configuration and write operation in the second embodiment are the same as those in the first embodiment, and for the read operation, an acceptability signal from the small-scale asynchronous FIFO 3 is not sent to the FIFO controller 1. The operation is the same as that of the first embodiment except for the case.

The output of memory block 2 is a small-scale asynchronous F
It is the input of IFO3, and this small asynchronous FIF
O3 provides an accept signal to FIFO controller 1, which in turn provides a small asynchronous F
A write permission signal can be issued to IFO3. The acceptability signal outputted from the small-scale asynchronous FIFO 3 is a vacancy-ready signal to the FIFO controller 1 when the number of cells in the small-scale asynchronous FIFO 3 is below a certain number, and an acceptability signal when the number of cells in the small-scale asynchronous FIFO 3 exceeds a certain number. It is designed not to give

As shown in FIG. 3, the timing within the memory bank 2 at this time is such that each word is sequentially written to each memory bank with a shift, and writing and reading are performed alternately, so writing and reading are performed in the same memory bank. Moreover, when the number of memory banks is 4 as in this embodiment, the writing and reading time for the entire memory block is twice (N/2) compared to when there is 1 memory bank.
By increasing the number of times (2 times), the time limit for writing and reading per RAM is relaxed. Therefore, the cell FIFO circuit according to the present invention can be made twice (N/2) faster than the access speed of a commercially available RAM, and the incoming and outgoing speeds can also be doubled.

The FIFO controller 1 gives a read start signal to the memory block 2 when the number of waiting cells in the memory block 2 is 1 or more and there is an acceptable signal from the small-scale asynchronous FIFO 3. , gives a write permission signal to the small-scale asynchronous FIFO 3, and if the number of waiting cells is 0 or an acceptability signal is not given from the small-scale asynchronous FIFO 3, starts reading from the memory block 2. Neither signal nor write permission signal to the small-scale asynchronous FIFO 3 is given. this is,
This is because cells are discarded when a write operation to the small-scale asynchronous FIFO is performed.

[0035] Due to the above action, it is as if the asynchronous cell FI
Similar to the case where the entire structure is made up of FO circuits, the write clock and read clock operate asynchronously.

The third embodiment of the present invention is shown in FIG.
Address is FIFO write and read address
It is specified from controller 1 to memory block 2, and ICS is a write start signal sent from FIFO controller 1 to memory block 2.
S is a signal indicating the head of an arriving cell, ICK is a signal for supplying the input highway from the FIFO controller 1 to the memory block 2, and OCSS is a read start signal sent from the FIFO controller 1 to the memory block 2.

The configuration of the memory block 2 and the write operation to the memory bank are the same as in the first embodiment. For read operations from memory banks, writes are written to each memory bank sequentially and reads are FIFO
Since reading is performed by randomly specifying addresses under the control of the controller 1, writing and reading may overlap on the same memory bank, and in this case, writing is given priority and reading is temporarily stopped.

If the number of waiting cells in the memory block 2 has not reached the preset limit, the FIFO controller 1 gives the memory block 2 an unused address as a write address and a write start signal. . However, if the number of waiting cells in the memory block 2 has reached a preset limit, neither a write address nor a write start signal is given.

Further, reading is performed using the FIFO controller 1.
The timing control circuit TB in the memory bank selects the memory bank in which the first word of the cell to be read next is written.
The memory bank specified by the FIFO controller 1 is read out sequentially, and if the number of waiting cells in the memory block is 1 or more, the read address is sent to the memory block 2 at a certain period. and gives a read start signal, but memory block 2
If the number of waiting cells in the cell is 0, neither a read address nor a read start signal is given.

Moreover, here, the FIFO controller 1, for example, has a structure as shown in FIG.
REQ), the read start signal (OCSS) sent from the contention control circuit 6 is given to the read address table 5 for one FIFO, and the selector circuit 7 sends the address for one FIFO to be read next to the memory block. By using the FIFO controller 1 that manages a plurality of cell queues corresponding to a plurality of virtual paths, it can be used with the same function as providing a plurality of cell FIFO circuits for each virtual path.

In the fourth embodiment of the present invention, in FIG. 2, the address specifies write and read addresses from the FIFO controller 1 to the memory block 2, and the ICS specifies the write and read addresses from the FIFO controller 1 to the memory block 2. ICSS
is the head instruction signal of the arriving cell, ICK is the signal that supplies the write clock from the FIFO controller 1 to the memory block 2, and OCSS is the signal that supplies the write clock from the FIFO controller 1 to the memory block 2.
This is a read start signal sent from the memory block 2 to the memory block 2.

[0042] Furthermore, in the small-scale asynchronous FIFO 3,
The NOTFUL terminal sends an acceptance signal to the REN terminal indicating that the data in the small-scale asynchronous FIFO 3 has not reached the preset value, and the WEN terminal sends the memory signal sent from the JK>0 terminal of the FIFO controller 1. A write permission signal indicating that one or more cells are waiting in block 2 is received, and the LDCK terminal receives ICK, which is the input highway clock.

The structure and write operation of the memory block 2 are the same as in the first embodiment. For read operations, FIFO controller 1 has a small asynchronous F
The operation is the same as in the first embodiment except for the case where the acceptability signal from the IFO 3 is not transmitted.

The output of memory block 2 is a small-scale asynchronous F
It is the input of IFO3, and this small asynchronous FIF
O3 provides an accept signal to FIFO controller 1, which in turn provides a small asynchronous F
A write permission signal can be issued to IFO3. The acceptability signal output from the small-scale asynchronous FIFO 3 is such that an acceptability signal is sent to the FIFO controller 1 when the number of cells in the small-scale asynchronous FIFO 3 is below a certain number, and an acceptability signal is sent to the FIFO controller 1 when the number of cells in the small-scale asynchronous FIFO 3 exceeds a certain number. It is designed not to be given.

The timing within the memory bank at this time is such that each word is sequentially written to each memory bank with a shift,
Reading is performed in the same way as writing, but at this time, writing is written to each memory bank sequentially, and reading is performed by randomly specifying an address under the control of FIFO controller 1, so writing and reading are performed from the same memory. There may be duplicates on a bank, in which case writing will take priority and reading will be temporarily stopped.

The FIFO controller 1 gives a read start signal to the memory block 2 when the number of waiting cells in the memory block 2 is 1 or more and there is an acceptable signal from the small-scale asynchronous FIFO 3, and A write permission signal is given to the small-scale asynchronous FIFO 3, and if the number of waiting cells is 0 or an acceptability signal is not given from the small-scale asynchronous FIFO 3, a read start signal is sent to the memory block 2. Also, no write permission signal is given to the small-scale asynchronous FIFO 3.

Here, the FIFO controller 1 has a structure as shown in FIG. 5, for example, and sends a sendable signal (REQ
), the read start signal (OCSS) sent from the contention control circuit 6 is given to the read address table 5 for one FIFO, and the selector circuit 7 selects the next FIF to be read.
By using the FIFO controller 1 that manages queues of multiple cells corresponding to multiple virtual paths, such as sending O1 addresses to the memory block 2, multiple asynchronous addresses can be generated for each virtual path. It can be used for the same function as using FIFO. In addition, due to the action of small-scale asynchronous FIFO3,
Write clock and read clock can be asynchronous,
Even if reading of cells in the memory block 2 is uneven, the cell spacing on the output side can be made constant.

[0048]

[Effects of the Invention] As stated above, the first,
According to the third invention (embodiment), the FIFO circuit is used for waiting for fixed-length cell-type data, and includes a memory block in which data can be written and read in units of one cell, and a memory block for the memory block. It is equipped with a FIFO controller that provides a write address, a write start signal, a read address, and a read start signal, and uses the configuration shown in Figure 1, and the whole is an asynchronous FIFO using a 2-port RAM.
We solved the problem that it was difficult to achieve sufficient buffer capacity by configuring with FO, and the speed was increased by providing memory banks and dividing each word into banks.
/2 times (where N is the number of memory banks),
Moreover, it is possible to obtain the effect that cells having an arbitrary data length can be handled.

[0049] In addition to the above effects, the second effect in this application is
According to the fourth invention (embodiment), the configuration shown in FIG. 2 is provided, and a small-scale asynchronous FIFO is provided on the output side of the memory block.
By providing this, the write clock and the read clock can be made asynchronous, and according to the fourth invention (embodiment), when the interval between cells output from the memory block is undefined, it is possible to make the write clock and the read clock asynchronous. Since the output is performed after the output, even if the readout of the cells in the memory block is uneven, it is possible to obtain the effect of making the interval between the cells on the output side constant. Moreover, the third
In the fourth invention (embodiment), it is possible to obtain the effect that it can be used for the same function as providing a plurality of cell FIFO circuits for each of a plurality of virtual paths.

[Brief explanation of the drawing]

[Fig. 1] Cell FIF which is the first and third embodiments of the present invention
FIG. 3 is a configuration diagram of an O circuit.

[Fig. 2] Cell FIF which is the second and fourth embodiments of the present invention
FIG. 3 is a configuration diagram of an O circuit.

FIG. 3 is an operation timing diagram of a memory bank controlled by a timing control circuit within a memory block.

FIG. 4 is a block configuration diagram of a memory block common to FIGS. 1 and 2;

FIG. 5 is an internal configuration diagram of a FIFO controller common to the third and fourth embodiments.

[Explanation of symbols]

1...FIFO controller, 2...memory block, 3...
Small-scale asynchronous FIFO, 5...Read address table for one FIFO, 6...Conflict control circuit, 7...Selector, address...Address in memory block, ICS: Write start signal, OCSS: Read start signal, JK>0: A signal indicating that a cell is waiting in the memory block, WEN: Takes the write permission signal of JK>0 into the small asynchronous FIFO, NOTFUL: Sends an acceptable signal to the FIFO controller, REN: NOTF
LDCK: Small-scale asynchronous FI that takes in the write enable signal from UL to the FIFO controller.
Take clock into FO, IFF: write timing signal, OFF: read timing signal, WAFF:
Write address timing signal, RAFF: Read address timing signal, WE: Write enable signal, O
E: Readable signal, TB: Timing control circuit, R
EQ: Sendable signal.

Claims (4)

[Claims] Claim 1: A FIFO circuit used for waiting for fixed-length cell-type data, which includes a memory block in which data can be written and read in units of cells, and a write address and write start for the memory block. a FIFO controller circuit that provides a signal, a read address, and a read start signal, and when the memory block receives a write start signal from the FIFO controller, it takes in one cell's worth of data at the write address and sends the data to the FIFO controller. When the FIFO controller receives a read start signal from the read address, it outputs one cell's worth of data from the read address, and if the number of waiting cells does not reach a preset limit when the cell arrives, the FIFO controller An unused address is given as a write address and a write start signal is given to the memory block, and conversely, when the limit has been reached, a write start signal is not given to the memory block. , If the number of waiting cells is 1 or more at a certain period, the address containing the waiting cell to be output next is given to the memory block as the read address, and the read If a reading start signal is given and the number of waiting cells is 0, a reading start signal is not given, and the memory blocks are
N memory banks (where N is any integer) up to
It consists of one timing control circuit, one write address conversion circuit, and one read address conversion circuit, and the write operation upon arrival of the cell is performed by converting the first word of the cell from the previous write. The timing control circuit performs write address conversion on the write position within each memory bank according to write pulses generated sequentially for each memory bank. The circuit is FI
According to the address obtained by converting the address value from the FO controller using the number of clock pulses from the beginning of the cell, each word is transferred to the memory bank next to the memory bank in which the previous word was written (unless the previous word was written). When the last memory bank is the Nth bank, the first bank is set as the next memory bank.) The read operation, which is performed at a certain period, reads the first word of the cell from the previous read. The last word of the cell read out is read from the memory bank next to the memory bank from which the last word of the cell was read. The start position is read and the address conversion circuit is F.
According to the address obtained by converting the address value from the IFO controller using the number of clock pulses from the beginning of the cell, each word is read from the memory bank next to the memory bank from which the previous word was read (but only if the previous word was read). 1. A cell FIFO circuit characterized in that when the output memory bank is the final Nth bank, reading is performed using the first bank as the next memory bank. 2. In the cell FIFO circuit according to claim 1, a small-scale asynchronous FIFO is added, the data output of the memory block becomes a data input of the small-scale asynchronous FIFO, and the small-scale asynchronous FIFO is the above F
An accept signal may be provided to an IFO controller, the FIFO controller may provide a write permission signal to the small asynchronous FIFO, and the small asynchronous FIFO may be configured to control the number of cells in the asynchronous FIFO. When the number of cells is less than a certain number, an acceptability signal is given to the FIFO controller, and when the number of cells exceeds a certain number, an acceptability signal is not given to the FIFO controller. In a data read operation from a memory block, if the number of waiting cells is 1 or more and an acceptable signal is given from the small-scale asynchronous FIFO, a read start signal is given to the memory block. At the same time, a write permission signal is given to the asynchronous FIFO, and if the number of waiting cells is 0 or an acceptability signal is not given from the small-scale asynchronous FIFO, a read start signal is given to the memory block. A cell FIFO circuit characterized in that neither a write permission signal to the asynchronous FIFO is given. 3. A FIFO circuit used for queuing fixed-length cell-type data with a plurality of attributes defined, comprising a memory block in which data can be written and read in units of one cell, and a memory block for the memory block. , a write address, a write start signal, a read address, and a FIFO controller circuit that provides a read start signal, and when the memory block receives a write start signal from the FIFO controller, it stores data for one cell at the write address. When it receives a read start signal from the FIFO controller, it outputs data for one cell from the read address, and the FIFO controller is a FIFO controller that manages a plurality of queues corresponding to the attributes of the cell. At the time of arrival, if the number of waiting cells for each attribute of the arriving cell does not reach the preset limit, an unused address is given as a write address to the memory block, and a write start signal is given. On the contrary, if the limit number is reached, the write start signal is not given, and at a certain period, a procedure that is fixedly installed in advance or given from the outside is set. Accordingly, select the cell attribute to be read, and if the number of waiting cells for the selected cell attribute is 1 or more, the next waiting cell attribute to be output as the read address for the memory block is selected. along with giving the address that houses the cell,
When a read start signal is given and the number of waiting cells is 0, the selection is redone or no read start signal is given, and the memory blocks are divided into memory blocks from the first to the Nth. It consists of N memory banks (N is any integer), one timing control circuit, one write address conversion circuit, and one read address conversion circuit. In the write operation, the first word of the cell is written to the memory bank next to the memory bank to which the last word of the previously written cell was written. The word is written to the memory bank next to the memory bank in which the previous word was written.
(However, if the memory bank to which the previous word was written is the final Nth bank, the first bank is set as the next memory bank.) Write and read operations are performed at the beginning of the cell to be read next by the FIFO controller. The memory bank in which the word is stored is specified and set in the timing control circuit, and the first word of the cell is
Each word is read from the memory bank specified by the FO controller, and then, by the action of the timing control circuit and address conversion circuit, each word is read from the memory bank next to the memory bank from which the previous word was read (however, the previous word A cell FIFO circuit characterized in that when the memory bank from which the data is read is the final Nth bank, the first bank is read as the next memory bank. 4. In the cell FIFO circuit according to claim 3, a small-scale asynchronous FIFO is added, the data output of the memory block becomes a data input of the small-scale asynchronous FIFO, and the small-scale asynchronous FIFO is the above F
An accept signal may be provided to an IFO controller, the FIFO controller may provide a write permission signal to the small asynchronous FIFO, and the small asynchronous FIFO may be configured to control the number of cells in the asynchronous FIFO. When the number of cells is less than a certain number, an acceptability signal is given to the FIFO controller, and when the number of cells exceeds a certain number, an acceptability signal is not given to the FIFO controller. In a data read operation, if the number of waiting cells for the selected attribute is 1 or more and an acceptability signal is given from the small-scale asynchronous FIFO, a read start signal is given to the memory block. At the same time, a write permission signal is given to the asynchronous FIFO, and if the number of waiting cells for the selected attribute is 0 or an acceptability signal is not given from the small-scale asynchronous FIFO, the memory block A cell FIFO circuit characterized in that neither a read start signal to the asynchronous FIFO nor a write permission signal to the asynchronous FIFO is applied.