JPS57192151A - Communicating system for packet signal - Google Patents

Communicating system for packet signal

Info

Publication number
JPS57192151A
JPS57192151A JP56076999A JP7699981A JPS57192151A JP S57192151 A JPS57192151 A JP S57192151A JP 56076999 A JP56076999 A JP 56076999A JP 7699981 A JP7699981 A JP 7699981A JP S57192151 A JPS57192151 A JP S57192151A
Authority
JP
Japan
Prior art keywords
packet
memory
memories
processor
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56076999A
Other languages
Japanese (ja)
Other versions
JPS6332300B2 (en
Inventor
Satoshi Nojima
Takashi Suzuki
Akimasa Yatsuhoshi
Tatsuro Takahashi
Tomonori Aoyama
Hiromi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56076999A priority Critical patent/JPS57192151A/en
Publication of JPS57192151A publication Critical patent/JPS57192151A/en
Publication of JPS6332300B2 publication Critical patent/JPS6332300B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To speed up the packet signal transmission and to increase the number of allocated subscribers per processor, by providing a buffer memory for each of reception and transmission section of a packet processor and making the data transmission of each packet at a DMA controller. CONSTITUTION:HDLC circuits 4 and 4' making rearrangement of packets corresponding to a subscriber are arranged and the circuits 4 and 4' are provided respectively with line memories 51 and 51' having functions as buffer memories. The memories 51 and 51' are connected with a memory 3, a processor 2 and a direct memory access controller DMAC1 via a bus line 6. Through the control of the DMACA1, the types and address of packets are discriminated at the memory 51 with the access from the processor 2 and the relayed packet is transmitted to the memory 51' with one time of DMA via a bus 9. Further, the packet required for the processing is transmitted to the memories 51 and 51' through the memory 3 on a bus 10 to speed up the transmission of packet signals.
JP56076999A 1981-05-21 1981-05-21 Communicating system for packet signal Granted JPS57192151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076999A JPS57192151A (en) 1981-05-21 1981-05-21 Communicating system for packet signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076999A JPS57192151A (en) 1981-05-21 1981-05-21 Communicating system for packet signal

Publications (2)

Publication Number Publication Date
JPS57192151A true JPS57192151A (en) 1982-11-26
JPS6332300B2 JPS6332300B2 (en) 1988-06-29

Family

ID=13621468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076999A Granted JPS57192151A (en) 1981-05-21 1981-05-21 Communicating system for packet signal

Country Status (1)

Country Link
JP (1) JPS57192151A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206346A (en) * 1985-03-11 1986-09-12 Fujitsu Ltd Data exchange equipment
JPS6285533A (en) * 1985-10-11 1987-04-20 Nec Corp Decentralized packet exchange system
JPS6361530A (en) * 1986-09-02 1988-03-17 Nippon Telegr & Teleph Corp <Ntt> Packet switch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571339A (en) * 1978-11-22 1980-05-29 Fujitsu Ltd Packet transfer circuit system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571339A (en) * 1978-11-22 1980-05-29 Fujitsu Ltd Packet transfer circuit system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206346A (en) * 1985-03-11 1986-09-12 Fujitsu Ltd Data exchange equipment
JPH0511453B2 (en) * 1985-03-11 1993-02-15 Fujitsu Ltd
JPS6285533A (en) * 1985-10-11 1987-04-20 Nec Corp Decentralized packet exchange system
JPS6361530A (en) * 1986-09-02 1988-03-17 Nippon Telegr & Teleph Corp <Ntt> Packet switch

Also Published As

Publication number Publication date
JPS6332300B2 (en) 1988-06-29

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