ES8402091A1 - Multiprocessing interrupt arrangement - Google Patents
Multiprocessing interrupt arrangementInfo
- Publication number
- ES8402091A1 ES8402091A1 ES517861A ES517861A ES8402091A1 ES 8402091 A1 ES8402091 A1 ES 8402091A1 ES 517861 A ES517861 A ES 517861A ES 517861 A ES517861 A ES 517861A ES 8402091 A1 ES8402091 A1 ES 8402091A1
- Authority
- ES
- Spain
- Prior art keywords
- interrupt
- processor
- arrangement
- message
- target processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
There is disclosed an interrupt arrangement for use in a multiprocessing system where it is desired to specifically direct interrupts from one processor to any other processor. The arrangement treats the interrupt signal as a data communication between processors. In this regard, common address space is set aside, on a system basis, for interrupt signals. A sending processor first contends for the system bus and then addresses a message to a specific target processor. The message is received at the target processor over the regular communication channel and stored in a FIFO memory. Interrupt messages filter through the memory in order of arrival and cause interrupts to occur at the target processor. The information at the output of the FIFO memory controls the processing of the interrupt.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/326,908 US4604500A (en) | 1981-12-02 | 1981-12-02 | Multiprocessing interrupt arrangement |
Publications (2)
Publication Number | Publication Date |
---|---|
ES8402091A1 true ES8402091A1 (en) | 1984-02-01 |
ES517861A0 ES517861A0 (en) | 1984-02-01 |
Family
ID=23274259
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES517861A Granted ES517861A0 (en) | 1981-12-02 | 1982-12-01 | IMPROVEMENTS IN MULTI-PROCESS INTERRUPTION DEVICES. |
ES527124A Granted ES527124A0 (en) | 1981-12-02 | 1983-11-08 | PROCEDURE FOR CONTROLLING INTERRUPTIONS BETWEEN PROCESSORS OF A MULTIPLE PROCESSOR SYSTEM |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES527124A Granted ES527124A0 (en) | 1981-12-02 | 1983-11-08 | PROCEDURE FOR CONTROLLING INTERRUPTIONS BETWEEN PROCESSORS OF A MULTIPLE PROCESSOR SYSTEM |
Country Status (13)
Country | Link |
---|---|
US (1) | US4604500A (en) |
JP (1) | JPS58149557A (en) |
AU (1) | AU559645B2 (en) |
BE (1) | BE895188A (en) |
CA (1) | CA1186802A (en) |
DE (1) | DE3243830C2 (en) |
ES (2) | ES517861A0 (en) |
FR (1) | FR2517442B1 (en) |
GB (1) | GB2110442B (en) |
IE (1) | IE54282B1 (en) |
IT (1) | IT1154388B (en) |
NL (1) | NL192228C (en) |
SE (1) | SE8206640L (en) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62184544A (en) * | 1986-02-10 | 1987-08-12 | Nec Corp | Virtual computer system |
JPS62243058A (en) * | 1986-04-15 | 1987-10-23 | Fanuc Ltd | Control method of interruption for multi-processor system |
CA1280216C (en) * | 1986-08-05 | 1991-02-12 | At&T Global Information Solutions Company | Time slot protocol in the transmission of data in a data processing network |
JPS63186360A (en) * | 1987-01-29 | 1988-08-01 | Matsushita Graphic Commun Syst Inc | Multi-cpu device |
FI884026A (en) * | 1987-09-03 | 1989-03-04 | Honeywell Bull | MICROPROCESSORS. |
JPH02503121A (en) * | 1987-10-06 | 1990-09-27 | ベル、コミュニケーションズ、リサーチ、インコーポレーテッド | Selective receiver for each processor in a multiple processor system |
JPH01151350U (en) * | 1988-04-08 | 1989-10-19 | ||
US5283869A (en) * | 1989-07-25 | 1994-02-01 | Allen-Bradley Company, Inc. | Interrupt structure for network interface circuit |
JPH0619759B2 (en) * | 1990-05-21 | 1994-03-16 | 富士ゼロックス株式会社 | Mutual communication method in multiprocessor system |
US5125093A (en) * | 1990-08-14 | 1992-06-23 | Nexgen Microsystems | Interrupt control for multiprocessor computer system |
US5870497A (en) * | 1991-03-15 | 1999-02-09 | C-Cube Microsystems | Decoder for compressed video signals |
US5805841A (en) * | 1991-07-24 | 1998-09-08 | Micron Electronics, Inc. | Symmetric parallel multi-processing bus architeture |
DE69223303T2 (en) * | 1991-09-27 | 1998-06-18 | Sun Microsystems Inc | Method and device for the dynamic allocation of unaddressed interruptions |
US5581770A (en) * | 1992-06-04 | 1996-12-03 | Mitsubishi Denki Kabushiki Kaisha | Floating interruption handling system and method |
US5438677A (en) * | 1992-08-17 | 1995-08-01 | Intel Corporation | Mutual exclusion for computer system |
US5481724A (en) * | 1993-04-06 | 1996-01-02 | International Business Machines Corp. | Peer to peer computer-interrupt handling |
US6170003B1 (en) * | 1993-08-10 | 2001-01-02 | International Computers Limited | Apparatus and method for communicating messages between data processing nodes using remote reading of message queues |
JPH07105023A (en) * | 1993-09-20 | 1995-04-21 | Internatl Business Mach Corp <Ibm> | Method and apparatus for detection of spurious interrupt at inside of data processing system |
CA2123447C (en) * | 1993-09-20 | 1999-02-16 | Richard L. Arndt | Scalable system interrupt structure for a multiprocessing system |
JPH07262152A (en) * | 1994-03-24 | 1995-10-13 | Hitachi Ltd | Computer system |
US5553293A (en) * | 1994-12-09 | 1996-09-03 | International Business Machines Corporation | Interprocessor interrupt processing system |
US5560018A (en) * | 1994-12-16 | 1996-09-24 | International Business Machines Corporation | Providing external interrupt serialization compatibility in a multiprocessing environment for software written to run in a uniprocessor environment |
US5872982A (en) * | 1994-12-28 | 1999-02-16 | Compaq Computer Corporation | Reducing the elapsed time period between an interrupt acknowledge and an interrupt vector |
US5689713A (en) * | 1995-03-31 | 1997-11-18 | Sun Microsystems, Inc. | Method and apparatus for interrupt communication in a packet-switched computer system |
US6105071A (en) * | 1997-04-08 | 2000-08-15 | International Business Machines Corporation | Source and destination initiated interrupt system for message arrival notification |
US6098104A (en) * | 1997-04-08 | 2000-08-01 | International Business Machines Corporation | Source and destination initiated interrupts for message arrival notification, and related data structures |
US6098105A (en) * | 1997-04-08 | 2000-08-01 | International Business Machines Corporation | Source and destination initiated interrupt method for message arrival notification |
US6247091B1 (en) * | 1997-04-28 | 2001-06-12 | International Business Machines Corporation | Method and system for communicating interrupts between nodes of a multinode computer system |
US6192439B1 (en) * | 1998-08-11 | 2001-02-20 | Hewlett-Packard Company | PCI-compliant interrupt steering architecture |
US20020178313A1 (en) * | 2001-03-30 | 2002-11-28 | Gary Scott Paul | Using software interrupts to manage communication between data processors |
US7480697B2 (en) * | 2002-05-28 | 2009-01-20 | International Business Machines Corporation | Method and apparatus using attached hardware subsystem to communicate between attached hosts |
US8984199B2 (en) * | 2003-07-31 | 2015-03-17 | Intel Corporation | Inter-processor interrupts |
US7752371B2 (en) * | 2003-12-29 | 2010-07-06 | Broadcom Corporation | System and method for interrupt abstraction |
US7444449B2 (en) * | 2006-02-09 | 2008-10-28 | Sony Ericsson Mobile Communications Ab | Method, computer program product and computer system for controlling execution of an interruption routine |
US9661521B2 (en) | 2015-01-08 | 2017-05-23 | Freescale Semiconductor, Inc. | Interrupt handling system for cellular communication network |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4320451A (en) * | 1974-04-19 | 1982-03-16 | Honeywell Information Systems Inc. | Extended semaphore architecture |
JPS50156336A (en) * | 1974-06-05 | 1975-12-17 | ||
US4015243A (en) * | 1975-06-02 | 1977-03-29 | Kurpanek Horst G | Multi-processing computer system |
JPS5537680A (en) * | 1978-09-08 | 1980-03-15 | Nec Corp | Decentralized control system |
NL7907179A (en) * | 1979-09-27 | 1981-03-31 | Philips Nv | SIGNAL PROCESSOR DEVICE WITH CONDITIONAL INTERRUPT UNIT AND MULTIPROCESSOR SYSTEM WITH THESE SIGNAL PROCESSOR DEVICES. |
US4271468A (en) * | 1979-11-06 | 1981-06-02 | International Business Machines Corp. | Multiprocessor mechanism for handling channel interrupts |
JPS5835294B2 (en) * | 1980-02-06 | 1983-08-02 | 富士通株式会社 | Multiprocessor processing method |
US4323967A (en) * | 1980-04-15 | 1982-04-06 | Honeywell Information Systems Inc. | Local bus interface for controlling information transfers between units in a central subsystem |
US4414624A (en) * | 1980-11-19 | 1983-11-08 | The United States Of America As Represented By The Secretary Of The Navy | Multiple-microcomputer processing |
US4424561A (en) * | 1980-12-31 | 1984-01-03 | Honeywell Information Systems Inc. | Odd/even bank structure for a cache memory |
US4420806A (en) * | 1981-01-15 | 1983-12-13 | Harris Corporation | Interrupt coupling and monitoring system |
-
1981
- 1981-12-02 US US06/326,908 patent/US4604500A/en not_active Expired - Lifetime
-
1982
- 1982-11-22 SE SE8206640A patent/SE8206640L/en not_active Application Discontinuation
- 1982-11-23 FR FR8219574A patent/FR2517442B1/en not_active Expired
- 1982-11-26 DE DE3243830A patent/DE3243830C2/en not_active Expired - Lifetime
- 1982-11-29 CA CA000416598A patent/CA1186802A/en not_active Expired
- 1982-11-29 AU AU90951/82A patent/AU559645B2/en not_active Expired
- 1982-11-29 GB GB08233921A patent/GB2110442B/en not_active Expired
- 1982-11-30 BE BE0/209604A patent/BE895188A/en unknown
- 1982-12-01 IE IE2859/82A patent/IE54282B1/en unknown
- 1982-12-01 ES ES517861A patent/ES517861A0/en active Granted
- 1982-12-01 IT IT24548/82A patent/IT1154388B/en active
- 1982-12-01 NL NL8204670A patent/NL192228C/en not_active IP Right Cessation
- 1982-12-02 JP JP57210713A patent/JPS58149557A/en active Pending
-
1983
- 1983-11-08 ES ES527124A patent/ES527124A0/en active Granted
Also Published As
Publication number | Publication date |
---|---|
IE54282B1 (en) | 1989-08-16 |
NL8204670A (en) | 1983-07-01 |
NL192228C (en) | 1997-03-04 |
GB2110442B (en) | 1985-07-24 |
FR2517442B1 (en) | 1988-09-16 |
AU559645B2 (en) | 1987-03-19 |
IT8224548A0 (en) | 1982-12-01 |
BE895188A (en) | 1983-03-16 |
DE3243830A1 (en) | 1983-06-16 |
SE8206640D0 (en) | 1982-11-22 |
IT1154388B (en) | 1987-01-21 |
CA1186802A (en) | 1985-05-07 |
SE8206640L (en) | 1983-06-03 |
JPS58149557A (en) | 1983-09-05 |
DE3243830C2 (en) | 1995-03-09 |
US4604500A (en) | 1986-08-05 |
AU9095182A (en) | 1983-06-09 |
NL192228B (en) | 1996-11-01 |
FR2517442A1 (en) | 1983-06-03 |
ES8407348A1 (en) | 1984-09-16 |
ES517861A0 (en) | 1984-02-01 |
IE822859L (en) | 1983-06-02 |
GB2110442A (en) | 1983-06-15 |
ES527124A0 (en) | 1984-09-16 |
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