JPS57176441A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS57176441A JPS57176441A JP56062133A JP6213381A JPS57176441A JP S57176441 A JPS57176441 A JP S57176441A JP 56062133 A JP56062133 A JP 56062133A JP 6213381 A JP6213381 A JP 6213381A JP S57176441 A JPS57176441 A JP S57176441A
- Authority
- JP
- Japan
- Prior art keywords
- control
- circuit
- main
- data transfer
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Abstract
PURPOSE:To decrease the data transfer time, by providing an independent control line between a main device and each slave device, transmitting a start signal and transferring data through a common bus. CONSTITUTION:A main control circuit MC in a main device M' and decentralized control circuits SC1-SCn in slave devices S1'-Sn' are connected to a common bus BUS via a data transmission circuit DS' and data reception circuits DR1'-DRn' corresponding to the circuit DS'. Control lines CL1-CRn are provided between the main device M' and the slave devices S1'-Sn', and the main control circuit MC is connected to the control lines CL1-CLn, and the decentralized control circuits SC1-SCn are connected to corresponding control lines CL1-CLn respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56062133A JPS57176441A (en) | 1981-04-24 | 1981-04-24 | Data transfer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56062133A JPS57176441A (en) | 1981-04-24 | 1981-04-24 | Data transfer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57176441A true JPS57176441A (en) | 1982-10-29 |
Family
ID=13191270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56062133A Pending JPS57176441A (en) | 1981-04-24 | 1981-04-24 | Data transfer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57176441A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59135524A (en) * | 1983-01-24 | 1984-08-03 | Fujitsu Ltd | Loading system of initial program |
JPH08274773A (en) * | 1995-04-03 | 1996-10-18 | Nec Corp | Broadcast communication system by isdn |
-
1981
- 1981-04-24 JP JP56062133A patent/JPS57176441A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59135524A (en) * | 1983-01-24 | 1984-08-03 | Fujitsu Ltd | Loading system of initial program |
JPH08274773A (en) * | 1995-04-03 | 1996-10-18 | Nec Corp | Broadcast communication system by isdn |
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